Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3a58df35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1da177e4 LT |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/init.h> | |
fe27cb35 VP |
31 | #include <linux/smp.h> |
32 | #include <linux/sched.h> | |
1da177e4 | 33 | #include <linux/cpufreq.h> |
d395bf12 | 34 | #include <linux/compiler.h> |
8adcc0c6 | 35 | #include <linux/dmi.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1da177e4 LT |
37 | |
38 | #include <linux/acpi.h> | |
3a58df35 DJ |
39 | #include <linux/io.h> |
40 | #include <linux/delay.h> | |
41 | #include <linux/uaccess.h> | |
42 | ||
1da177e4 LT |
43 | #include <acpi/processor.h> |
44 | ||
dde9f7ba | 45 | #include <asm/msr.h> |
fe27cb35 VP |
46 | #include <asm/processor.h> |
47 | #include <asm/cpufeature.h> | |
fe27cb35 | 48 | |
1da177e4 LT |
49 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
50 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
acd31624 AP |
53 | #define PFX "acpi-cpufreq: " |
54 | ||
dde9f7ba VP |
55 | enum { |
56 | UNDEFINED_CAPABLE = 0, | |
57 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 58 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
59 | SYSTEM_IO_CAPABLE, |
60 | }; | |
61 | ||
62 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 63 | #define AMD_MSR_RANGE (0x7) |
dde9f7ba | 64 | |
615b7300 AP |
65 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
66 | ||
fe27cb35 | 67 | struct acpi_cpufreq_data { |
64be7eed VP |
68 | struct cpufreq_frequency_table *freq_table; |
69 | unsigned int resume; | |
70 | unsigned int cpu_feature; | |
8cfcfd39 | 71 | unsigned int acpi_perf_cpu; |
f4fd3797 | 72 | cpumask_var_t freqdomain_cpus; |
1da177e4 LT |
73 | }; |
74 | ||
50109292 | 75 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 76 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 | 77 | |
3427616b RW |
78 | static inline struct acpi_processor_performance *to_perf_data(struct acpi_cpufreq_data *data) |
79 | { | |
80 | return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); | |
81 | } | |
82 | ||
1da177e4 LT |
83 | static struct cpufreq_driver acpi_cpufreq_driver; |
84 | ||
d395bf12 | 85 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
86 | static struct msr __percpu *msrs; |
87 | ||
88 | static bool boost_state(unsigned int cpu) | |
89 | { | |
90 | u32 lo, hi; | |
91 | u64 msr; | |
92 | ||
93 | switch (boot_cpu_data.x86_vendor) { | |
94 | case X86_VENDOR_INTEL: | |
95 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
96 | msr = lo | ((u64)hi << 32); | |
97 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
98 | case X86_VENDOR_AMD: | |
99 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
100 | msr = lo | ((u64)hi << 32); | |
101 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
102 | } | |
103 | return false; | |
104 | } | |
105 | ||
106 | static void boost_set_msrs(bool enable, const struct cpumask *cpumask) | |
107 | { | |
108 | u32 cpu; | |
109 | u32 msr_addr; | |
110 | u64 msr_mask; | |
111 | ||
112 | switch (boot_cpu_data.x86_vendor) { | |
113 | case X86_VENDOR_INTEL: | |
114 | msr_addr = MSR_IA32_MISC_ENABLE; | |
115 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
116 | break; | |
117 | case X86_VENDOR_AMD: | |
118 | msr_addr = MSR_K7_HWCR; | |
119 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
120 | break; | |
121 | default: | |
122 | return; | |
123 | } | |
124 | ||
125 | rdmsr_on_cpus(cpumask, msr_addr, msrs); | |
126 | ||
127 | for_each_cpu(cpu, cpumask) { | |
128 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
129 | if (enable) | |
130 | reg->q &= ~msr_mask; | |
131 | else | |
132 | reg->q |= msr_mask; | |
133 | } | |
134 | ||
135 | wrmsr_on_cpus(cpumask, msr_addr, msrs); | |
136 | } | |
137 | ||
cfc9c8ed | 138 | static int _store_boost(int val) |
615b7300 | 139 | { |
615b7300 | 140 | get_online_cpus(); |
615b7300 | 141 | boost_set_msrs(val, cpu_online_mask); |
615b7300 | 142 | put_online_cpus(); |
615b7300 AP |
143 | pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); |
144 | ||
cfc9c8ed | 145 | return 0; |
615b7300 AP |
146 | } |
147 | ||
f4fd3797 LT |
148 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
149 | { | |
eb0b3e78 | 150 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 LT |
151 | |
152 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); | |
153 | } | |
154 | ||
155 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
156 | ||
11269ff5 | 157 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
cfc9c8ed LM |
158 | static ssize_t store_boost(const char *buf, size_t count) |
159 | { | |
160 | int ret; | |
161 | unsigned long val = 0; | |
162 | ||
163 | if (!acpi_cpufreq_driver.boost_supported) | |
164 | return -EINVAL; | |
165 | ||
166 | ret = kstrtoul(buf, 10, &val); | |
167 | if (ret || (val > 1)) | |
168 | return -EINVAL; | |
169 | ||
170 | _store_boost((int) val); | |
171 | ||
172 | return count; | |
173 | } | |
174 | ||
11269ff5 AP |
175 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
176 | size_t count) | |
177 | { | |
cfc9c8ed | 178 | return store_boost(buf, count); |
11269ff5 AP |
179 | } |
180 | ||
181 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) | |
182 | { | |
cfc9c8ed | 183 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
184 | } |
185 | ||
59027d35 | 186 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
187 | #endif |
188 | ||
dde9f7ba VP |
189 | static int check_est_cpu(unsigned int cpuid) |
190 | { | |
92cb7612 | 191 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 192 | |
0de51088 | 193 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
194 | } |
195 | ||
3dc9a633 MG |
196 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
197 | { | |
198 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
199 | ||
200 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
201 | } | |
202 | ||
dde9f7ba | 203 | static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) |
fe27cb35 | 204 | { |
64be7eed VP |
205 | struct acpi_processor_performance *perf; |
206 | int i; | |
fe27cb35 | 207 | |
3427616b | 208 | perf = to_perf_data(data); |
fe27cb35 | 209 | |
3a58df35 | 210 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 VP |
211 | if (value == perf->states[i].status) |
212 | return data->freq_table[i].frequency; | |
213 | } | |
214 | return 0; | |
215 | } | |
216 | ||
dde9f7ba VP |
217 | static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) |
218 | { | |
041526f9 | 219 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 220 | struct acpi_processor_performance *perf; |
dde9f7ba | 221 | |
3dc9a633 MG |
222 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
223 | msr &= AMD_MSR_RANGE; | |
224 | else | |
225 | msr &= INTEL_MSR_RANGE; | |
226 | ||
3427616b | 227 | perf = to_perf_data(data); |
a6f6e6e6 | 228 | |
041526f9 SK |
229 | cpufreq_for_each_entry(pos, data->freq_table) |
230 | if (msr == perf->states[pos->driver_data].status) | |
231 | return pos->frequency; | |
dde9f7ba VP |
232 | return data->freq_table[0].frequency; |
233 | } | |
234 | ||
dde9f7ba VP |
235 | static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) |
236 | { | |
237 | switch (data->cpu_feature) { | |
64be7eed | 238 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 239 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba | 240 | return extract_msr(val, data); |
64be7eed | 241 | case SYSTEM_IO_CAPABLE: |
dde9f7ba | 242 | return extract_io(val, data); |
64be7eed | 243 | default: |
dde9f7ba VP |
244 | return 0; |
245 | } | |
246 | } | |
247 | ||
dde9f7ba VP |
248 | struct msr_addr { |
249 | u32 reg; | |
250 | }; | |
251 | ||
fe27cb35 VP |
252 | struct io_addr { |
253 | u16 port; | |
254 | u8 bit_width; | |
255 | }; | |
256 | ||
257 | struct drv_cmd { | |
dde9f7ba | 258 | unsigned int type; |
bfa318ad | 259 | const struct cpumask *mask; |
3a58df35 DJ |
260 | union { |
261 | struct msr_addr msr; | |
262 | struct io_addr io; | |
263 | } addr; | |
fe27cb35 VP |
264 | u32 val; |
265 | }; | |
266 | ||
01599fca AM |
267 | /* Called via smp_call_function_single(), on the target CPU */ |
268 | static void do_drv_read(void *_cmd) | |
1da177e4 | 269 | { |
72859081 | 270 | struct drv_cmd *cmd = _cmd; |
dde9f7ba VP |
271 | u32 h; |
272 | ||
273 | switch (cmd->type) { | |
64be7eed | 274 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 275 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba VP |
276 | rdmsr(cmd->addr.msr.reg, cmd->val, h); |
277 | break; | |
64be7eed | 278 | case SYSTEM_IO_CAPABLE: |
4e581ff1 VP |
279 | acpi_os_read_port((acpi_io_address)cmd->addr.io.port, |
280 | &cmd->val, | |
281 | (u32)cmd->addr.io.bit_width); | |
dde9f7ba | 282 | break; |
64be7eed | 283 | default: |
dde9f7ba VP |
284 | break; |
285 | } | |
fe27cb35 | 286 | } |
1da177e4 | 287 | |
01599fca AM |
288 | /* Called via smp_call_function_many(), on the target CPUs */ |
289 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 290 | { |
72859081 | 291 | struct drv_cmd *cmd = _cmd; |
13424f65 | 292 | u32 lo, hi; |
dde9f7ba VP |
293 | |
294 | switch (cmd->type) { | |
64be7eed | 295 | case SYSTEM_INTEL_MSR_CAPABLE: |
13424f65 VP |
296 | rdmsr(cmd->addr.msr.reg, lo, hi); |
297 | lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); | |
298 | wrmsr(cmd->addr.msr.reg, lo, hi); | |
dde9f7ba | 299 | break; |
3dc9a633 MG |
300 | case SYSTEM_AMD_MSR_CAPABLE: |
301 | wrmsr(cmd->addr.msr.reg, cmd->val, 0); | |
302 | break; | |
64be7eed | 303 | case SYSTEM_IO_CAPABLE: |
4e581ff1 VP |
304 | acpi_os_write_port((acpi_io_address)cmd->addr.io.port, |
305 | cmd->val, | |
306 | (u32)cmd->addr.io.bit_width); | |
dde9f7ba | 307 | break; |
64be7eed | 308 | default: |
dde9f7ba VP |
309 | break; |
310 | } | |
fe27cb35 | 311 | } |
1da177e4 | 312 | |
95dd7227 | 313 | static void drv_read(struct drv_cmd *cmd) |
fe27cb35 | 314 | { |
4a28395d | 315 | int err; |
fe27cb35 VP |
316 | cmd->val = 0; |
317 | ||
4a28395d AM |
318 | err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1); |
319 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
fe27cb35 VP |
320 | } |
321 | ||
322 | static void drv_write(struct drv_cmd *cmd) | |
323 | { | |
ea34f43a LT |
324 | int this_cpu; |
325 | ||
326 | this_cpu = get_cpu(); | |
327 | if (cpumask_test_cpu(this_cpu, cmd->mask)) | |
328 | do_drv_write(cmd); | |
01599fca | 329 | smp_call_function_many(cmd->mask, do_drv_write, cmd, 1); |
ea34f43a | 330 | put_cpu(); |
fe27cb35 | 331 | } |
1da177e4 | 332 | |
eb0b3e78 PX |
333 | static u32 |
334 | get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) | |
fe27cb35 | 335 | { |
64be7eed VP |
336 | struct acpi_processor_performance *perf; |
337 | struct drv_cmd cmd; | |
1da177e4 | 338 | |
4d8bb537 | 339 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 340 | return 0; |
1da177e4 | 341 | |
eb0b3e78 | 342 | switch (data->cpu_feature) { |
dde9f7ba VP |
343 | case SYSTEM_INTEL_MSR_CAPABLE: |
344 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
8673b83b | 345 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; |
dde9f7ba | 346 | break; |
3dc9a633 MG |
347 | case SYSTEM_AMD_MSR_CAPABLE: |
348 | cmd.type = SYSTEM_AMD_MSR_CAPABLE; | |
8673b83b | 349 | cmd.addr.msr.reg = MSR_AMD_PERF_CTL; |
3dc9a633 | 350 | break; |
dde9f7ba VP |
351 | case SYSTEM_IO_CAPABLE: |
352 | cmd.type = SYSTEM_IO_CAPABLE; | |
3427616b | 353 | perf = to_perf_data(data); |
dde9f7ba VP |
354 | cmd.addr.io.port = perf->control_register.address; |
355 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
356 | break; | |
357 | default: | |
358 | return 0; | |
359 | } | |
360 | ||
bfa318ad | 361 | cmd.mask = mask; |
fe27cb35 | 362 | drv_read(&cmd); |
1da177e4 | 363 | |
2d06d8c4 | 364 | pr_debug("get_cur_val = %u\n", cmd.val); |
fe27cb35 VP |
365 | |
366 | return cmd.val; | |
367 | } | |
1da177e4 | 368 | |
fe27cb35 VP |
369 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
370 | { | |
eb0b3e78 PX |
371 | struct acpi_cpufreq_data *data; |
372 | struct cpufreq_policy *policy; | |
64be7eed | 373 | unsigned int freq; |
e56a727b | 374 | unsigned int cached_freq; |
fe27cb35 | 375 | |
2d06d8c4 | 376 | pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); |
fe27cb35 | 377 | |
eb0b3e78 PX |
378 | policy = cpufreq_cpu_get(cpu); |
379 | if (unlikely(!policy)) | |
380 | return 0; | |
381 | ||
382 | data = policy->driver_data; | |
383 | cpufreq_cpu_put(policy); | |
3427616b | 384 | if (unlikely(!data || !data->freq_table)) |
fe27cb35 | 385 | return 0; |
1da177e4 | 386 | |
3427616b | 387 | cached_freq = data->freq_table[to_perf_data(data)->state].frequency; |
eb0b3e78 | 388 | freq = extract_freq(get_cur_val(cpumask_of(cpu), data), data); |
e56a727b VP |
389 | if (freq != cached_freq) { |
390 | /* | |
391 | * The dreaded BIOS frequency change behind our back. | |
392 | * Force set the frequency on next target call. | |
393 | */ | |
394 | data->resume = 1; | |
395 | } | |
396 | ||
2d06d8c4 | 397 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 398 | |
fe27cb35 | 399 | return freq; |
1da177e4 LT |
400 | } |
401 | ||
72859081 | 402 | static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq, |
64be7eed | 403 | struct acpi_cpufreq_data *data) |
fe27cb35 | 404 | { |
64be7eed VP |
405 | unsigned int cur_freq; |
406 | unsigned int i; | |
1da177e4 | 407 | |
3a58df35 | 408 | for (i = 0; i < 100; i++) { |
eb0b3e78 | 409 | cur_freq = extract_freq(get_cur_val(mask, data), data); |
fe27cb35 VP |
410 | if (cur_freq == freq) |
411 | return 1; | |
412 | udelay(10); | |
413 | } | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 418 | unsigned int index) |
1da177e4 | 419 | { |
eb0b3e78 | 420 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 421 | struct acpi_processor_performance *perf; |
64be7eed | 422 | struct drv_cmd cmd; |
8edc59d9 | 423 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 424 | int result = 0; |
fe27cb35 | 425 | |
3427616b | 426 | if (unlikely(data == NULL || data->freq_table == NULL)) { |
fe27cb35 VP |
427 | return -ENODEV; |
428 | } | |
1da177e4 | 429 | |
3427616b | 430 | perf = to_perf_data(data); |
9c0ebcf7 | 431 | next_perf_state = data->freq_table[index].driver_data; |
7650b281 | 432 | if (perf->state == next_perf_state) { |
fe27cb35 | 433 | if (unlikely(data->resume)) { |
2d06d8c4 | 434 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 435 | next_perf_state); |
fe27cb35 VP |
436 | data->resume = 0; |
437 | } else { | |
2d06d8c4 | 438 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 439 | next_perf_state); |
4d8bb537 | 440 | goto out; |
fe27cb35 | 441 | } |
09b4d1ee VP |
442 | } |
443 | ||
64be7eed VP |
444 | switch (data->cpu_feature) { |
445 | case SYSTEM_INTEL_MSR_CAPABLE: | |
446 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
447 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; | |
13424f65 | 448 | cmd.val = (u32) perf->states[next_perf_state].control; |
64be7eed | 449 | break; |
3dc9a633 MG |
450 | case SYSTEM_AMD_MSR_CAPABLE: |
451 | cmd.type = SYSTEM_AMD_MSR_CAPABLE; | |
452 | cmd.addr.msr.reg = MSR_AMD_PERF_CTL; | |
453 | cmd.val = (u32) perf->states[next_perf_state].control; | |
454 | break; | |
64be7eed VP |
455 | case SYSTEM_IO_CAPABLE: |
456 | cmd.type = SYSTEM_IO_CAPABLE; | |
457 | cmd.addr.io.port = perf->control_register.address; | |
458 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
459 | cmd.val = (u32) perf->states[next_perf_state].control; | |
460 | break; | |
461 | default: | |
4d8bb537 MT |
462 | result = -ENODEV; |
463 | goto out; | |
64be7eed | 464 | } |
09b4d1ee | 465 | |
4d8bb537 | 466 | /* cpufreq holds the hotplug lock, so we are safe from here on */ |
fe27cb35 | 467 | if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) |
bfa318ad | 468 | cmd.mask = policy->cpus; |
fe27cb35 | 469 | else |
bfa318ad | 470 | cmd.mask = cpumask_of(policy->cpu); |
09b4d1ee | 471 | |
fe27cb35 | 472 | drv_write(&cmd); |
09b4d1ee | 473 | |
fe27cb35 | 474 | if (acpi_pstate_strict) { |
d4019f0a VK |
475 | if (!check_freqs(cmd.mask, data->freq_table[index].frequency, |
476 | data)) { | |
2d06d8c4 | 477 | pr_debug("acpi_cpufreq_target failed (%d)\n", |
64be7eed | 478 | policy->cpu); |
4d8bb537 | 479 | result = -EAGAIN; |
09b4d1ee VP |
480 | } |
481 | } | |
482 | ||
e15d8309 VK |
483 | if (!result) |
484 | perf->state = next_perf_state; | |
fe27cb35 | 485 | |
4d8bb537 | 486 | out: |
fe27cb35 | 487 | return result; |
1da177e4 LT |
488 | } |
489 | ||
1da177e4 | 490 | static unsigned long |
64be7eed | 491 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 492 | { |
3427616b | 493 | struct acpi_processor_performance *perf; |
09b4d1ee | 494 | |
3427616b | 495 | perf = to_perf_data(data); |
1da177e4 LT |
496 | if (cpu_khz) { |
497 | /* search the closest match to cpu_khz */ | |
498 | unsigned int i; | |
499 | unsigned long freq; | |
09b4d1ee | 500 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 501 | |
3a58df35 | 502 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 503 | freq = freqn; |
95dd7227 | 504 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 505 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 506 | perf->state = i; |
64be7eed | 507 | return freq; |
1da177e4 LT |
508 | } |
509 | } | |
95dd7227 | 510 | perf->state = perf->state_count-1; |
64be7eed | 511 | return freqn; |
09b4d1ee | 512 | } else { |
1da177e4 | 513 | /* assume CPU is at P0... */ |
09b4d1ee VP |
514 | perf->state = 0; |
515 | return perf->states[0].core_frequency * 1000; | |
516 | } | |
1da177e4 LT |
517 | } |
518 | ||
2fdf66b4 RR |
519 | static void free_acpi_perf_data(void) |
520 | { | |
521 | unsigned int i; | |
522 | ||
523 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
524 | for_each_possible_cpu(i) | |
525 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
526 | ->shared_cpu_map); | |
527 | free_percpu(acpi_perf_data); | |
528 | } | |
529 | ||
615b7300 AP |
530 | static int boost_notify(struct notifier_block *nb, unsigned long action, |
531 | void *hcpu) | |
532 | { | |
533 | unsigned cpu = (long)hcpu; | |
534 | const struct cpumask *cpumask; | |
535 | ||
536 | cpumask = get_cpu_mask(cpu); | |
537 | ||
538 | /* | |
539 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
540 | * this cpu cannot block the remaining ones from boosting. On | |
541 | * the CPU_UP path we simply keep the boost-disable flag in | |
542 | * sync with the current global state. | |
543 | */ | |
544 | ||
545 | switch (action) { | |
546 | case CPU_UP_PREPARE: | |
547 | case CPU_UP_PREPARE_FROZEN: | |
cfc9c8ed | 548 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); |
615b7300 AP |
549 | break; |
550 | ||
551 | case CPU_DOWN_PREPARE: | |
552 | case CPU_DOWN_PREPARE_FROZEN: | |
553 | boost_set_msrs(1, cpumask); | |
554 | break; | |
555 | ||
556 | default: | |
557 | break; | |
558 | } | |
559 | ||
560 | return NOTIFY_OK; | |
561 | } | |
562 | ||
563 | ||
564 | static struct notifier_block boost_nb = { | |
565 | .notifier_call = boost_notify, | |
566 | }; | |
567 | ||
09b4d1ee VP |
568 | /* |
569 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
570 | * | |
571 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
572 | * in order to determine correct frequency and voltage pairings. We can | |
573 | * do _PDC and _PSD and find out the processor dependency for the | |
574 | * actual init that will happen later... | |
575 | */ | |
50109292 | 576 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 577 | { |
2fdf66b4 | 578 | unsigned int i; |
2d06d8c4 | 579 | pr_debug("acpi_cpufreq_early_init\n"); |
09b4d1ee | 580 | |
50109292 FY |
581 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
582 | if (!acpi_perf_data) { | |
2d06d8c4 | 583 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 584 | return -ENOMEM; |
09b4d1ee | 585 | } |
2fdf66b4 | 586 | for_each_possible_cpu(i) { |
eaa95840 | 587 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
588 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
589 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
590 | |
591 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
592 | free_acpi_perf_data(); | |
593 | return -ENOMEM; | |
594 | } | |
595 | } | |
09b4d1ee VP |
596 | |
597 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
598 | acpi_processor_preregister_performance(acpi_perf_data); |
599 | return 0; | |
09b4d1ee VP |
600 | } |
601 | ||
95625b8f | 602 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
603 | /* |
604 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
605 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
606 | * detected, this has a side effect of making CPU run at a different speed | |
607 | * than OS intended it to run at. Detect it and handle it cleanly. | |
608 | */ | |
609 | static int bios_with_sw_any_bug; | |
610 | ||
1855256c | 611 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
612 | { |
613 | bios_with_sw_any_bug = 1; | |
614 | return 0; | |
615 | } | |
616 | ||
1855256c | 617 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
618 | { |
619 | .callback = sw_any_bug_found, | |
620 | .ident = "Supermicro Server X6DLP", | |
621 | .matches = { | |
622 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
623 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
624 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
625 | }, | |
626 | }, | |
627 | { } | |
628 | }; | |
1a8e42fa PB |
629 | |
630 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
631 | { | |
293afe44 JV |
632 | /* Intel Xeon Processor 7100 Series Specification Update |
633 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
634 | * AL30: A Machine Check Exception (MCE) Occurring during an |
635 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 636 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
637 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
638 | if ((c->x86 == 15) && | |
639 | (c->x86_model == 6) && | |
293afe44 JV |
640 | (c->x86_mask == 8)) { |
641 | printk(KERN_INFO "acpi-cpufreq: Intel(R) " | |
642 | "Xeon(R) 7100 Errata AL30, processors may " | |
643 | "lock up on frequency changes: disabling " | |
644 | "acpi-cpufreq.\n"); | |
1a8e42fa | 645 | return -ENODEV; |
293afe44 | 646 | } |
1a8e42fa PB |
647 | } |
648 | return 0; | |
649 | } | |
95625b8f | 650 | #endif |
8adcc0c6 | 651 | |
64be7eed | 652 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 653 | { |
64be7eed VP |
654 | unsigned int i; |
655 | unsigned int valid_states = 0; | |
656 | unsigned int cpu = policy->cpu; | |
657 | struct acpi_cpufreq_data *data; | |
64be7eed | 658 | unsigned int result = 0; |
92cb7612 | 659 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 660 | struct acpi_processor_performance *perf; |
293afe44 JV |
661 | #ifdef CONFIG_SMP |
662 | static int blacklisted; | |
663 | #endif | |
1da177e4 | 664 | |
2d06d8c4 | 665 | pr_debug("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 666 | |
1a8e42fa | 667 | #ifdef CONFIG_SMP |
293afe44 JV |
668 | if (blacklisted) |
669 | return blacklisted; | |
670 | blacklisted = acpi_cpufreq_blacklist(c); | |
671 | if (blacklisted) | |
672 | return blacklisted; | |
1a8e42fa PB |
673 | #endif |
674 | ||
d5b73cd8 | 675 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 676 | if (!data) |
64be7eed | 677 | return -ENOMEM; |
1da177e4 | 678 | |
f4fd3797 LT |
679 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
680 | result = -ENOMEM; | |
681 | goto err_free; | |
682 | } | |
683 | ||
3427616b | 684 | perf = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 685 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 686 | policy->driver_data = data; |
1da177e4 | 687 | |
95dd7227 | 688 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 689 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 690 | |
3427616b | 691 | result = acpi_processor_register_performance(perf, cpu); |
1da177e4 | 692 | if (result) |
f4fd3797 | 693 | goto err_free_mask; |
1da177e4 | 694 | |
09b4d1ee | 695 | policy->shared_type = perf->shared_type; |
95dd7227 | 696 | |
46f18e3a | 697 | /* |
95dd7227 | 698 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
699 | * coordination is required. |
700 | */ | |
701 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 702 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 703 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 704 | } |
f4fd3797 | 705 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
706 | |
707 | #ifdef CONFIG_SMP | |
708 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 709 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 710 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 711 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 712 | } |
acd31624 AP |
713 | |
714 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
715 | cpumask_clear(policy->cpus); | |
716 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
717 | cpumask_copy(data->freqdomain_cpus, |
718 | topology_sibling_cpumask(cpu)); | |
acd31624 AP |
719 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
720 | pr_info_once(PFX "overriding BIOS provided _PSD data\n"); | |
721 | } | |
8adcc0c6 | 722 | #endif |
09b4d1ee | 723 | |
1da177e4 | 724 | /* capability check */ |
09b4d1ee | 725 | if (perf->state_count <= 1) { |
2d06d8c4 | 726 | pr_debug("No P-States\n"); |
1da177e4 LT |
727 | result = -ENODEV; |
728 | goto err_unreg; | |
729 | } | |
09b4d1ee | 730 | |
fe27cb35 VP |
731 | if (perf->control_register.space_id != perf->status_register.space_id) { |
732 | result = -ENODEV; | |
733 | goto err_unreg; | |
734 | } | |
735 | ||
736 | switch (perf->control_register.space_id) { | |
64be7eed | 737 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
738 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
739 | boot_cpu_data.x86 == 0xf) { | |
740 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
741 | result = -ENODEV; | |
742 | goto err_unreg; | |
743 | } | |
2d06d8c4 | 744 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba VP |
745 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
746 | break; | |
64be7eed | 747 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 748 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
749 | if (check_est_cpu(cpu)) { |
750 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
751 | break; | |
dde9f7ba | 752 | } |
3dc9a633 MG |
753 | if (check_amd_hwpstate_cpu(cpu)) { |
754 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
755 | break; | |
756 | } | |
757 | result = -ENODEV; | |
758 | goto err_unreg; | |
64be7eed | 759 | default: |
2d06d8c4 | 760 | pr_debug("Unknown addr space %d\n", |
64be7eed | 761 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
762 | result = -ENODEV; |
763 | goto err_unreg; | |
764 | } | |
765 | ||
71508a1f | 766 | data->freq_table = kzalloc(sizeof(*data->freq_table) * |
95dd7227 | 767 | (perf->state_count+1), GFP_KERNEL); |
1da177e4 LT |
768 | if (!data->freq_table) { |
769 | result = -ENOMEM; | |
770 | goto err_unreg; | |
771 | } | |
772 | ||
773 | /* detect transition latency */ | |
774 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 775 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
776 | if ((perf->states[i].transition_latency * 1000) > |
777 | policy->cpuinfo.transition_latency) | |
778 | policy->cpuinfo.transition_latency = | |
779 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 780 | } |
1da177e4 | 781 | |
a59d1637 PV |
782 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
783 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
784 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 785 | policy->cpuinfo.transition_latency = 20 * 1000; |
61c8c67e JP |
786 | printk_once(KERN_INFO |
787 | "P-state transition latency capped at 20 uS\n"); | |
a59d1637 PV |
788 | } |
789 | ||
1da177e4 | 790 | /* table init */ |
3a58df35 DJ |
791 | for (i = 0; i < perf->state_count; i++) { |
792 | if (i > 0 && perf->states[i].core_frequency >= | |
3cdf552b | 793 | data->freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
794 | continue; |
795 | ||
50701588 | 796 | data->freq_table[valid_states].driver_data = i; |
fe27cb35 | 797 | data->freq_table[valid_states].frequency = |
64be7eed | 798 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 799 | valid_states++; |
1da177e4 | 800 | } |
3d4a7ef3 | 801 | data->freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
8edc59d9 | 802 | perf->state = 0; |
1da177e4 | 803 | |
776b57be | 804 | result = cpufreq_table_validate_and_show(policy, data->freq_table); |
95dd7227 | 805 | if (result) |
1da177e4 | 806 | goto err_freqfree; |
1da177e4 | 807 | |
d876dfbb TR |
808 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) |
809 | printk(KERN_WARNING FW_WARN "P-state 0 is not max freq\n"); | |
810 | ||
a507ac4b | 811 | switch (perf->control_register.space_id) { |
64be7eed | 812 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
813 | /* |
814 | * The core will not set policy->cur, because | |
815 | * cpufreq_driver->get is NULL, so we need to set it here. | |
816 | * However, we have to guess it, because the current speed is | |
817 | * unknown and not detectable via IO ports. | |
818 | */ | |
dde9f7ba VP |
819 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
820 | break; | |
64be7eed | 821 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 822 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 823 | break; |
64be7eed | 824 | default: |
dde9f7ba VP |
825 | break; |
826 | } | |
827 | ||
1da177e4 LT |
828 | /* notify BIOS that we exist */ |
829 | acpi_processor_notify_smm(THIS_MODULE); | |
830 | ||
2d06d8c4 | 831 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 832 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 833 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 834 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
835 | (u32) perf->states[i].core_frequency, |
836 | (u32) perf->states[i].power, | |
837 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 838 | |
4b31e774 DB |
839 | /* |
840 | * the first call to ->target() should result in us actually | |
841 | * writing something to the appropriate registers. | |
842 | */ | |
843 | data->resume = 1; | |
64be7eed | 844 | |
fe27cb35 | 845 | return result; |
1da177e4 | 846 | |
95dd7227 | 847 | err_freqfree: |
1da177e4 | 848 | kfree(data->freq_table); |
95dd7227 | 849 | err_unreg: |
b2f8dc4c | 850 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
851 | err_free_mask: |
852 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 853 | err_free: |
1da177e4 | 854 | kfree(data); |
eb0b3e78 | 855 | policy->driver_data = NULL; |
1da177e4 | 856 | |
64be7eed | 857 | return result; |
1da177e4 LT |
858 | } |
859 | ||
64be7eed | 860 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 861 | { |
eb0b3e78 | 862 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 863 | |
2d06d8c4 | 864 | pr_debug("acpi_cpufreq_cpu_exit\n"); |
1da177e4 LT |
865 | |
866 | if (data) { | |
eb0b3e78 | 867 | policy->driver_data = NULL; |
b2f8dc4c | 868 | acpi_processor_unregister_performance(data->acpi_perf_cpu); |
f4fd3797 | 869 | free_cpumask_var(data->freqdomain_cpus); |
dab5fff1 | 870 | kfree(data->freq_table); |
1da177e4 LT |
871 | kfree(data); |
872 | } | |
873 | ||
64be7eed | 874 | return 0; |
1da177e4 LT |
875 | } |
876 | ||
64be7eed | 877 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 878 | { |
eb0b3e78 | 879 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 880 | |
2d06d8c4 | 881 | pr_debug("acpi_cpufreq_resume\n"); |
1da177e4 LT |
882 | |
883 | data->resume = 1; | |
884 | ||
64be7eed | 885 | return 0; |
1da177e4 LT |
886 | } |
887 | ||
64be7eed | 888 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 889 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 890 | &freqdomain_cpus, |
f56c50e3 RW |
891 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
892 | &cpb, | |
893 | #endif | |
1da177e4 LT |
894 | NULL, |
895 | }; | |
896 | ||
897 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 898 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 899 | .target_index = acpi_cpufreq_target, |
e2f74f35 TR |
900 | .bios_limit = acpi_processor_get_bios_limit, |
901 | .init = acpi_cpufreq_cpu_init, | |
902 | .exit = acpi_cpufreq_cpu_exit, | |
903 | .resume = acpi_cpufreq_resume, | |
904 | .name = "acpi-cpufreq", | |
e2f74f35 | 905 | .attr = acpi_cpufreq_attr, |
cfc9c8ed | 906 | .set_boost = _store_boost, |
1da177e4 LT |
907 | }; |
908 | ||
615b7300 AP |
909 | static void __init acpi_cpufreq_boost_init(void) |
910 | { | |
911 | if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { | |
912 | msrs = msrs_alloc(); | |
913 | ||
914 | if (!msrs) | |
915 | return; | |
916 | ||
cfc9c8ed LM |
917 | acpi_cpufreq_driver.boost_supported = true; |
918 | acpi_cpufreq_driver.boost_enabled = boost_state(0); | |
0197fbd2 SB |
919 | |
920 | cpu_notifier_register_begin(); | |
615b7300 AP |
921 | |
922 | /* Force all MSRs to the same value */ | |
cfc9c8ed LM |
923 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, |
924 | cpu_online_mask); | |
615b7300 | 925 | |
0197fbd2 | 926 | __register_cpu_notifier(&boost_nb); |
615b7300 | 927 | |
0197fbd2 | 928 | cpu_notifier_register_done(); |
cfc9c8ed | 929 | } |
615b7300 AP |
930 | } |
931 | ||
eb8c68ef | 932 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 933 | { |
615b7300 AP |
934 | if (msrs) { |
935 | unregister_cpu_notifier(&boost_nb); | |
936 | ||
937 | msrs_free(msrs); | |
938 | msrs = NULL; | |
939 | } | |
940 | } | |
941 | ||
64be7eed | 942 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 943 | { |
50109292 FY |
944 | int ret; |
945 | ||
75c07581 RW |
946 | if (acpi_disabled) |
947 | return -ENODEV; | |
948 | ||
8a61e12e YL |
949 | /* don't keep reloading if cpufreq_driver exists */ |
950 | if (cpufreq_get_current_driver()) | |
75c07581 | 951 | return -EEXIST; |
ee297533 | 952 | |
2d06d8c4 | 953 | pr_debug("acpi_cpufreq_init\n"); |
1da177e4 | 954 | |
50109292 FY |
955 | ret = acpi_cpufreq_early_init(); |
956 | if (ret) | |
957 | return ret; | |
09b4d1ee | 958 | |
11269ff5 AP |
959 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
960 | /* this is a sysfs file with a strange name and an even stranger | |
961 | * semantic - per CPU instantiation, but system global effect. | |
962 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
963 | * only if configured. This is considered legacy code, which | |
964 | * will probably be removed at some point in the future. | |
965 | */ | |
f56c50e3 RW |
966 | if (!check_amd_hwpstate_cpu(0)) { |
967 | struct freq_attr **attr; | |
11269ff5 | 968 | |
f56c50e3 | 969 | pr_debug("CPB unsupported, do not expose it\n"); |
11269ff5 | 970 | |
f56c50e3 RW |
971 | for (attr = acpi_cpufreq_attr; *attr; attr++) |
972 | if (*attr == &cpb) { | |
973 | *attr = NULL; | |
974 | break; | |
975 | } | |
11269ff5 AP |
976 | } |
977 | #endif | |
cfc9c8ed | 978 | acpi_cpufreq_boost_init(); |
11269ff5 | 979 | |
847aef6f | 980 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 981 | if (ret) { |
2fdf66b4 | 982 | free_acpi_perf_data(); |
eb8c68ef KRW |
983 | acpi_cpufreq_boost_exit(); |
984 | } | |
847aef6f | 985 | return ret; |
1da177e4 LT |
986 | } |
987 | ||
64be7eed | 988 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 989 | { |
2d06d8c4 | 990 | pr_debug("acpi_cpufreq_exit\n"); |
1da177e4 | 991 | |
615b7300 AP |
992 | acpi_cpufreq_boost_exit(); |
993 | ||
1da177e4 LT |
994 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
995 | ||
50f4ddd4 | 996 | free_acpi_perf_data(); |
1da177e4 LT |
997 | } |
998 | ||
d395bf12 | 999 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 1000 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
1001 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
1002 | "performed during frequency changes."); | |
1da177e4 LT |
1003 | |
1004 | late_initcall(acpi_cpufreq_init); | |
1005 | module_exit(acpi_cpufreq_exit); | |
1006 | ||
efa17194 MG |
1007 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
1008 | X86_FEATURE_MATCH(X86_FEATURE_ACPI), | |
1009 | X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), | |
1010 | {} | |
1011 | }; | |
1012 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1013 | ||
c655affb RW |
1014 | static const struct acpi_device_id processor_device_ids[] = { |
1015 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
1016 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1017 | {}, | |
1018 | }; | |
1019 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1020 | ||
1da177e4 | 1021 | MODULE_ALIAS("acpi"); |