Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3a58df35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1c5864e2 JP |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
fe27cb35 VP |
33 | #include <linux/smp.h> |
34 | #include <linux/sched.h> | |
1da177e4 | 35 | #include <linux/cpufreq.h> |
d395bf12 | 36 | #include <linux/compiler.h> |
8adcc0c6 | 37 | #include <linux/dmi.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
1da177e4 LT |
39 | |
40 | #include <linux/acpi.h> | |
3a58df35 DJ |
41 | #include <linux/io.h> |
42 | #include <linux/delay.h> | |
43 | #include <linux/uaccess.h> | |
44 | ||
1da177e4 LT |
45 | #include <acpi/processor.h> |
46 | ||
dde9f7ba | 47 | #include <asm/msr.h> |
fe27cb35 VP |
48 | #include <asm/processor.h> |
49 | #include <asm/cpufeature.h> | |
fe27cb35 | 50 | |
1da177e4 LT |
51 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
52 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
53 | MODULE_LICENSE("GPL"); | |
54 | ||
dde9f7ba VP |
55 | enum { |
56 | UNDEFINED_CAPABLE = 0, | |
57 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 58 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
59 | SYSTEM_IO_CAPABLE, |
60 | }; | |
61 | ||
62 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 63 | #define AMD_MSR_RANGE (0x7) |
cc9690cf | 64 | #define HYGON_MSR_RANGE (0x7) |
dde9f7ba | 65 | |
615b7300 AP |
66 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
67 | ||
fe27cb35 | 68 | struct acpi_cpufreq_data { |
64be7eed VP |
69 | unsigned int resume; |
70 | unsigned int cpu_feature; | |
8cfcfd39 | 71 | unsigned int acpi_perf_cpu; |
f4fd3797 | 72 | cpumask_var_t freqdomain_cpus; |
ed757a2c RW |
73 | void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val); |
74 | u32 (*cpu_freq_read)(struct acpi_pct_register *reg); | |
1da177e4 LT |
75 | }; |
76 | ||
50109292 | 77 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 78 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 | 79 | |
3427616b RW |
80 | static inline struct acpi_processor_performance *to_perf_data(struct acpi_cpufreq_data *data) |
81 | { | |
82 | return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); | |
83 | } | |
84 | ||
1da177e4 LT |
85 | static struct cpufreq_driver acpi_cpufreq_driver; |
86 | ||
d395bf12 | 87 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
88 | |
89 | static bool boost_state(unsigned int cpu) | |
90 | { | |
91 | u32 lo, hi; | |
92 | u64 msr; | |
93 | ||
94 | switch (boot_cpu_data.x86_vendor) { | |
95 | case X86_VENDOR_INTEL: | |
96 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
97 | msr = lo | ((u64)hi << 32); | |
98 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
cc9690cf | 99 | case X86_VENDOR_HYGON: |
615b7300 AP |
100 | case X86_VENDOR_AMD: |
101 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
102 | msr = lo | ((u64)hi << 32); | |
103 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
104 | } | |
105 | return false; | |
106 | } | |
107 | ||
a3605c46 | 108 | static int boost_set_msr(bool enable) |
615b7300 | 109 | { |
615b7300 | 110 | u32 msr_addr; |
a3605c46 | 111 | u64 msr_mask, val; |
615b7300 AP |
112 | |
113 | switch (boot_cpu_data.x86_vendor) { | |
114 | case X86_VENDOR_INTEL: | |
115 | msr_addr = MSR_IA32_MISC_ENABLE; | |
116 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
117 | break; | |
cc9690cf | 118 | case X86_VENDOR_HYGON: |
615b7300 AP |
119 | case X86_VENDOR_AMD: |
120 | msr_addr = MSR_K7_HWCR; | |
121 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
122 | break; | |
123 | default: | |
a3605c46 | 124 | return -EINVAL; |
615b7300 AP |
125 | } |
126 | ||
a3605c46 | 127 | rdmsrl(msr_addr, val); |
615b7300 | 128 | |
a3605c46 SAS |
129 | if (enable) |
130 | val &= ~msr_mask; | |
131 | else | |
132 | val |= msr_mask; | |
615b7300 | 133 | |
a3605c46 SAS |
134 | wrmsrl(msr_addr, val); |
135 | return 0; | |
136 | } | |
137 | ||
138 | static void boost_set_msr_each(void *p_en) | |
139 | { | |
140 | bool enable = (bool) p_en; | |
141 | ||
142 | boost_set_msr(enable); | |
615b7300 AP |
143 | } |
144 | ||
17135782 | 145 | static int set_boost(int val) |
615b7300 | 146 | { |
615b7300 | 147 | get_online_cpus(); |
a3605c46 | 148 | on_each_cpu(boost_set_msr_each, (void *)(long)val, 1); |
615b7300 | 149 | put_online_cpus(); |
615b7300 AP |
150 | pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); |
151 | ||
cfc9c8ed | 152 | return 0; |
615b7300 AP |
153 | } |
154 | ||
f4fd3797 LT |
155 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
156 | { | |
eb0b3e78 | 157 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 | 158 | |
e2530367 SP |
159 | if (unlikely(!data)) |
160 | return -ENODEV; | |
161 | ||
f4fd3797 LT |
162 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); |
163 | } | |
164 | ||
165 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
166 | ||
11269ff5 | 167 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
17135782 RW |
168 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
169 | size_t count) | |
cfc9c8ed LM |
170 | { |
171 | int ret; | |
17135782 | 172 | unsigned int val = 0; |
cfc9c8ed | 173 | |
7a6c79f2 | 174 | if (!acpi_cpufreq_driver.set_boost) |
cfc9c8ed LM |
175 | return -EINVAL; |
176 | ||
17135782 RW |
177 | ret = kstrtouint(buf, 10, &val); |
178 | if (ret || val > 1) | |
cfc9c8ed LM |
179 | return -EINVAL; |
180 | ||
17135782 | 181 | set_boost(val); |
cfc9c8ed LM |
182 | |
183 | return count; | |
184 | } | |
185 | ||
11269ff5 AP |
186 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) |
187 | { | |
cfc9c8ed | 188 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
189 | } |
190 | ||
59027d35 | 191 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
192 | #endif |
193 | ||
dde9f7ba VP |
194 | static int check_est_cpu(unsigned int cpuid) |
195 | { | |
92cb7612 | 196 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 197 | |
0de51088 | 198 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
199 | } |
200 | ||
3dc9a633 MG |
201 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
202 | { | |
203 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
204 | ||
205 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
206 | } | |
207 | ||
8cee1eed | 208 | static unsigned extract_io(struct cpufreq_policy *policy, u32 value) |
fe27cb35 | 209 | { |
8cee1eed | 210 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
211 | struct acpi_processor_performance *perf; |
212 | int i; | |
fe27cb35 | 213 | |
3427616b | 214 | perf = to_perf_data(data); |
fe27cb35 | 215 | |
3a58df35 | 216 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 | 217 | if (value == perf->states[i].status) |
8cee1eed | 218 | return policy->freq_table[i].frequency; |
fe27cb35 VP |
219 | } |
220 | return 0; | |
221 | } | |
222 | ||
8cee1eed | 223 | static unsigned extract_msr(struct cpufreq_policy *policy, u32 msr) |
dde9f7ba | 224 | { |
8cee1eed | 225 | struct acpi_cpufreq_data *data = policy->driver_data; |
041526f9 | 226 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 227 | struct acpi_processor_performance *perf; |
dde9f7ba | 228 | |
3dc9a633 MG |
229 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
230 | msr &= AMD_MSR_RANGE; | |
cc9690cf PW |
231 | else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) |
232 | msr &= HYGON_MSR_RANGE; | |
3dc9a633 MG |
233 | else |
234 | msr &= INTEL_MSR_RANGE; | |
235 | ||
3427616b | 236 | perf = to_perf_data(data); |
a6f6e6e6 | 237 | |
8cee1eed | 238 | cpufreq_for_each_entry(pos, policy->freq_table) |
041526f9 SK |
239 | if (msr == perf->states[pos->driver_data].status) |
240 | return pos->frequency; | |
8cee1eed | 241 | return policy->freq_table[0].frequency; |
dde9f7ba VP |
242 | } |
243 | ||
8cee1eed | 244 | static unsigned extract_freq(struct cpufreq_policy *policy, u32 val) |
dde9f7ba | 245 | { |
8cee1eed VK |
246 | struct acpi_cpufreq_data *data = policy->driver_data; |
247 | ||
dde9f7ba | 248 | switch (data->cpu_feature) { |
64be7eed | 249 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 250 | case SYSTEM_AMD_MSR_CAPABLE: |
8cee1eed | 251 | return extract_msr(policy, val); |
64be7eed | 252 | case SYSTEM_IO_CAPABLE: |
8cee1eed | 253 | return extract_io(policy, val); |
64be7eed | 254 | default: |
dde9f7ba VP |
255 | return 0; |
256 | } | |
257 | } | |
258 | ||
ac13b996 | 259 | static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used) |
ed757a2c RW |
260 | { |
261 | u32 val, dummy; | |
dde9f7ba | 262 | |
ed757a2c RW |
263 | rdmsr(MSR_IA32_PERF_CTL, val, dummy); |
264 | return val; | |
265 | } | |
266 | ||
ac13b996 | 267 | static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
268 | { |
269 | u32 lo, hi; | |
270 | ||
271 | rdmsr(MSR_IA32_PERF_CTL, lo, hi); | |
272 | lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE); | |
273 | wrmsr(MSR_IA32_PERF_CTL, lo, hi); | |
274 | } | |
275 | ||
ac13b996 | 276 | static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used) |
ed757a2c RW |
277 | { |
278 | u32 val, dummy; | |
279 | ||
280 | rdmsr(MSR_AMD_PERF_CTL, val, dummy); | |
281 | return val; | |
282 | } | |
283 | ||
ac13b996 | 284 | static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
285 | { |
286 | wrmsr(MSR_AMD_PERF_CTL, val, 0); | |
287 | } | |
288 | ||
ac13b996 | 289 | static u32 cpu_freq_read_io(struct acpi_pct_register *reg) |
ed757a2c RW |
290 | { |
291 | u32 val; | |
292 | ||
293 | acpi_os_read_port(reg->address, &val, reg->bit_width); | |
294 | return val; | |
295 | } | |
296 | ||
ac13b996 | 297 | static void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val) |
ed757a2c RW |
298 | { |
299 | acpi_os_write_port(reg->address, val, reg->bit_width); | |
300 | } | |
fe27cb35 VP |
301 | |
302 | struct drv_cmd { | |
ed757a2c | 303 | struct acpi_pct_register *reg; |
fe27cb35 | 304 | u32 val; |
ed757a2c RW |
305 | union { |
306 | void (*write)(struct acpi_pct_register *reg, u32 val); | |
307 | u32 (*read)(struct acpi_pct_register *reg); | |
308 | } func; | |
fe27cb35 VP |
309 | }; |
310 | ||
01599fca AM |
311 | /* Called via smp_call_function_single(), on the target CPU */ |
312 | static void do_drv_read(void *_cmd) | |
1da177e4 | 313 | { |
72859081 | 314 | struct drv_cmd *cmd = _cmd; |
dde9f7ba | 315 | |
ed757a2c | 316 | cmd->val = cmd->func.read(cmd->reg); |
fe27cb35 | 317 | } |
1da177e4 | 318 | |
ed757a2c | 319 | static u32 drv_read(struct acpi_cpufreq_data *data, const struct cpumask *mask) |
fe27cb35 | 320 | { |
ed757a2c RW |
321 | struct acpi_processor_performance *perf = to_perf_data(data); |
322 | struct drv_cmd cmd = { | |
323 | .reg = &perf->control_register, | |
324 | .func.read = data->cpu_freq_read, | |
325 | }; | |
326 | int err; | |
dde9f7ba | 327 | |
ed757a2c RW |
328 | err = smp_call_function_any(mask, do_drv_read, &cmd, 1); |
329 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
330 | return cmd.val; | |
fe27cb35 | 331 | } |
1da177e4 | 332 | |
ed757a2c RW |
333 | /* Called via smp_call_function_many(), on the target CPUs */ |
334 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 335 | { |
ed757a2c | 336 | struct drv_cmd *cmd = _cmd; |
fe27cb35 | 337 | |
ed757a2c | 338 | cmd->func.write(cmd->reg, cmd->val); |
fe27cb35 VP |
339 | } |
340 | ||
ed757a2c RW |
341 | static void drv_write(struct acpi_cpufreq_data *data, |
342 | const struct cpumask *mask, u32 val) | |
fe27cb35 | 343 | { |
ed757a2c RW |
344 | struct acpi_processor_performance *perf = to_perf_data(data); |
345 | struct drv_cmd cmd = { | |
346 | .reg = &perf->control_register, | |
347 | .val = val, | |
348 | .func.write = data->cpu_freq_write, | |
349 | }; | |
ea34f43a LT |
350 | int this_cpu; |
351 | ||
352 | this_cpu = get_cpu(); | |
ed757a2c RW |
353 | if (cpumask_test_cpu(this_cpu, mask)) |
354 | do_drv_write(&cmd); | |
355 | ||
356 | smp_call_function_many(mask, do_drv_write, &cmd, 1); | |
ea34f43a | 357 | put_cpu(); |
fe27cb35 | 358 | } |
1da177e4 | 359 | |
ed757a2c | 360 | static u32 get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) |
fe27cb35 | 361 | { |
ed757a2c | 362 | u32 val; |
1da177e4 | 363 | |
4d8bb537 | 364 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 365 | return 0; |
1da177e4 | 366 | |
ed757a2c | 367 | val = drv_read(data, mask); |
1da177e4 | 368 | |
ed757a2c | 369 | pr_debug("get_cur_val = %u\n", val); |
fe27cb35 | 370 | |
ed757a2c | 371 | return val; |
fe27cb35 | 372 | } |
1da177e4 | 373 | |
fe27cb35 VP |
374 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
375 | { | |
eb0b3e78 PX |
376 | struct acpi_cpufreq_data *data; |
377 | struct cpufreq_policy *policy; | |
64be7eed | 378 | unsigned int freq; |
e56a727b | 379 | unsigned int cached_freq; |
fe27cb35 | 380 | |
2d06d8c4 | 381 | pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); |
fe27cb35 | 382 | |
1f0bd44e | 383 | policy = cpufreq_cpu_get_raw(cpu); |
eb0b3e78 PX |
384 | if (unlikely(!policy)) |
385 | return 0; | |
386 | ||
387 | data = policy->driver_data; | |
8cee1eed | 388 | if (unlikely(!data || !policy->freq_table)) |
fe27cb35 | 389 | return 0; |
1da177e4 | 390 | |
8cee1eed VK |
391 | cached_freq = policy->freq_table[to_perf_data(data)->state].frequency; |
392 | freq = extract_freq(policy, get_cur_val(cpumask_of(cpu), data)); | |
e56a727b VP |
393 | if (freq != cached_freq) { |
394 | /* | |
395 | * The dreaded BIOS frequency change behind our back. | |
396 | * Force set the frequency on next target call. | |
397 | */ | |
398 | data->resume = 1; | |
399 | } | |
400 | ||
2d06d8c4 | 401 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 402 | |
fe27cb35 | 403 | return freq; |
1da177e4 LT |
404 | } |
405 | ||
8cee1eed VK |
406 | static unsigned int check_freqs(struct cpufreq_policy *policy, |
407 | const struct cpumask *mask, unsigned int freq) | |
fe27cb35 | 408 | { |
8cee1eed | 409 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
410 | unsigned int cur_freq; |
411 | unsigned int i; | |
1da177e4 | 412 | |
3a58df35 | 413 | for (i = 0; i < 100; i++) { |
8cee1eed | 414 | cur_freq = extract_freq(policy, get_cur_val(mask, data)); |
fe27cb35 VP |
415 | if (cur_freq == freq) |
416 | return 1; | |
417 | udelay(10); | |
418 | } | |
419 | return 0; | |
420 | } | |
421 | ||
422 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 423 | unsigned int index) |
1da177e4 | 424 | { |
eb0b3e78 | 425 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 426 | struct acpi_processor_performance *perf; |
ed757a2c | 427 | const struct cpumask *mask; |
8edc59d9 | 428 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 429 | int result = 0; |
fe27cb35 | 430 | |
8cee1eed | 431 | if (unlikely(!data)) { |
fe27cb35 VP |
432 | return -ENODEV; |
433 | } | |
1da177e4 | 434 | |
3427616b | 435 | perf = to_perf_data(data); |
8cee1eed | 436 | next_perf_state = policy->freq_table[index].driver_data; |
7650b281 | 437 | if (perf->state == next_perf_state) { |
fe27cb35 | 438 | if (unlikely(data->resume)) { |
2d06d8c4 | 439 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 440 | next_perf_state); |
fe27cb35 VP |
441 | data->resume = 0; |
442 | } else { | |
2d06d8c4 | 443 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 444 | next_perf_state); |
9a909a14 | 445 | return 0; |
fe27cb35 | 446 | } |
09b4d1ee VP |
447 | } |
448 | ||
ed757a2c RW |
449 | /* |
450 | * The core won't allow CPUs to go away until the governor has been | |
451 | * stopped, so we can rely on the stability of policy->cpus. | |
452 | */ | |
453 | mask = policy->shared_type == CPUFREQ_SHARED_TYPE_ANY ? | |
454 | cpumask_of(policy->cpu) : policy->cpus; | |
09b4d1ee | 455 | |
ed757a2c | 456 | drv_write(data, mask, perf->states[next_perf_state].control); |
09b4d1ee | 457 | |
fe27cb35 | 458 | if (acpi_pstate_strict) { |
8cee1eed VK |
459 | if (!check_freqs(policy, mask, |
460 | policy->freq_table[index].frequency)) { | |
2d06d8c4 | 461 | pr_debug("acpi_cpufreq_target failed (%d)\n", |
64be7eed | 462 | policy->cpu); |
4d8bb537 | 463 | result = -EAGAIN; |
09b4d1ee VP |
464 | } |
465 | } | |
466 | ||
e15d8309 VK |
467 | if (!result) |
468 | perf->state = next_perf_state; | |
fe27cb35 VP |
469 | |
470 | return result; | |
1da177e4 LT |
471 | } |
472 | ||
08e9cc40 CIK |
473 | static unsigned int acpi_cpufreq_fast_switch(struct cpufreq_policy *policy, |
474 | unsigned int target_freq) | |
b7898fda RW |
475 | { |
476 | struct acpi_cpufreq_data *data = policy->driver_data; | |
477 | struct acpi_processor_performance *perf; | |
478 | struct cpufreq_frequency_table *entry; | |
82577360 | 479 | unsigned int next_perf_state, next_freq, index; |
b7898fda RW |
480 | |
481 | /* | |
482 | * Find the closest frequency above target_freq. | |
b7898fda | 483 | */ |
5b6667c7 SM |
484 | if (policy->cached_target_freq == target_freq) |
485 | index = policy->cached_resolved_idx; | |
486 | else | |
487 | index = cpufreq_table_find_index_dl(policy, target_freq); | |
82577360 VK |
488 | |
489 | entry = &policy->freq_table[index]; | |
b7898fda RW |
490 | next_freq = entry->frequency; |
491 | next_perf_state = entry->driver_data; | |
492 | ||
493 | perf = to_perf_data(data); | |
494 | if (perf->state == next_perf_state) { | |
495 | if (unlikely(data->resume)) | |
496 | data->resume = 0; | |
497 | else | |
498 | return next_freq; | |
499 | } | |
500 | ||
501 | data->cpu_freq_write(&perf->control_register, | |
502 | perf->states[next_perf_state].control); | |
503 | perf->state = next_perf_state; | |
504 | return next_freq; | |
505 | } | |
506 | ||
1da177e4 | 507 | static unsigned long |
64be7eed | 508 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 509 | { |
3427616b | 510 | struct acpi_processor_performance *perf; |
09b4d1ee | 511 | |
3427616b | 512 | perf = to_perf_data(data); |
1da177e4 LT |
513 | if (cpu_khz) { |
514 | /* search the closest match to cpu_khz */ | |
515 | unsigned int i; | |
516 | unsigned long freq; | |
09b4d1ee | 517 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 518 | |
3a58df35 | 519 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 520 | freq = freqn; |
95dd7227 | 521 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 522 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 523 | perf->state = i; |
64be7eed | 524 | return freq; |
1da177e4 LT |
525 | } |
526 | } | |
95dd7227 | 527 | perf->state = perf->state_count-1; |
64be7eed | 528 | return freqn; |
09b4d1ee | 529 | } else { |
1da177e4 | 530 | /* assume CPU is at P0... */ |
09b4d1ee VP |
531 | perf->state = 0; |
532 | return perf->states[0].core_frequency * 1000; | |
533 | } | |
1da177e4 LT |
534 | } |
535 | ||
2fdf66b4 RR |
536 | static void free_acpi_perf_data(void) |
537 | { | |
538 | unsigned int i; | |
539 | ||
540 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
541 | for_each_possible_cpu(i) | |
542 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
543 | ->shared_cpu_map); | |
544 | free_percpu(acpi_perf_data); | |
545 | } | |
546 | ||
4d66ddf2 | 547 | static int cpufreq_boost_online(unsigned int cpu) |
615b7300 | 548 | { |
615b7300 | 549 | /* |
4d66ddf2 SAS |
550 | * On the CPU_UP path we simply keep the boost-disable flag |
551 | * in sync with the current global state. | |
615b7300 | 552 | */ |
a3605c46 | 553 | return boost_set_msr(acpi_cpufreq_driver.boost_enabled); |
4d66ddf2 | 554 | } |
615b7300 | 555 | |
4d66ddf2 SAS |
556 | static int cpufreq_boost_down_prep(unsigned int cpu) |
557 | { | |
4d66ddf2 SAS |
558 | /* |
559 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
560 | * this cpu cannot block the remaining ones from boosting. | |
561 | */ | |
a3605c46 | 562 | return boost_set_msr(1); |
615b7300 AP |
563 | } |
564 | ||
09b4d1ee VP |
565 | /* |
566 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
567 | * | |
568 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
569 | * in order to determine correct frequency and voltage pairings. We can | |
570 | * do _PDC and _PSD and find out the processor dependency for the | |
571 | * actual init that will happen later... | |
572 | */ | |
50109292 | 573 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 574 | { |
2fdf66b4 | 575 | unsigned int i; |
2d06d8c4 | 576 | pr_debug("acpi_cpufreq_early_init\n"); |
09b4d1ee | 577 | |
50109292 FY |
578 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
579 | if (!acpi_perf_data) { | |
2d06d8c4 | 580 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 581 | return -ENOMEM; |
09b4d1ee | 582 | } |
2fdf66b4 | 583 | for_each_possible_cpu(i) { |
eaa95840 | 584 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
585 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
586 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
587 | |
588 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
589 | free_acpi_perf_data(); | |
590 | return -ENOMEM; | |
591 | } | |
592 | } | |
09b4d1ee VP |
593 | |
594 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
595 | acpi_processor_preregister_performance(acpi_perf_data); |
596 | return 0; | |
09b4d1ee VP |
597 | } |
598 | ||
95625b8f | 599 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
600 | /* |
601 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
602 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
603 | * detected, this has a side effect of making CPU run at a different speed | |
604 | * than OS intended it to run at. Detect it and handle it cleanly. | |
605 | */ | |
606 | static int bios_with_sw_any_bug; | |
607 | ||
1855256c | 608 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
609 | { |
610 | bios_with_sw_any_bug = 1; | |
611 | return 0; | |
612 | } | |
613 | ||
1855256c | 614 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
615 | { |
616 | .callback = sw_any_bug_found, | |
617 | .ident = "Supermicro Server X6DLP", | |
618 | .matches = { | |
619 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
620 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
621 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
622 | }, | |
623 | }, | |
624 | { } | |
625 | }; | |
1a8e42fa PB |
626 | |
627 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
628 | { | |
293afe44 JV |
629 | /* Intel Xeon Processor 7100 Series Specification Update |
630 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
631 | * AL30: A Machine Check Exception (MCE) Occurring during an |
632 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 633 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
634 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
635 | if ((c->x86 == 15) && | |
636 | (c->x86_model == 6) && | |
b399151c | 637 | (c->x86_stepping == 8)) { |
1c5864e2 | 638 | pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n"); |
1a8e42fa | 639 | return -ENODEV; |
293afe44 | 640 | } |
1a8e42fa PB |
641 | } |
642 | return 0; | |
643 | } | |
95625b8f | 644 | #endif |
8adcc0c6 | 645 | |
64be7eed | 646 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 647 | { |
64be7eed VP |
648 | unsigned int i; |
649 | unsigned int valid_states = 0; | |
650 | unsigned int cpu = policy->cpu; | |
651 | struct acpi_cpufreq_data *data; | |
64be7eed | 652 | unsigned int result = 0; |
92cb7612 | 653 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 654 | struct acpi_processor_performance *perf; |
8cee1eed | 655 | struct cpufreq_frequency_table *freq_table; |
293afe44 JV |
656 | #ifdef CONFIG_SMP |
657 | static int blacklisted; | |
658 | #endif | |
1da177e4 | 659 | |
2d06d8c4 | 660 | pr_debug("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 661 | |
1a8e42fa | 662 | #ifdef CONFIG_SMP |
293afe44 JV |
663 | if (blacklisted) |
664 | return blacklisted; | |
665 | blacklisted = acpi_cpufreq_blacklist(c); | |
666 | if (blacklisted) | |
667 | return blacklisted; | |
1a8e42fa PB |
668 | #endif |
669 | ||
d5b73cd8 | 670 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 671 | if (!data) |
64be7eed | 672 | return -ENOMEM; |
1da177e4 | 673 | |
f4fd3797 LT |
674 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
675 | result = -ENOMEM; | |
676 | goto err_free; | |
677 | } | |
678 | ||
3427616b | 679 | perf = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 680 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 681 | policy->driver_data = data; |
1da177e4 | 682 | |
95dd7227 | 683 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 684 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 685 | |
3427616b | 686 | result = acpi_processor_register_performance(perf, cpu); |
1da177e4 | 687 | if (result) |
f4fd3797 | 688 | goto err_free_mask; |
1da177e4 | 689 | |
09b4d1ee | 690 | policy->shared_type = perf->shared_type; |
95dd7227 | 691 | |
46f18e3a | 692 | /* |
95dd7227 | 693 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
694 | * coordination is required. |
695 | */ | |
696 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 697 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 698 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 699 | } |
f4fd3797 | 700 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
701 | |
702 | #ifdef CONFIG_SMP | |
703 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 704 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 705 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 706 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 707 | } |
acd31624 AP |
708 | |
709 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
710 | cpumask_clear(policy->cpus); | |
711 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
712 | cpumask_copy(data->freqdomain_cpus, |
713 | topology_sibling_cpumask(cpu)); | |
acd31624 | 714 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
1c5864e2 | 715 | pr_info_once("overriding BIOS provided _PSD data\n"); |
acd31624 | 716 | } |
8adcc0c6 | 717 | #endif |
09b4d1ee | 718 | |
1da177e4 | 719 | /* capability check */ |
09b4d1ee | 720 | if (perf->state_count <= 1) { |
2d06d8c4 | 721 | pr_debug("No P-States\n"); |
1da177e4 LT |
722 | result = -ENODEV; |
723 | goto err_unreg; | |
724 | } | |
09b4d1ee | 725 | |
fe27cb35 VP |
726 | if (perf->control_register.space_id != perf->status_register.space_id) { |
727 | result = -ENODEV; | |
728 | goto err_unreg; | |
729 | } | |
730 | ||
731 | switch (perf->control_register.space_id) { | |
64be7eed | 732 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
733 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
734 | boot_cpu_data.x86 == 0xf) { | |
735 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
736 | result = -ENODEV; | |
737 | goto err_unreg; | |
738 | } | |
2d06d8c4 | 739 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba | 740 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
ed757a2c RW |
741 | data->cpu_freq_read = cpu_freq_read_io; |
742 | data->cpu_freq_write = cpu_freq_write_io; | |
dde9f7ba | 743 | break; |
64be7eed | 744 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 745 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
746 | if (check_est_cpu(cpu)) { |
747 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
ed757a2c RW |
748 | data->cpu_freq_read = cpu_freq_read_intel; |
749 | data->cpu_freq_write = cpu_freq_write_intel; | |
3dc9a633 | 750 | break; |
dde9f7ba | 751 | } |
3dc9a633 MG |
752 | if (check_amd_hwpstate_cpu(cpu)) { |
753 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
ed757a2c RW |
754 | data->cpu_freq_read = cpu_freq_read_amd; |
755 | data->cpu_freq_write = cpu_freq_write_amd; | |
3dc9a633 MG |
756 | break; |
757 | } | |
758 | result = -ENODEV; | |
759 | goto err_unreg; | |
64be7eed | 760 | default: |
2d06d8c4 | 761 | pr_debug("Unknown addr space %d\n", |
64be7eed | 762 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
763 | result = -ENODEV; |
764 | goto err_unreg; | |
765 | } | |
766 | ||
6396bb22 KC |
767 | freq_table = kcalloc(perf->state_count + 1, sizeof(*freq_table), |
768 | GFP_KERNEL); | |
8cee1eed | 769 | if (!freq_table) { |
1da177e4 LT |
770 | result = -ENOMEM; |
771 | goto err_unreg; | |
772 | } | |
773 | ||
774 | /* detect transition latency */ | |
775 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 776 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
777 | if ((perf->states[i].transition_latency * 1000) > |
778 | policy->cpuinfo.transition_latency) | |
779 | policy->cpuinfo.transition_latency = | |
780 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 781 | } |
1da177e4 | 782 | |
a59d1637 PV |
783 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
784 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
785 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 786 | policy->cpuinfo.transition_latency = 20 * 1000; |
b49c22a6 | 787 | pr_info_once("P-state transition latency capped at 20 uS\n"); |
a59d1637 PV |
788 | } |
789 | ||
1da177e4 | 790 | /* table init */ |
3a58df35 DJ |
791 | for (i = 0; i < perf->state_count; i++) { |
792 | if (i > 0 && perf->states[i].core_frequency >= | |
8cee1eed | 793 | freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
794 | continue; |
795 | ||
8cee1eed VK |
796 | freq_table[valid_states].driver_data = i; |
797 | freq_table[valid_states].frequency = | |
64be7eed | 798 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 799 | valid_states++; |
1da177e4 | 800 | } |
8cee1eed | 801 | freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
1a186d9e | 802 | policy->freq_table = freq_table; |
8edc59d9 | 803 | perf->state = 0; |
1da177e4 | 804 | |
a507ac4b | 805 | switch (perf->control_register.space_id) { |
64be7eed | 806 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
807 | /* |
808 | * The core will not set policy->cur, because | |
809 | * cpufreq_driver->get is NULL, so we need to set it here. | |
810 | * However, we have to guess it, because the current speed is | |
811 | * unknown and not detectable via IO ports. | |
812 | */ | |
dde9f7ba VP |
813 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
814 | break; | |
64be7eed | 815 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 816 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 817 | break; |
64be7eed | 818 | default: |
dde9f7ba VP |
819 | break; |
820 | } | |
821 | ||
1da177e4 LT |
822 | /* notify BIOS that we exist */ |
823 | acpi_processor_notify_smm(THIS_MODULE); | |
824 | ||
2d06d8c4 | 825 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 826 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 827 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 828 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
829 | (u32) perf->states[i].core_frequency, |
830 | (u32) perf->states[i].power, | |
831 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 832 | |
4b31e774 DB |
833 | /* |
834 | * the first call to ->target() should result in us actually | |
835 | * writing something to the appropriate registers. | |
836 | */ | |
837 | data->resume = 1; | |
64be7eed | 838 | |
b7898fda RW |
839 | policy->fast_switch_possible = !acpi_pstate_strict && |
840 | !(policy_is_shared(policy) && policy->shared_type != CPUFREQ_SHARED_TYPE_ANY); | |
841 | ||
fe27cb35 | 842 | return result; |
1da177e4 | 843 | |
95dd7227 | 844 | err_unreg: |
b2f8dc4c | 845 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
846 | err_free_mask: |
847 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 848 | err_free: |
1da177e4 | 849 | kfree(data); |
eb0b3e78 | 850 | policy->driver_data = NULL; |
1da177e4 | 851 | |
64be7eed | 852 | return result; |
1da177e4 LT |
853 | } |
854 | ||
64be7eed | 855 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 856 | { |
eb0b3e78 | 857 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 858 | |
2d06d8c4 | 859 | pr_debug("acpi_cpufreq_cpu_exit\n"); |
1da177e4 | 860 | |
9b55f55a VK |
861 | policy->fast_switch_possible = false; |
862 | policy->driver_data = NULL; | |
863 | acpi_processor_unregister_performance(data->acpi_perf_cpu); | |
864 | free_cpumask_var(data->freqdomain_cpus); | |
8cee1eed | 865 | kfree(policy->freq_table); |
9b55f55a | 866 | kfree(data); |
1da177e4 | 867 | |
64be7eed | 868 | return 0; |
1da177e4 LT |
869 | } |
870 | ||
1a186d9e VK |
871 | static void acpi_cpufreq_cpu_ready(struct cpufreq_policy *policy) |
872 | { | |
873 | struct acpi_processor_performance *perf = per_cpu_ptr(acpi_perf_data, | |
874 | policy->cpu); | |
875 | ||
876 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) | |
877 | pr_warn(FW_WARN "P-state 0 is not max freq\n"); | |
878 | } | |
879 | ||
64be7eed | 880 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 881 | { |
eb0b3e78 | 882 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 883 | |
2d06d8c4 | 884 | pr_debug("acpi_cpufreq_resume\n"); |
1da177e4 LT |
885 | |
886 | data->resume = 1; | |
887 | ||
64be7eed | 888 | return 0; |
1da177e4 LT |
889 | } |
890 | ||
64be7eed | 891 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 892 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 893 | &freqdomain_cpus, |
f56c50e3 RW |
894 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
895 | &cpb, | |
896 | #endif | |
1da177e4 LT |
897 | NULL, |
898 | }; | |
899 | ||
900 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 901 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 902 | .target_index = acpi_cpufreq_target, |
b7898fda | 903 | .fast_switch = acpi_cpufreq_fast_switch, |
e2f74f35 TR |
904 | .bios_limit = acpi_processor_get_bios_limit, |
905 | .init = acpi_cpufreq_cpu_init, | |
906 | .exit = acpi_cpufreq_cpu_exit, | |
1a186d9e | 907 | .ready = acpi_cpufreq_cpu_ready, |
e2f74f35 TR |
908 | .resume = acpi_cpufreq_resume, |
909 | .name = "acpi-cpufreq", | |
e2f74f35 | 910 | .attr = acpi_cpufreq_attr, |
1da177e4 LT |
911 | }; |
912 | ||
4d66ddf2 SAS |
913 | static enum cpuhp_state acpi_cpufreq_online; |
914 | ||
615b7300 AP |
915 | static void __init acpi_cpufreq_boost_init(void) |
916 | { | |
4d66ddf2 | 917 | int ret; |
615b7300 | 918 | |
4d66ddf2 SAS |
919 | if (!(boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA))) |
920 | return; | |
0197fbd2 | 921 | |
4d66ddf2 SAS |
922 | acpi_cpufreq_driver.set_boost = set_boost; |
923 | acpi_cpufreq_driver.boost_enabled = boost_state(0); | |
615b7300 | 924 | |
4d66ddf2 SAS |
925 | /* |
926 | * This calls the online callback on all online cpu and forces all | |
927 | * MSRs to the same value. | |
928 | */ | |
929 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "cpufreq/acpi:online", | |
930 | cpufreq_boost_online, cpufreq_boost_down_prep); | |
931 | if (ret < 0) { | |
932 | pr_err("acpi_cpufreq: failed to register hotplug callbacks\n"); | |
4d66ddf2 | 933 | return; |
cfc9c8ed | 934 | } |
4d66ddf2 | 935 | acpi_cpufreq_online = ret; |
615b7300 AP |
936 | } |
937 | ||
eb8c68ef | 938 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 939 | { |
2a8fa123 | 940 | if (acpi_cpufreq_online > 0) |
4d66ddf2 | 941 | cpuhp_remove_state_nocalls(acpi_cpufreq_online); |
615b7300 AP |
942 | } |
943 | ||
64be7eed | 944 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 945 | { |
50109292 FY |
946 | int ret; |
947 | ||
75c07581 RW |
948 | if (acpi_disabled) |
949 | return -ENODEV; | |
950 | ||
8a61e12e YL |
951 | /* don't keep reloading if cpufreq_driver exists */ |
952 | if (cpufreq_get_current_driver()) | |
75c07581 | 953 | return -EEXIST; |
ee297533 | 954 | |
2d06d8c4 | 955 | pr_debug("acpi_cpufreq_init\n"); |
1da177e4 | 956 | |
50109292 FY |
957 | ret = acpi_cpufreq_early_init(); |
958 | if (ret) | |
959 | return ret; | |
09b4d1ee | 960 | |
11269ff5 AP |
961 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
962 | /* this is a sysfs file with a strange name and an even stranger | |
963 | * semantic - per CPU instantiation, but system global effect. | |
964 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
965 | * only if configured. This is considered legacy code, which | |
966 | * will probably be removed at some point in the future. | |
967 | */ | |
f56c50e3 RW |
968 | if (!check_amd_hwpstate_cpu(0)) { |
969 | struct freq_attr **attr; | |
11269ff5 | 970 | |
f56c50e3 | 971 | pr_debug("CPB unsupported, do not expose it\n"); |
11269ff5 | 972 | |
f56c50e3 RW |
973 | for (attr = acpi_cpufreq_attr; *attr; attr++) |
974 | if (*attr == &cpb) { | |
975 | *attr = NULL; | |
976 | break; | |
977 | } | |
11269ff5 AP |
978 | } |
979 | #endif | |
cfc9c8ed | 980 | acpi_cpufreq_boost_init(); |
11269ff5 | 981 | |
847aef6f | 982 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 983 | if (ret) { |
2fdf66b4 | 984 | free_acpi_perf_data(); |
eb8c68ef KRW |
985 | acpi_cpufreq_boost_exit(); |
986 | } | |
847aef6f | 987 | return ret; |
1da177e4 LT |
988 | } |
989 | ||
64be7eed | 990 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 991 | { |
2d06d8c4 | 992 | pr_debug("acpi_cpufreq_exit\n"); |
1da177e4 | 993 | |
615b7300 AP |
994 | acpi_cpufreq_boost_exit(); |
995 | ||
1da177e4 LT |
996 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
997 | ||
50f4ddd4 | 998 | free_acpi_perf_data(); |
1da177e4 LT |
999 | } |
1000 | ||
d395bf12 | 1001 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 1002 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
1003 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
1004 | "performed during frequency changes."); | |
1da177e4 LT |
1005 | |
1006 | late_initcall(acpi_cpufreq_init); | |
1007 | module_exit(acpi_cpufreq_exit); | |
1008 | ||
efa17194 MG |
1009 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
1010 | X86_FEATURE_MATCH(X86_FEATURE_ACPI), | |
1011 | X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), | |
1012 | {} | |
1013 | }; | |
1014 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1015 | ||
c655affb RW |
1016 | static const struct acpi_device_id processor_device_ids[] = { |
1017 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
1018 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1019 | {}, | |
1020 | }; | |
1021 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1022 | ||
1da177e4 | 1023 | MODULE_ALIAS("acpi"); |