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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | /* |
3a58df35 | 3 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
6 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
7 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 8 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
9 | */ |
10 | ||
1c5864e2 JP |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
12 | ||
1da177e4 LT |
13 | #include <linux/kernel.h> |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
fe27cb35 VP |
16 | #include <linux/smp.h> |
17 | #include <linux/sched.h> | |
1da177e4 | 18 | #include <linux/cpufreq.h> |
d395bf12 | 19 | #include <linux/compiler.h> |
8adcc0c6 | 20 | #include <linux/dmi.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include <linux/acpi.h> | |
3a58df35 DJ |
24 | #include <linux/io.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/uaccess.h> | |
27 | ||
1da177e4 | 28 | #include <acpi/processor.h> |
3c55e94c | 29 | #include <acpi/cppc_acpi.h> |
1da177e4 | 30 | |
dde9f7ba | 31 | #include <asm/msr.h> |
fe27cb35 VP |
32 | #include <asm/processor.h> |
33 | #include <asm/cpufeature.h> | |
ba5bade4 | 34 | #include <asm/cpu_device_id.h> |
fe27cb35 | 35 | |
1da177e4 LT |
36 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
37 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
38 | MODULE_LICENSE("GPL"); | |
39 | ||
dde9f7ba VP |
40 | enum { |
41 | UNDEFINED_CAPABLE = 0, | |
42 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 43 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
44 | SYSTEM_IO_CAPABLE, |
45 | }; | |
46 | ||
47 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 48 | #define AMD_MSR_RANGE (0x7) |
cc9690cf | 49 | #define HYGON_MSR_RANGE (0x7) |
dde9f7ba | 50 | |
615b7300 AP |
51 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
52 | ||
fe27cb35 | 53 | struct acpi_cpufreq_data { |
64be7eed VP |
54 | unsigned int resume; |
55 | unsigned int cpu_feature; | |
8cfcfd39 | 56 | unsigned int acpi_perf_cpu; |
f4fd3797 | 57 | cpumask_var_t freqdomain_cpus; |
ed757a2c RW |
58 | void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val); |
59 | u32 (*cpu_freq_read)(struct acpi_pct_register *reg); | |
1da177e4 LT |
60 | }; |
61 | ||
50109292 | 62 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 63 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 | 64 | |
3427616b RW |
65 | static inline struct acpi_processor_performance *to_perf_data(struct acpi_cpufreq_data *data) |
66 | { | |
67 | return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); | |
68 | } | |
69 | ||
1da177e4 LT |
70 | static struct cpufreq_driver acpi_cpufreq_driver; |
71 | ||
d395bf12 | 72 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
73 | |
74 | static bool boost_state(unsigned int cpu) | |
75 | { | |
76 | u32 lo, hi; | |
77 | u64 msr; | |
78 | ||
79 | switch (boot_cpu_data.x86_vendor) { | |
80 | case X86_VENDOR_INTEL: | |
81 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
82 | msr = lo | ((u64)hi << 32); | |
83 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
cc9690cf | 84 | case X86_VENDOR_HYGON: |
615b7300 AP |
85 | case X86_VENDOR_AMD: |
86 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
87 | msr = lo | ((u64)hi << 32); | |
88 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
89 | } | |
90 | return false; | |
91 | } | |
92 | ||
a3605c46 | 93 | static int boost_set_msr(bool enable) |
615b7300 | 94 | { |
615b7300 | 95 | u32 msr_addr; |
a3605c46 | 96 | u64 msr_mask, val; |
615b7300 AP |
97 | |
98 | switch (boot_cpu_data.x86_vendor) { | |
99 | case X86_VENDOR_INTEL: | |
100 | msr_addr = MSR_IA32_MISC_ENABLE; | |
101 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
102 | break; | |
cc9690cf | 103 | case X86_VENDOR_HYGON: |
615b7300 AP |
104 | case X86_VENDOR_AMD: |
105 | msr_addr = MSR_K7_HWCR; | |
106 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
107 | break; | |
108 | default: | |
a3605c46 | 109 | return -EINVAL; |
615b7300 AP |
110 | } |
111 | ||
a3605c46 | 112 | rdmsrl(msr_addr, val); |
615b7300 | 113 | |
a3605c46 SAS |
114 | if (enable) |
115 | val &= ~msr_mask; | |
116 | else | |
117 | val |= msr_mask; | |
615b7300 | 118 | |
a3605c46 SAS |
119 | wrmsrl(msr_addr, val); |
120 | return 0; | |
121 | } | |
122 | ||
123 | static void boost_set_msr_each(void *p_en) | |
124 | { | |
125 | bool enable = (bool) p_en; | |
126 | ||
127 | boost_set_msr(enable); | |
615b7300 AP |
128 | } |
129 | ||
cf6fada7 | 130 | static int set_boost(struct cpufreq_policy *policy, int val) |
615b7300 | 131 | { |
cf6fada7 XW |
132 | on_each_cpu_mask(policy->cpus, boost_set_msr_each, |
133 | (void *)(long)val, 1); | |
134 | pr_debug("CPU %*pbl: Core Boosting %sabled.\n", | |
135 | cpumask_pr_args(policy->cpus), val ? "en" : "dis"); | |
615b7300 | 136 | |
cfc9c8ed | 137 | return 0; |
615b7300 AP |
138 | } |
139 | ||
f4fd3797 LT |
140 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
141 | { | |
eb0b3e78 | 142 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 | 143 | |
e2530367 SP |
144 | if (unlikely(!data)) |
145 | return -ENODEV; | |
146 | ||
f4fd3797 LT |
147 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); |
148 | } | |
149 | ||
150 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
151 | ||
11269ff5 | 152 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
17135782 RW |
153 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
154 | size_t count) | |
cfc9c8ed LM |
155 | { |
156 | int ret; | |
17135782 | 157 | unsigned int val = 0; |
cfc9c8ed | 158 | |
7a6c79f2 | 159 | if (!acpi_cpufreq_driver.set_boost) |
cfc9c8ed LM |
160 | return -EINVAL; |
161 | ||
17135782 RW |
162 | ret = kstrtouint(buf, 10, &val); |
163 | if (ret || val > 1) | |
cfc9c8ed LM |
164 | return -EINVAL; |
165 | ||
09681a07 | 166 | cpus_read_lock(); |
cf6fada7 | 167 | set_boost(policy, val); |
09681a07 | 168 | cpus_read_unlock(); |
cfc9c8ed LM |
169 | |
170 | return count; | |
171 | } | |
172 | ||
11269ff5 AP |
173 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) |
174 | { | |
cfc9c8ed | 175 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
176 | } |
177 | ||
59027d35 | 178 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
179 | #endif |
180 | ||
dde9f7ba VP |
181 | static int check_est_cpu(unsigned int cpuid) |
182 | { | |
92cb7612 | 183 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 184 | |
0de51088 | 185 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
186 | } |
187 | ||
3dc9a633 MG |
188 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
189 | { | |
190 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
191 | ||
192 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
193 | } | |
194 | ||
8cee1eed | 195 | static unsigned extract_io(struct cpufreq_policy *policy, u32 value) |
fe27cb35 | 196 | { |
8cee1eed | 197 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
198 | struct acpi_processor_performance *perf; |
199 | int i; | |
fe27cb35 | 200 | |
3427616b | 201 | perf = to_perf_data(data); |
fe27cb35 | 202 | |
3a58df35 | 203 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 | 204 | if (value == perf->states[i].status) |
8cee1eed | 205 | return policy->freq_table[i].frequency; |
fe27cb35 VP |
206 | } |
207 | return 0; | |
208 | } | |
209 | ||
8cee1eed | 210 | static unsigned extract_msr(struct cpufreq_policy *policy, u32 msr) |
dde9f7ba | 211 | { |
8cee1eed | 212 | struct acpi_cpufreq_data *data = policy->driver_data; |
041526f9 | 213 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 214 | struct acpi_processor_performance *perf; |
dde9f7ba | 215 | |
3dc9a633 MG |
216 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
217 | msr &= AMD_MSR_RANGE; | |
cc9690cf PW |
218 | else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) |
219 | msr &= HYGON_MSR_RANGE; | |
3dc9a633 MG |
220 | else |
221 | msr &= INTEL_MSR_RANGE; | |
222 | ||
3427616b | 223 | perf = to_perf_data(data); |
a6f6e6e6 | 224 | |
538b0188 | 225 | cpufreq_for_each_entry(pos, policy->freq_table) |
041526f9 SK |
226 | if (msr == perf->states[pos->driver_data].status) |
227 | return pos->frequency; | |
538b0188 | 228 | return policy->freq_table[0].frequency; |
dde9f7ba VP |
229 | } |
230 | ||
8cee1eed | 231 | static unsigned extract_freq(struct cpufreq_policy *policy, u32 val) |
dde9f7ba | 232 | { |
8cee1eed VK |
233 | struct acpi_cpufreq_data *data = policy->driver_data; |
234 | ||
dde9f7ba | 235 | switch (data->cpu_feature) { |
64be7eed | 236 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 237 | case SYSTEM_AMD_MSR_CAPABLE: |
8cee1eed | 238 | return extract_msr(policy, val); |
64be7eed | 239 | case SYSTEM_IO_CAPABLE: |
8cee1eed | 240 | return extract_io(policy, val); |
64be7eed | 241 | default: |
dde9f7ba VP |
242 | return 0; |
243 | } | |
244 | } | |
245 | ||
ac13b996 | 246 | static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used) |
ed757a2c | 247 | { |
e1711f29 | 248 | u32 val, dummy __always_unused; |
dde9f7ba | 249 | |
ed757a2c RW |
250 | rdmsr(MSR_IA32_PERF_CTL, val, dummy); |
251 | return val; | |
252 | } | |
253 | ||
ac13b996 | 254 | static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
255 | { |
256 | u32 lo, hi; | |
257 | ||
258 | rdmsr(MSR_IA32_PERF_CTL, lo, hi); | |
259 | lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE); | |
260 | wrmsr(MSR_IA32_PERF_CTL, lo, hi); | |
261 | } | |
262 | ||
ac13b996 | 263 | static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used) |
ed757a2c | 264 | { |
e1711f29 | 265 | u32 val, dummy __always_unused; |
ed757a2c RW |
266 | |
267 | rdmsr(MSR_AMD_PERF_CTL, val, dummy); | |
268 | return val; | |
269 | } | |
270 | ||
ac13b996 | 271 | static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
272 | { |
273 | wrmsr(MSR_AMD_PERF_CTL, val, 0); | |
274 | } | |
275 | ||
ac13b996 | 276 | static u32 cpu_freq_read_io(struct acpi_pct_register *reg) |
ed757a2c RW |
277 | { |
278 | u32 val; | |
279 | ||
280 | acpi_os_read_port(reg->address, &val, reg->bit_width); | |
281 | return val; | |
282 | } | |
283 | ||
ac13b996 | 284 | static void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val) |
ed757a2c RW |
285 | { |
286 | acpi_os_write_port(reg->address, val, reg->bit_width); | |
287 | } | |
fe27cb35 VP |
288 | |
289 | struct drv_cmd { | |
ed757a2c | 290 | struct acpi_pct_register *reg; |
fe27cb35 | 291 | u32 val; |
ed757a2c RW |
292 | union { |
293 | void (*write)(struct acpi_pct_register *reg, u32 val); | |
294 | u32 (*read)(struct acpi_pct_register *reg); | |
295 | } func; | |
fe27cb35 VP |
296 | }; |
297 | ||
01599fca AM |
298 | /* Called via smp_call_function_single(), on the target CPU */ |
299 | static void do_drv_read(void *_cmd) | |
1da177e4 | 300 | { |
72859081 | 301 | struct drv_cmd *cmd = _cmd; |
dde9f7ba | 302 | |
ed757a2c | 303 | cmd->val = cmd->func.read(cmd->reg); |
fe27cb35 | 304 | } |
1da177e4 | 305 | |
ed757a2c | 306 | static u32 drv_read(struct acpi_cpufreq_data *data, const struct cpumask *mask) |
fe27cb35 | 307 | { |
ed757a2c RW |
308 | struct acpi_processor_performance *perf = to_perf_data(data); |
309 | struct drv_cmd cmd = { | |
310 | .reg = &perf->control_register, | |
311 | .func.read = data->cpu_freq_read, | |
312 | }; | |
313 | int err; | |
dde9f7ba | 314 | |
ed757a2c RW |
315 | err = smp_call_function_any(mask, do_drv_read, &cmd, 1); |
316 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
317 | return cmd.val; | |
fe27cb35 | 318 | } |
1da177e4 | 319 | |
ed757a2c RW |
320 | /* Called via smp_call_function_many(), on the target CPUs */ |
321 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 322 | { |
ed757a2c | 323 | struct drv_cmd *cmd = _cmd; |
fe27cb35 | 324 | |
ed757a2c | 325 | cmd->func.write(cmd->reg, cmd->val); |
fe27cb35 VP |
326 | } |
327 | ||
ed757a2c RW |
328 | static void drv_write(struct acpi_cpufreq_data *data, |
329 | const struct cpumask *mask, u32 val) | |
fe27cb35 | 330 | { |
ed757a2c RW |
331 | struct acpi_processor_performance *perf = to_perf_data(data); |
332 | struct drv_cmd cmd = { | |
333 | .reg = &perf->control_register, | |
334 | .val = val, | |
335 | .func.write = data->cpu_freq_write, | |
336 | }; | |
ea34f43a LT |
337 | int this_cpu; |
338 | ||
339 | this_cpu = get_cpu(); | |
ed757a2c RW |
340 | if (cpumask_test_cpu(this_cpu, mask)) |
341 | do_drv_write(&cmd); | |
342 | ||
343 | smp_call_function_many(mask, do_drv_write, &cmd, 1); | |
ea34f43a | 344 | put_cpu(); |
fe27cb35 | 345 | } |
1da177e4 | 346 | |
ed757a2c | 347 | static u32 get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) |
fe27cb35 | 348 | { |
ed757a2c | 349 | u32 val; |
1da177e4 | 350 | |
4d8bb537 | 351 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 352 | return 0; |
1da177e4 | 353 | |
ed757a2c | 354 | val = drv_read(data, mask); |
1da177e4 | 355 | |
eae2ef0e | 356 | pr_debug("%s = %u\n", __func__, val); |
fe27cb35 | 357 | |
ed757a2c | 358 | return val; |
fe27cb35 | 359 | } |
1da177e4 | 360 | |
fe27cb35 VP |
361 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
362 | { | |
eb0b3e78 PX |
363 | struct acpi_cpufreq_data *data; |
364 | struct cpufreq_policy *policy; | |
64be7eed | 365 | unsigned int freq; |
e56a727b | 366 | unsigned int cached_freq; |
fe27cb35 | 367 | |
eae2ef0e | 368 | pr_debug("%s (%d)\n", __func__, cpu); |
fe27cb35 | 369 | |
1f0bd44e | 370 | policy = cpufreq_cpu_get_raw(cpu); |
eb0b3e78 PX |
371 | if (unlikely(!policy)) |
372 | return 0; | |
373 | ||
374 | data = policy->driver_data; | |
8cee1eed | 375 | if (unlikely(!data || !policy->freq_table)) |
fe27cb35 | 376 | return 0; |
1da177e4 | 377 | |
538b0188 | 378 | cached_freq = policy->freq_table[to_perf_data(data)->state].frequency; |
8cee1eed | 379 | freq = extract_freq(policy, get_cur_val(cpumask_of(cpu), data)); |
e56a727b VP |
380 | if (freq != cached_freq) { |
381 | /* | |
382 | * The dreaded BIOS frequency change behind our back. | |
383 | * Force set the frequency on next target call. | |
384 | */ | |
385 | data->resume = 1; | |
386 | } | |
387 | ||
2d06d8c4 | 388 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 389 | |
fe27cb35 | 390 | return freq; |
1da177e4 LT |
391 | } |
392 | ||
8cee1eed VK |
393 | static unsigned int check_freqs(struct cpufreq_policy *policy, |
394 | const struct cpumask *mask, unsigned int freq) | |
fe27cb35 | 395 | { |
8cee1eed | 396 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
397 | unsigned int cur_freq; |
398 | unsigned int i; | |
1da177e4 | 399 | |
3a58df35 | 400 | for (i = 0; i < 100; i++) { |
8cee1eed | 401 | cur_freq = extract_freq(policy, get_cur_val(mask, data)); |
fe27cb35 VP |
402 | if (cur_freq == freq) |
403 | return 1; | |
404 | udelay(10); | |
405 | } | |
406 | return 0; | |
407 | } | |
408 | ||
409 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 410 | unsigned int index) |
1da177e4 | 411 | { |
eb0b3e78 | 412 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 413 | struct acpi_processor_performance *perf; |
ed757a2c | 414 | const struct cpumask *mask; |
8edc59d9 | 415 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 416 | int result = 0; |
fe27cb35 | 417 | |
8cee1eed | 418 | if (unlikely(!data)) { |
fe27cb35 VP |
419 | return -ENODEV; |
420 | } | |
1da177e4 | 421 | |
3427616b | 422 | perf = to_perf_data(data); |
8cee1eed | 423 | next_perf_state = policy->freq_table[index].driver_data; |
7650b281 | 424 | if (perf->state == next_perf_state) { |
fe27cb35 | 425 | if (unlikely(data->resume)) { |
2d06d8c4 | 426 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 427 | next_perf_state); |
fe27cb35 VP |
428 | data->resume = 0; |
429 | } else { | |
2d06d8c4 | 430 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 431 | next_perf_state); |
9a909a14 | 432 | return 0; |
fe27cb35 | 433 | } |
09b4d1ee VP |
434 | } |
435 | ||
ed757a2c RW |
436 | /* |
437 | * The core won't allow CPUs to go away until the governor has been | |
438 | * stopped, so we can rely on the stability of policy->cpus. | |
439 | */ | |
440 | mask = policy->shared_type == CPUFREQ_SHARED_TYPE_ANY ? | |
441 | cpumask_of(policy->cpu) : policy->cpus; | |
09b4d1ee | 442 | |
ed757a2c | 443 | drv_write(data, mask, perf->states[next_perf_state].control); |
09b4d1ee | 444 | |
fe27cb35 | 445 | if (acpi_pstate_strict) { |
8cee1eed VK |
446 | if (!check_freqs(policy, mask, |
447 | policy->freq_table[index].frequency)) { | |
eae2ef0e | 448 | pr_debug("%s (%d)\n", __func__, policy->cpu); |
4d8bb537 | 449 | result = -EAGAIN; |
09b4d1ee VP |
450 | } |
451 | } | |
452 | ||
e15d8309 VK |
453 | if (!result) |
454 | perf->state = next_perf_state; | |
fe27cb35 VP |
455 | |
456 | return result; | |
1da177e4 LT |
457 | } |
458 | ||
08e9cc40 CIK |
459 | static unsigned int acpi_cpufreq_fast_switch(struct cpufreq_policy *policy, |
460 | unsigned int target_freq) | |
b7898fda RW |
461 | { |
462 | struct acpi_cpufreq_data *data = policy->driver_data; | |
463 | struct acpi_processor_performance *perf; | |
464 | struct cpufreq_frequency_table *entry; | |
82577360 | 465 | unsigned int next_perf_state, next_freq, index; |
b7898fda RW |
466 | |
467 | /* | |
468 | * Find the closest frequency above target_freq. | |
b7898fda | 469 | */ |
5b6667c7 SM |
470 | if (policy->cached_target_freq == target_freq) |
471 | index = policy->cached_resolved_idx; | |
472 | else | |
1f39fa0d VD |
473 | index = cpufreq_table_find_index_dl(policy, target_freq, |
474 | false); | |
82577360 VK |
475 | |
476 | entry = &policy->freq_table[index]; | |
b7898fda RW |
477 | next_freq = entry->frequency; |
478 | next_perf_state = entry->driver_data; | |
479 | ||
480 | perf = to_perf_data(data); | |
481 | if (perf->state == next_perf_state) { | |
482 | if (unlikely(data->resume)) | |
483 | data->resume = 0; | |
484 | else | |
485 | return next_freq; | |
486 | } | |
487 | ||
488 | data->cpu_freq_write(&perf->control_register, | |
489 | perf->states[next_perf_state].control); | |
490 | perf->state = next_perf_state; | |
491 | return next_freq; | |
492 | } | |
493 | ||
1da177e4 | 494 | static unsigned long |
64be7eed | 495 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 496 | { |
3427616b | 497 | struct acpi_processor_performance *perf; |
09b4d1ee | 498 | |
3427616b | 499 | perf = to_perf_data(data); |
1da177e4 LT |
500 | if (cpu_khz) { |
501 | /* search the closest match to cpu_khz */ | |
502 | unsigned int i; | |
503 | unsigned long freq; | |
09b4d1ee | 504 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 505 | |
3a58df35 | 506 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 507 | freq = freqn; |
95dd7227 | 508 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 509 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 510 | perf->state = i; |
64be7eed | 511 | return freq; |
1da177e4 LT |
512 | } |
513 | } | |
95dd7227 | 514 | perf->state = perf->state_count-1; |
64be7eed | 515 | return freqn; |
09b4d1ee | 516 | } else { |
1da177e4 | 517 | /* assume CPU is at P0... */ |
09b4d1ee VP |
518 | perf->state = 0; |
519 | return perf->states[0].core_frequency * 1000; | |
520 | } | |
1da177e4 LT |
521 | } |
522 | ||
2fdf66b4 RR |
523 | static void free_acpi_perf_data(void) |
524 | { | |
525 | unsigned int i; | |
526 | ||
527 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
528 | for_each_possible_cpu(i) | |
529 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
530 | ->shared_cpu_map); | |
531 | free_percpu(acpi_perf_data); | |
532 | } | |
533 | ||
4d66ddf2 | 534 | static int cpufreq_boost_online(unsigned int cpu) |
615b7300 | 535 | { |
615b7300 | 536 | /* |
4d66ddf2 SAS |
537 | * On the CPU_UP path we simply keep the boost-disable flag |
538 | * in sync with the current global state. | |
615b7300 | 539 | */ |
a3605c46 | 540 | return boost_set_msr(acpi_cpufreq_driver.boost_enabled); |
4d66ddf2 | 541 | } |
615b7300 | 542 | |
4d66ddf2 SAS |
543 | static int cpufreq_boost_down_prep(unsigned int cpu) |
544 | { | |
4d66ddf2 SAS |
545 | /* |
546 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
547 | * this cpu cannot block the remaining ones from boosting. | |
548 | */ | |
a3605c46 | 549 | return boost_set_msr(1); |
615b7300 AP |
550 | } |
551 | ||
09b4d1ee VP |
552 | /* |
553 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
554 | * | |
555 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
556 | * in order to determine correct frequency and voltage pairings. We can | |
557 | * do _PDC and _PSD and find out the processor dependency for the | |
558 | * actual init that will happen later... | |
559 | */ | |
50109292 | 560 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 561 | { |
2fdf66b4 | 562 | unsigned int i; |
eae2ef0e | 563 | pr_debug("%s\n", __func__); |
09b4d1ee | 564 | |
50109292 FY |
565 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
566 | if (!acpi_perf_data) { | |
2d06d8c4 | 567 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 568 | return -ENOMEM; |
09b4d1ee | 569 | } |
2fdf66b4 | 570 | for_each_possible_cpu(i) { |
eaa95840 | 571 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
572 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
573 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
574 | |
575 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
576 | free_acpi_perf_data(); | |
577 | return -ENOMEM; | |
578 | } | |
579 | } | |
09b4d1ee VP |
580 | |
581 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
582 | acpi_processor_preregister_performance(acpi_perf_data); |
583 | return 0; | |
09b4d1ee VP |
584 | } |
585 | ||
95625b8f | 586 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
587 | /* |
588 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
589 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
590 | * detected, this has a side effect of making CPU run at a different speed | |
591 | * than OS intended it to run at. Detect it and handle it cleanly. | |
592 | */ | |
593 | static int bios_with_sw_any_bug; | |
594 | ||
1855256c | 595 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
596 | { |
597 | bios_with_sw_any_bug = 1; | |
598 | return 0; | |
599 | } | |
600 | ||
1855256c | 601 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
602 | { |
603 | .callback = sw_any_bug_found, | |
604 | .ident = "Supermicro Server X6DLP", | |
605 | .matches = { | |
606 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
607 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
608 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
609 | }, | |
610 | }, | |
611 | { } | |
612 | }; | |
1a8e42fa PB |
613 | |
614 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
615 | { | |
293afe44 | 616 | /* Intel Xeon Processor 7100 Series Specification Update |
8479eb82 | 617 | * https://www.intel.com/Assets/PDF/specupdate/314554.pdf |
1a8e42fa PB |
618 | * AL30: A Machine Check Exception (MCE) Occurring during an |
619 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 620 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
621 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
622 | if ((c->x86 == 15) && | |
623 | (c->x86_model == 6) && | |
b399151c | 624 | (c->x86_stepping == 8)) { |
1c5864e2 | 625 | pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n"); |
1a8e42fa | 626 | return -ENODEV; |
293afe44 | 627 | } |
1a8e42fa PB |
628 | } |
629 | return 0; | |
630 | } | |
95625b8f | 631 | #endif |
8adcc0c6 | 632 | |
3c55e94c RW |
633 | #ifdef CONFIG_ACPI_CPPC_LIB |
634 | static u64 get_max_boost_ratio(unsigned int cpu) | |
635 | { | |
636 | struct cppc_perf_caps perf_caps; | |
637 | u64 highest_perf, nominal_perf; | |
638 | int ret; | |
639 | ||
640 | if (acpi_pstate_strict) | |
641 | return 0; | |
642 | ||
643 | ret = cppc_get_perf_caps(cpu, &perf_caps); | |
644 | if (ret) { | |
645 | pr_debug("CPU%d: Unable to get performance capabilities (%d)\n", | |
646 | cpu, ret); | |
647 | return 0; | |
648 | } | |
649 | ||
3743d55b HR |
650 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
651 | highest_perf = amd_get_highest_perf(); | |
652 | else | |
653 | highest_perf = perf_caps.highest_perf; | |
654 | ||
3c55e94c RW |
655 | nominal_perf = perf_caps.nominal_perf; |
656 | ||
657 | if (!highest_perf || !nominal_perf) { | |
658 | pr_debug("CPU%d: highest or nominal performance missing\n", cpu); | |
659 | return 0; | |
660 | } | |
661 | ||
662 | if (highest_perf < nominal_perf) { | |
663 | pr_debug("CPU%d: nominal performance above highest\n", cpu); | |
664 | return 0; | |
665 | } | |
666 | ||
667 | return div_u64(highest_perf << SCHED_CAPACITY_SHIFT, nominal_perf); | |
668 | } | |
669 | #else | |
670 | static inline u64 get_max_boost_ratio(unsigned int cpu) { return 0; } | |
671 | #endif | |
672 | ||
64be7eed | 673 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 674 | { |
3c55e94c RW |
675 | struct cpufreq_frequency_table *freq_table; |
676 | struct acpi_processor_performance *perf; | |
64be7eed | 677 | struct acpi_cpufreq_data *data; |
3c55e94c RW |
678 | unsigned int cpu = policy->cpu; |
679 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
680 | unsigned int valid_states = 0; | |
64be7eed | 681 | unsigned int result = 0; |
3c55e94c RW |
682 | u64 max_boost_ratio; |
683 | unsigned int i; | |
293afe44 JV |
684 | #ifdef CONFIG_SMP |
685 | static int blacklisted; | |
686 | #endif | |
1da177e4 | 687 | |
eae2ef0e | 688 | pr_debug("%s\n", __func__); |
1da177e4 | 689 | |
1a8e42fa | 690 | #ifdef CONFIG_SMP |
293afe44 JV |
691 | if (blacklisted) |
692 | return blacklisted; | |
693 | blacklisted = acpi_cpufreq_blacklist(c); | |
694 | if (blacklisted) | |
695 | return blacklisted; | |
1a8e42fa PB |
696 | #endif |
697 | ||
d5b73cd8 | 698 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 699 | if (!data) |
64be7eed | 700 | return -ENOMEM; |
1da177e4 | 701 | |
f4fd3797 LT |
702 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
703 | result = -ENOMEM; | |
704 | goto err_free; | |
705 | } | |
706 | ||
3427616b | 707 | perf = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 708 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 709 | policy->driver_data = data; |
1da177e4 | 710 | |
95dd7227 | 711 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 712 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 713 | |
3427616b | 714 | result = acpi_processor_register_performance(perf, cpu); |
1da177e4 | 715 | if (result) |
f4fd3797 | 716 | goto err_free_mask; |
1da177e4 | 717 | |
09b4d1ee | 718 | policy->shared_type = perf->shared_type; |
95dd7227 | 719 | |
46f18e3a | 720 | /* |
95dd7227 | 721 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
722 | * coordination is required. |
723 | */ | |
724 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 725 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 726 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 727 | } |
f4fd3797 | 728 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
729 | |
730 | #ifdef CONFIG_SMP | |
731 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 732 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 733 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 734 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 735 | } |
acd31624 | 736 | |
5368512a WH |
737 | if (check_amd_hwpstate_cpu(cpu) && boot_cpu_data.x86 < 0x19 && |
738 | !acpi_pstate_strict) { | |
acd31624 AP |
739 | cpumask_clear(policy->cpus); |
740 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
741 | cpumask_copy(data->freqdomain_cpus, |
742 | topology_sibling_cpumask(cpu)); | |
acd31624 | 743 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
1c5864e2 | 744 | pr_info_once("overriding BIOS provided _PSD data\n"); |
acd31624 | 745 | } |
8adcc0c6 | 746 | #endif |
09b4d1ee | 747 | |
1da177e4 | 748 | /* capability check */ |
09b4d1ee | 749 | if (perf->state_count <= 1) { |
2d06d8c4 | 750 | pr_debug("No P-States\n"); |
1da177e4 LT |
751 | result = -ENODEV; |
752 | goto err_unreg; | |
753 | } | |
09b4d1ee | 754 | |
fe27cb35 VP |
755 | if (perf->control_register.space_id != perf->status_register.space_id) { |
756 | result = -ENODEV; | |
757 | goto err_unreg; | |
758 | } | |
759 | ||
760 | switch (perf->control_register.space_id) { | |
64be7eed | 761 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
762 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
763 | boot_cpu_data.x86 == 0xf) { | |
764 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
765 | result = -ENODEV; | |
766 | goto err_unreg; | |
767 | } | |
2d06d8c4 | 768 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba | 769 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
ed757a2c RW |
770 | data->cpu_freq_read = cpu_freq_read_io; |
771 | data->cpu_freq_write = cpu_freq_write_io; | |
dde9f7ba | 772 | break; |
64be7eed | 773 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 774 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
775 | if (check_est_cpu(cpu)) { |
776 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
ed757a2c RW |
777 | data->cpu_freq_read = cpu_freq_read_intel; |
778 | data->cpu_freq_write = cpu_freq_write_intel; | |
3dc9a633 | 779 | break; |
dde9f7ba | 780 | } |
3dc9a633 MG |
781 | if (check_amd_hwpstate_cpu(cpu)) { |
782 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
ed757a2c RW |
783 | data->cpu_freq_read = cpu_freq_read_amd; |
784 | data->cpu_freq_write = cpu_freq_write_amd; | |
3dc9a633 MG |
785 | break; |
786 | } | |
787 | result = -ENODEV; | |
788 | goto err_unreg; | |
64be7eed | 789 | default: |
2d06d8c4 | 790 | pr_debug("Unknown addr space %d\n", |
64be7eed | 791 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
792 | result = -ENODEV; |
793 | goto err_unreg; | |
794 | } | |
795 | ||
538b0188 RW |
796 | freq_table = kcalloc(perf->state_count + 1, sizeof(*freq_table), |
797 | GFP_KERNEL); | |
8cee1eed | 798 | if (!freq_table) { |
1da177e4 LT |
799 | result = -ENOMEM; |
800 | goto err_unreg; | |
801 | } | |
802 | ||
803 | /* detect transition latency */ | |
804 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 805 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
806 | if ((perf->states[i].transition_latency * 1000) > |
807 | policy->cpuinfo.transition_latency) | |
808 | policy->cpuinfo.transition_latency = | |
809 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 810 | } |
1da177e4 | 811 | |
a59d1637 PV |
812 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
813 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
814 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 815 | policy->cpuinfo.transition_latency = 20 * 1000; |
b49c22a6 | 816 | pr_info_once("P-state transition latency capped at 20 uS\n"); |
a59d1637 PV |
817 | } |
818 | ||
1da177e4 | 819 | /* table init */ |
3a58df35 DJ |
820 | for (i = 0; i < perf->state_count; i++) { |
821 | if (i > 0 && perf->states[i].core_frequency >= | |
8cee1eed | 822 | freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
823 | continue; |
824 | ||
8cee1eed VK |
825 | freq_table[valid_states].driver_data = i; |
826 | freq_table[valid_states].frequency = | |
64be7eed | 827 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 828 | valid_states++; |
1da177e4 | 829 | } |
8cee1eed | 830 | freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
3c55e94c | 831 | |
538b0188 | 832 | max_boost_ratio = get_max_boost_ratio(cpu); |
3c55e94c | 833 | if (max_boost_ratio) { |
538b0188 | 834 | unsigned int freq = freq_table[0].frequency; |
3c55e94c RW |
835 | |
836 | /* | |
837 | * Because the loop above sorts the freq_table entries in the | |
838 | * descending order, freq is the maximum frequency in the table. | |
839 | * Assume that it corresponds to the CPPC nominal frequency and | |
538b0188 | 840 | * use it to set cpuinfo.max_freq. |
3c55e94c | 841 | */ |
538b0188 RW |
842 | policy->cpuinfo.max_freq = freq * max_boost_ratio >> SCHED_CAPACITY_SHIFT; |
843 | } else { | |
3c55e94c | 844 | /* |
538b0188 RW |
845 | * If the maximum "boost" frequency is unknown, ask the arch |
846 | * scale-invariance code to use the "nominal" performance for | |
847 | * CPU utilization scaling so as to prevent the schedutil | |
848 | * governor from selecting inadequate CPU frequencies. | |
3c55e94c | 849 | */ |
538b0188 | 850 | arch_set_max_freq_ratio(true); |
3c55e94c RW |
851 | } |
852 | ||
1a186d9e | 853 | policy->freq_table = freq_table; |
8edc59d9 | 854 | perf->state = 0; |
1da177e4 | 855 | |
a507ac4b | 856 | switch (perf->control_register.space_id) { |
64be7eed | 857 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
858 | /* |
859 | * The core will not set policy->cur, because | |
860 | * cpufreq_driver->get is NULL, so we need to set it here. | |
861 | * However, we have to guess it, because the current speed is | |
862 | * unknown and not detectable via IO ports. | |
863 | */ | |
dde9f7ba VP |
864 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
865 | break; | |
64be7eed | 866 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 867 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 868 | break; |
64be7eed | 869 | default: |
dde9f7ba VP |
870 | break; |
871 | } | |
872 | ||
1da177e4 LT |
873 | /* notify BIOS that we exist */ |
874 | acpi_processor_notify_smm(THIS_MODULE); | |
875 | ||
2d06d8c4 | 876 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 877 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 878 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 879 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
880 | (u32) perf->states[i].core_frequency, |
881 | (u32) perf->states[i].power, | |
882 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 883 | |
4b31e774 DB |
884 | /* |
885 | * the first call to ->target() should result in us actually | |
886 | * writing something to the appropriate registers. | |
887 | */ | |
888 | data->resume = 1; | |
64be7eed | 889 | |
b7898fda RW |
890 | policy->fast_switch_possible = !acpi_pstate_strict && |
891 | !(policy_is_shared(policy) && policy->shared_type != CPUFREQ_SHARED_TYPE_ANY); | |
892 | ||
692a3b9a VK |
893 | if (perf->states[0].core_frequency * 1000 != freq_table[0].frequency) |
894 | pr_warn(FW_WARN "P-state 0 is not max freq\n"); | |
895 | ||
fe27cb35 | 896 | return result; |
1da177e4 | 897 | |
95dd7227 | 898 | err_unreg: |
b2f8dc4c | 899 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
900 | err_free_mask: |
901 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 902 | err_free: |
1da177e4 | 903 | kfree(data); |
eb0b3e78 | 904 | policy->driver_data = NULL; |
1da177e4 | 905 | |
64be7eed | 906 | return result; |
1da177e4 LT |
907 | } |
908 | ||
64be7eed | 909 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 910 | { |
eb0b3e78 | 911 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 912 | |
eae2ef0e | 913 | pr_debug("%s\n", __func__); |
1da177e4 | 914 | |
9b55f55a VK |
915 | policy->fast_switch_possible = false; |
916 | policy->driver_data = NULL; | |
917 | acpi_processor_unregister_performance(data->acpi_perf_cpu); | |
918 | free_cpumask_var(data->freqdomain_cpus); | |
8cee1eed | 919 | kfree(policy->freq_table); |
9b55f55a | 920 | kfree(data); |
1da177e4 | 921 | |
64be7eed | 922 | return 0; |
1da177e4 LT |
923 | } |
924 | ||
64be7eed | 925 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 926 | { |
eb0b3e78 | 927 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 928 | |
eae2ef0e | 929 | pr_debug("%s\n", __func__); |
1da177e4 LT |
930 | |
931 | data->resume = 1; | |
932 | ||
64be7eed | 933 | return 0; |
1da177e4 LT |
934 | } |
935 | ||
64be7eed | 936 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 937 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 938 | &freqdomain_cpus, |
f56c50e3 RW |
939 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
940 | &cpb, | |
941 | #endif | |
1da177e4 LT |
942 | NULL, |
943 | }; | |
944 | ||
945 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 946 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 947 | .target_index = acpi_cpufreq_target, |
b7898fda | 948 | .fast_switch = acpi_cpufreq_fast_switch, |
e2f74f35 TR |
949 | .bios_limit = acpi_processor_get_bios_limit, |
950 | .init = acpi_cpufreq_cpu_init, | |
951 | .exit = acpi_cpufreq_cpu_exit, | |
952 | .resume = acpi_cpufreq_resume, | |
953 | .name = "acpi-cpufreq", | |
e2f74f35 | 954 | .attr = acpi_cpufreq_attr, |
1da177e4 LT |
955 | }; |
956 | ||
4d66ddf2 SAS |
957 | static enum cpuhp_state acpi_cpufreq_online; |
958 | ||
615b7300 AP |
959 | static void __init acpi_cpufreq_boost_init(void) |
960 | { | |
4d66ddf2 | 961 | int ret; |
615b7300 | 962 | |
1222d527 EV |
963 | if (!(boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA))) { |
964 | pr_debug("Boost capabilities not present in the processor\n"); | |
4d66ddf2 | 965 | return; |
1222d527 | 966 | } |
0197fbd2 | 967 | |
4d66ddf2 SAS |
968 | acpi_cpufreq_driver.set_boost = set_boost; |
969 | acpi_cpufreq_driver.boost_enabled = boost_state(0); | |
615b7300 | 970 | |
4d66ddf2 SAS |
971 | /* |
972 | * This calls the online callback on all online cpu and forces all | |
973 | * MSRs to the same value. | |
974 | */ | |
975 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "cpufreq/acpi:online", | |
976 | cpufreq_boost_online, cpufreq_boost_down_prep); | |
977 | if (ret < 0) { | |
978 | pr_err("acpi_cpufreq: failed to register hotplug callbacks\n"); | |
4d66ddf2 | 979 | return; |
cfc9c8ed | 980 | } |
4d66ddf2 | 981 | acpi_cpufreq_online = ret; |
615b7300 AP |
982 | } |
983 | ||
eb8c68ef | 984 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 985 | { |
2a8fa123 | 986 | if (acpi_cpufreq_online > 0) |
4d66ddf2 | 987 | cpuhp_remove_state_nocalls(acpi_cpufreq_online); |
615b7300 AP |
988 | } |
989 | ||
64be7eed | 990 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 991 | { |
50109292 FY |
992 | int ret; |
993 | ||
75c07581 RW |
994 | if (acpi_disabled) |
995 | return -ENODEV; | |
996 | ||
8a61e12e YL |
997 | /* don't keep reloading if cpufreq_driver exists */ |
998 | if (cpufreq_get_current_driver()) | |
75c07581 | 999 | return -EEXIST; |
ee297533 | 1000 | |
eae2ef0e | 1001 | pr_debug("%s\n", __func__); |
1da177e4 | 1002 | |
50109292 FY |
1003 | ret = acpi_cpufreq_early_init(); |
1004 | if (ret) | |
1005 | return ret; | |
09b4d1ee | 1006 | |
11269ff5 AP |
1007 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
1008 | /* this is a sysfs file with a strange name and an even stranger | |
1009 | * semantic - per CPU instantiation, but system global effect. | |
1010 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
1011 | * only if configured. This is considered legacy code, which | |
1012 | * will probably be removed at some point in the future. | |
1013 | */ | |
f56c50e3 RW |
1014 | if (!check_amd_hwpstate_cpu(0)) { |
1015 | struct freq_attr **attr; | |
11269ff5 | 1016 | |
f56c50e3 | 1017 | pr_debug("CPB unsupported, do not expose it\n"); |
11269ff5 | 1018 | |
f56c50e3 RW |
1019 | for (attr = acpi_cpufreq_attr; *attr; attr++) |
1020 | if (*attr == &cpb) { | |
1021 | *attr = NULL; | |
1022 | break; | |
1023 | } | |
11269ff5 AP |
1024 | } |
1025 | #endif | |
cfc9c8ed | 1026 | acpi_cpufreq_boost_init(); |
11269ff5 | 1027 | |
847aef6f | 1028 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 1029 | if (ret) { |
2fdf66b4 | 1030 | free_acpi_perf_data(); |
eb8c68ef KRW |
1031 | acpi_cpufreq_boost_exit(); |
1032 | } | |
847aef6f | 1033 | return ret; |
1da177e4 LT |
1034 | } |
1035 | ||
64be7eed | 1036 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 1037 | { |
eae2ef0e | 1038 | pr_debug("%s\n", __func__); |
1da177e4 | 1039 | |
615b7300 AP |
1040 | acpi_cpufreq_boost_exit(); |
1041 | ||
1da177e4 LT |
1042 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
1043 | ||
50f4ddd4 | 1044 | free_acpi_perf_data(); |
1da177e4 LT |
1045 | } |
1046 | ||
d395bf12 | 1047 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 1048 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
1049 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
1050 | "performed during frequency changes."); | |
1da177e4 LT |
1051 | |
1052 | late_initcall(acpi_cpufreq_init); | |
1053 | module_exit(acpi_cpufreq_exit); | |
1054 | ||
a7b90937 | 1055 | static const struct x86_cpu_id __maybe_unused acpi_cpufreq_ids[] = { |
b11d77fa TG |
1056 | X86_MATCH_FEATURE(X86_FEATURE_ACPI, NULL), |
1057 | X86_MATCH_FEATURE(X86_FEATURE_HW_PSTATE, NULL), | |
efa17194 MG |
1058 | {} |
1059 | }; | |
1060 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1061 | ||
a7b90937 | 1062 | static const struct acpi_device_id __maybe_unused processor_device_ids[] = { |
c655affb RW |
1063 | {ACPI_PROCESSOR_OBJECT_HID, }, |
1064 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1065 | {}, | |
1066 | }; | |
1067 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1068 | ||
1da177e4 | 1069 | MODULE_ALIAS("acpi"); |