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ad29937e BG |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * STM32 Timer Encoder and Counter driver | |
4 | * | |
5 | * Copyright (C) STMicroelectronics 2018 | |
6 | * | |
7 | * Author: Benjamin Gaignard <benjamin.gaignard@st.com> | |
8 | * | |
9 | */ | |
10 | #include <linux/counter.h> | |
ad29937e | 11 | #include <linux/mfd/stm32-timers.h> |
15e8573d | 12 | #include <linux/mod_devicetable.h> |
ad29937e | 13 | #include <linux/module.h> |
c5b84255 | 14 | #include <linux/pinctrl/consumer.h> |
ad29937e | 15 | #include <linux/platform_device.h> |
aaec1a0f | 16 | #include <linux/types.h> |
ad29937e BG |
17 | |
18 | #define TIM_CCMR_CCXS (BIT(8) | BIT(0)) | |
19 | #define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \ | |
20 | TIM_CCMR_IC1F | TIM_CCMR_IC2F) | |
21 | #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \ | |
22 | TIM_CCER_CC2P | TIM_CCER_CC2NP) | |
23 | ||
c5b84255 FG |
24 | struct stm32_timer_regs { |
25 | u32 cr1; | |
26 | u32 cnt; | |
27 | u32 smcr; | |
28 | u32 arr; | |
29 | }; | |
30 | ||
ad29937e | 31 | struct stm32_timer_cnt { |
ad29937e BG |
32 | struct regmap *regmap; |
33 | struct clk *clk; | |
e4c3e133 | 34 | u32 max_arr; |
c5b84255 FG |
35 | bool enabled; |
36 | struct stm32_timer_regs bak; | |
ad29937e BG |
37 | }; |
38 | ||
394a0150 | 39 | static const enum counter_function stm32_count_functions[] = { |
aaec1a0f WBG |
40 | COUNTER_FUNCTION_INCREASE, |
41 | COUNTER_FUNCTION_QUADRATURE_X2_A, | |
42 | COUNTER_FUNCTION_QUADRATURE_X2_B, | |
43 | COUNTER_FUNCTION_QUADRATURE_X4, | |
ad29937e BG |
44 | }; |
45 | ||
46 | static int stm32_count_read(struct counter_device *counter, | |
aaec1a0f | 47 | struct counter_count *count, u64 *val) |
ad29937e | 48 | { |
e152833b | 49 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
ad29937e BG |
50 | u32 cnt; |
51 | ||
52 | regmap_read(priv->regmap, TIM_CNT, &cnt); | |
d49e6ee2 | 53 | *val = cnt; |
ad29937e BG |
54 | |
55 | return 0; | |
56 | } | |
57 | ||
58 | static int stm32_count_write(struct counter_device *counter, | |
aaec1a0f | 59 | struct counter_count *count, const u64 val) |
ad29937e | 60 | { |
e152833b | 61 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
b14d72ac | 62 | u32 ceiling; |
ad29937e | 63 | |
b14d72ac FG |
64 | regmap_read(priv->regmap, TIM_ARR, &ceiling); |
65 | if (val > ceiling) | |
ad29937e BG |
66 | return -EINVAL; |
67 | ||
d49e6ee2 | 68 | return regmap_write(priv->regmap, TIM_CNT, val); |
ad29937e BG |
69 | } |
70 | ||
aaec1a0f WBG |
71 | static int stm32_count_function_read(struct counter_device *counter, |
72 | struct counter_count *count, | |
73 | enum counter_function *function) | |
ad29937e | 74 | { |
e152833b | 75 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
ad29937e BG |
76 | u32 smcr; |
77 | ||
78 | regmap_read(priv->regmap, TIM_SMCR, &smcr); | |
79 | ||
80 | switch (smcr & TIM_SMCR_SMS) { | |
ea434ff8 | 81 | case TIM_SMCR_SMS_SLAVE_MODE_DISABLED: |
aaec1a0f | 82 | *function = COUNTER_FUNCTION_INCREASE; |
fae6f62e | 83 | return 0; |
ea434ff8 | 84 | case TIM_SMCR_SMS_ENCODER_MODE_1: |
aaec1a0f | 85 | *function = COUNTER_FUNCTION_QUADRATURE_X2_A; |
ad29937e | 86 | return 0; |
ea434ff8 | 87 | case TIM_SMCR_SMS_ENCODER_MODE_2: |
aaec1a0f | 88 | *function = COUNTER_FUNCTION_QUADRATURE_X2_B; |
ad29937e | 89 | return 0; |
ea434ff8 | 90 | case TIM_SMCR_SMS_ENCODER_MODE_3: |
aaec1a0f | 91 | *function = COUNTER_FUNCTION_QUADRATURE_X4; |
ad29937e | 92 | return 0; |
fae6f62e WBG |
93 | default: |
94 | return -EINVAL; | |
ad29937e | 95 | } |
ad29937e BG |
96 | } |
97 | ||
aaec1a0f WBG |
98 | static int stm32_count_function_write(struct counter_device *counter, |
99 | struct counter_count *count, | |
100 | enum counter_function function) | |
ad29937e | 101 | { |
e152833b | 102 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
ad29937e BG |
103 | u32 cr1, sms; |
104 | ||
105 | switch (function) { | |
aaec1a0f | 106 | case COUNTER_FUNCTION_INCREASE: |
ea434ff8 | 107 | sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED; |
fae6f62e | 108 | break; |
aaec1a0f | 109 | case COUNTER_FUNCTION_QUADRATURE_X2_A: |
ea434ff8 | 110 | sms = TIM_SMCR_SMS_ENCODER_MODE_1; |
ad29937e | 111 | break; |
aaec1a0f | 112 | case COUNTER_FUNCTION_QUADRATURE_X2_B: |
ea434ff8 | 113 | sms = TIM_SMCR_SMS_ENCODER_MODE_2; |
ad29937e | 114 | break; |
aaec1a0f | 115 | case COUNTER_FUNCTION_QUADRATURE_X4: |
ea434ff8 | 116 | sms = TIM_SMCR_SMS_ENCODER_MODE_3; |
ad29937e BG |
117 | break; |
118 | default: | |
fae6f62e | 119 | return -EINVAL; |
ad29937e BG |
120 | } |
121 | ||
122 | /* Store enable status */ | |
123 | regmap_read(priv->regmap, TIM_CR1, &cr1); | |
124 | ||
125 | regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); | |
126 | ||
ad29937e BG |
127 | regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); |
128 | ||
129 | /* Make sure that registers are updated */ | |
130 | regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); | |
131 | ||
132 | /* Restore the enable status */ | |
133 | regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
aaec1a0f | 138 | static int stm32_count_direction_read(struct counter_device *counter, |
ad29937e | 139 | struct counter_count *count, |
aaec1a0f | 140 | enum counter_count_direction *direction) |
ad29937e | 141 | { |
e152833b | 142 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
ad29937e BG |
143 | u32 cr1; |
144 | ||
145 | regmap_read(priv->regmap, TIM_CR1, &cr1); | |
aaec1a0f WBG |
146 | *direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD : |
147 | COUNTER_COUNT_DIRECTION_FORWARD; | |
ad29937e | 148 | |
aaec1a0f | 149 | return 0; |
ad29937e BG |
150 | } |
151 | ||
aaec1a0f WBG |
152 | static int stm32_count_ceiling_read(struct counter_device *counter, |
153 | struct counter_count *count, u64 *ceiling) | |
ad29937e | 154 | { |
e152833b | 155 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
ad29937e BG |
156 | u32 arr; |
157 | ||
158 | regmap_read(priv->regmap, TIM_ARR, &arr); | |
159 | ||
aaec1a0f WBG |
160 | *ceiling = arr; |
161 | ||
162 | return 0; | |
ad29937e BG |
163 | } |
164 | ||
aaec1a0f WBG |
165 | static int stm32_count_ceiling_write(struct counter_device *counter, |
166 | struct counter_count *count, u64 ceiling) | |
ad29937e | 167 | { |
e152833b | 168 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
ad29937e | 169 | |
e4c3e133 FG |
170 | if (ceiling > priv->max_arr) |
171 | return -ERANGE; | |
172 | ||
ad29937e BG |
173 | /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ |
174 | regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); | |
175 | regmap_write(priv->regmap, TIM_ARR, ceiling); | |
176 | ||
aaec1a0f | 177 | return 0; |
ad29937e BG |
178 | } |
179 | ||
aaec1a0f WBG |
180 | static int stm32_count_enable_read(struct counter_device *counter, |
181 | struct counter_count *count, u8 *enable) | |
ad29937e | 182 | { |
e152833b | 183 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
ad29937e BG |
184 | u32 cr1; |
185 | ||
186 | regmap_read(priv->regmap, TIM_CR1, &cr1); | |
187 | ||
aaec1a0f WBG |
188 | *enable = cr1 & TIM_CR1_CEN; |
189 | ||
190 | return 0; | |
ad29937e BG |
191 | } |
192 | ||
aaec1a0f WBG |
193 | static int stm32_count_enable_write(struct counter_device *counter, |
194 | struct counter_count *count, u8 enable) | |
ad29937e | 195 | { |
e152833b | 196 | struct stm32_timer_cnt *const priv = counter_priv(counter); |
ad29937e | 197 | u32 cr1; |
ad29937e BG |
198 | |
199 | if (enable) { | |
200 | regmap_read(priv->regmap, TIM_CR1, &cr1); | |
76510ec6 CIK |
201 | if (!(cr1 & TIM_CR1_CEN)) |
202 | clk_enable(priv->clk); | |
ad29937e BG |
203 | |
204 | regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, | |
205 | TIM_CR1_CEN); | |
206 | } else { | |
207 | regmap_read(priv->regmap, TIM_CR1, &cr1); | |
208 | regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); | |
209 | if (cr1 & TIM_CR1_CEN) | |
210 | clk_disable(priv->clk); | |
211 | } | |
212 | ||
c5b84255 FG |
213 | /* Keep enabled state to properly handle low power states */ |
214 | priv->enabled = enable; | |
215 | ||
aaec1a0f | 216 | return 0; |
ad29937e BG |
217 | } |
218 | ||
aaec1a0f WBG |
219 | static struct counter_comp stm32_count_ext[] = { |
220 | COUNTER_COMP_DIRECTION(stm32_count_direction_read), | |
221 | COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), | |
222 | COUNTER_COMP_CEILING(stm32_count_ceiling_read, | |
223 | stm32_count_ceiling_write), | |
ad29937e BG |
224 | }; |
225 | ||
d0ce3d5c | 226 | static const enum counter_synapse_action stm32_synapse_actions[] = { |
aaec1a0f WBG |
227 | COUNTER_SYNAPSE_ACTION_NONE, |
228 | COUNTER_SYNAPSE_ACTION_BOTH_EDGES | |
ad29937e BG |
229 | }; |
230 | ||
aaec1a0f WBG |
231 | static int stm32_action_read(struct counter_device *counter, |
232 | struct counter_count *count, | |
233 | struct counter_synapse *synapse, | |
234 | enum counter_synapse_action *action) | |
ad29937e | 235 | { |
aaec1a0f | 236 | enum counter_function function; |
ad29937e BG |
237 | int err; |
238 | ||
aaec1a0f | 239 | err = stm32_count_function_read(counter, count, &function); |
ad29937e | 240 | if (err) |
fae6f62e | 241 | return err; |
ad29937e BG |
242 | |
243 | switch (function) { | |
aaec1a0f | 244 | case COUNTER_FUNCTION_INCREASE: |
fae6f62e | 245 | /* counts on internal clock when CEN=1 */ |
aaec1a0f | 246 | *action = COUNTER_SYNAPSE_ACTION_NONE; |
fae6f62e | 247 | return 0; |
aaec1a0f | 248 | case COUNTER_FUNCTION_QUADRATURE_X2_A: |
ad29937e BG |
249 | /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
250 | if (synapse->signal->id == count->synapses[0].signal->id) | |
aaec1a0f | 251 | *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; |
fae6f62e | 252 | else |
aaec1a0f | 253 | *action = COUNTER_SYNAPSE_ACTION_NONE; |
fae6f62e | 254 | return 0; |
aaec1a0f | 255 | case COUNTER_FUNCTION_QUADRATURE_X2_B: |
ad29937e BG |
256 | /* counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
257 | if (synapse->signal->id == count->synapses[1].signal->id) | |
aaec1a0f | 258 | *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; |
fae6f62e | 259 | else |
aaec1a0f | 260 | *action = COUNTER_SYNAPSE_ACTION_NONE; |
fae6f62e | 261 | return 0; |
aaec1a0f | 262 | case COUNTER_FUNCTION_QUADRATURE_X4: |
ad29937e | 263 | /* counts up/down on both TI1FP1 and TI2FP2 edges */ |
aaec1a0f | 264 | *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; |
fae6f62e WBG |
265 | return 0; |
266 | default: | |
267 | return -EINVAL; | |
ad29937e | 268 | } |
ad29937e BG |
269 | } |
270 | ||
271 | static const struct counter_ops stm32_timer_cnt_ops = { | |
272 | .count_read = stm32_count_read, | |
273 | .count_write = stm32_count_write, | |
aaec1a0f WBG |
274 | .function_read = stm32_count_function_read, |
275 | .function_write = stm32_count_function_write, | |
276 | .action_read = stm32_action_read, | |
ad29937e BG |
277 | }; |
278 | ||
279 | static struct counter_signal stm32_signals[] = { | |
280 | { | |
281 | .id = 0, | |
282 | .name = "Channel 1 Quadrature A" | |
283 | }, | |
284 | { | |
285 | .id = 1, | |
286 | .name = "Channel 1 Quadrature B" | |
287 | } | |
288 | }; | |
289 | ||
290 | static struct counter_synapse stm32_count_synapses[] = { | |
291 | { | |
292 | .actions_list = stm32_synapse_actions, | |
293 | .num_actions = ARRAY_SIZE(stm32_synapse_actions), | |
294 | .signal = &stm32_signals[0] | |
295 | }, | |
296 | { | |
297 | .actions_list = stm32_synapse_actions, | |
298 | .num_actions = ARRAY_SIZE(stm32_synapse_actions), | |
299 | .signal = &stm32_signals[1] | |
300 | } | |
301 | }; | |
302 | ||
303 | static struct counter_count stm32_counts = { | |
304 | .id = 0, | |
305 | .name = "Channel 1 Count", | |
306 | .functions_list = stm32_count_functions, | |
307 | .num_functions = ARRAY_SIZE(stm32_count_functions), | |
308 | .synapses = stm32_count_synapses, | |
309 | .num_synapses = ARRAY_SIZE(stm32_count_synapses), | |
310 | .ext = stm32_count_ext, | |
311 | .num_ext = ARRAY_SIZE(stm32_count_ext) | |
312 | }; | |
313 | ||
314 | static int stm32_timer_cnt_probe(struct platform_device *pdev) | |
315 | { | |
316 | struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); | |
317 | struct device *dev = &pdev->dev; | |
318 | struct stm32_timer_cnt *priv; | |
e1717d2e UKK |
319 | struct counter_device *counter; |
320 | int ret; | |
ad29937e BG |
321 | |
322 | if (IS_ERR_OR_NULL(ddata)) | |
323 | return -EINVAL; | |
324 | ||
e1717d2e UKK |
325 | counter = devm_counter_alloc(dev, sizeof(*priv)); |
326 | if (!counter) | |
ad29937e BG |
327 | return -ENOMEM; |
328 | ||
e1717d2e UKK |
329 | priv = counter_priv(counter); |
330 | ||
ad29937e BG |
331 | priv->regmap = ddata->regmap; |
332 | priv->clk = ddata->clk; | |
e4c3e133 | 333 | priv->max_arr = ddata->max_arr; |
ad29937e | 334 | |
e1717d2e UKK |
335 | counter->name = dev_name(dev); |
336 | counter->parent = dev; | |
337 | counter->ops = &stm32_timer_cnt_ops; | |
338 | counter->counts = &stm32_counts; | |
339 | counter->num_counts = 1; | |
340 | counter->signals = stm32_signals; | |
341 | counter->num_signals = ARRAY_SIZE(stm32_signals); | |
ad29937e | 342 | |
c5b84255 FG |
343 | platform_set_drvdata(pdev, priv); |
344 | ||
5272145d UKK |
345 | /* Reset input selector to its default input */ |
346 | regmap_write(priv->regmap, TIM_TISEL, 0x0); | |
347 | ||
ad29937e | 348 | /* Register Counter device */ |
e1717d2e UKK |
349 | ret = devm_counter_add(dev, counter); |
350 | if (ret < 0) | |
351 | dev_err_probe(dev, ret, "Failed to add counter\n"); | |
352 | ||
353 | return ret; | |
ad29937e BG |
354 | } |
355 | ||
c5b84255 FG |
356 | static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev) |
357 | { | |
358 | struct stm32_timer_cnt *priv = dev_get_drvdata(dev); | |
359 | ||
360 | /* Only take care of enabled counter: don't disturb other MFD child */ | |
361 | if (priv->enabled) { | |
362 | /* Backup registers that may get lost in low power mode */ | |
363 | regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr); | |
364 | regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr); | |
365 | regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt); | |
366 | regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); | |
367 | ||
368 | /* Disable the counter */ | |
369 | regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); | |
370 | clk_disable(priv->clk); | |
371 | } | |
372 | ||
373 | return pinctrl_pm_select_sleep_state(dev); | |
374 | } | |
375 | ||
376 | static int __maybe_unused stm32_timer_cnt_resume(struct device *dev) | |
377 | { | |
378 | struct stm32_timer_cnt *priv = dev_get_drvdata(dev); | |
379 | int ret; | |
380 | ||
381 | ret = pinctrl_pm_select_default_state(dev); | |
382 | if (ret) | |
383 | return ret; | |
384 | ||
385 | if (priv->enabled) { | |
386 | clk_enable(priv->clk); | |
387 | ||
388 | /* Restore registers that may have been lost */ | |
389 | regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr); | |
390 | regmap_write(priv->regmap, TIM_ARR, priv->bak.arr); | |
391 | regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt); | |
392 | ||
393 | /* Also re-enables the counter */ | |
394 | regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); | |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend, | |
401 | stm32_timer_cnt_resume); | |
402 | ||
ad29937e BG |
403 | static const struct of_device_id stm32_timer_cnt_of_match[] = { |
404 | { .compatible = "st,stm32-timer-counter", }, | |
405 | {}, | |
406 | }; | |
407 | MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match); | |
408 | ||
409 | static struct platform_driver stm32_timer_cnt_driver = { | |
410 | .probe = stm32_timer_cnt_probe, | |
411 | .driver = { | |
412 | .name = "stm32-timer-counter", | |
413 | .of_match_table = stm32_timer_cnt_of_match, | |
c5b84255 | 414 | .pm = &stm32_timer_cnt_pm_ops, |
ad29937e BG |
415 | }, |
416 | }; | |
417 | module_platform_driver(stm32_timer_cnt_driver); | |
418 | ||
419 | MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); | |
420 | MODULE_ALIAS("platform:stm32-timer-counter"); | |
421 | MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver"); | |
422 | MODULE_LICENSE("GPL v2"); | |
3216e551 | 423 | MODULE_IMPORT_NS(COUNTER); |