[linux-2.6-block.git] / drivers / counter / stm32-lptimer-cnt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * STM32 Low-Power Timer Encoder and Counter driver
 *
 * Copyright (C) STMicroelectronics 2017
 *
 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
 *
 * Inspired by 104-quad-8 and stm32-timer-trigger drivers.
 *
 */

#include <linux/bitfield.h>
#include <linux/counter.h>
#include <linux/iio/iio.h>
#include <linux/mfd/stm32-lptimer.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>

struct stm32_lptim_cnt {
	struct counter_device counter;
	struct device *dev;
	struct regmap *regmap;
	struct clk *clk;
	u32 ceiling;
	u32 polarity;
	u32 quadrature_mode;
	bool enabled;
};

static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
{
	u32 val;
	int ret;

	ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
	if (ret)
		return ret;

	return FIELD_GET(STM32_LPTIM_ENABLE, val);
}

static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
					int enable)
{
	int ret;
	u32 val;

	val = FIELD_PREP(STM32_LPTIM_ENABLE, enable);
	ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);
	if (ret)
		return ret;

	if (!enable) {
		clk_disable(priv->clk);
		priv->enabled = false;
		return 0;
	}

	/* LP timer must be enabled before writing CMP & ARR */
	ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
	if (ret)
		return ret;

	ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
	if (ret)
		return ret;

	/* ensure CMP & ARR registers are properly written */
	ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
				       (val & STM32_LPTIM_CMPOK_ARROK),
				       100, 1000);
	if (ret)
		return ret;

	ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
			   STM32_LPTIM_CMPOKCF_ARROKCF);
	if (ret)
		return ret;

	ret = clk_enable(priv->clk);
	if (ret) {
		regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
		return ret;
	}
	priv->enabled = true;

	/* Start LP timer in continuous mode */
	return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
				  STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
}

static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
{
	u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE |
		   STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC;
	u32 val;

	/* Setup LP timer encoder/counter and polarity, without prescaler */
	if (priv->quadrature_mode)
		val = enable ? STM32_LPTIM_ENC : 0;
	else
		val = enable ? STM32_LPTIM_COUNTMODE : 0;
	val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);

	return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);
}

static int stm32_lptim_write_raw(struct iio_dev *indio_dev,
				 struct iio_chan_spec const *chan,
				 int val, int val2, long mask)
{
	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_ENABLE:
		if (val < 0 || val > 1)
			return -EINVAL;

		/* Check nobody uses the timer, or already disabled/enabled */
		ret = stm32_lptim_is_enabled(priv);
		if ((ret < 0) || (!ret && !val))
			return ret;
		if (val && ret)
			return -EBUSY;

		ret = stm32_lptim_setup(priv, val);
		if (ret)
			return ret;
		return stm32_lptim_set_enable_state(priv, val);

	default:
		return -EINVAL;
	}
}

static int stm32_lptim_read_raw(struct iio_dev *indio_dev,
				struct iio_chan_spec const *chan,
				int *val, int *val2, long mask)
{
	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	u32 dat;
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &dat);
		if (ret)
			return ret;
		*val = dat;
		return IIO_VAL_INT;

	case IIO_CHAN_INFO_ENABLE:
		ret = stm32_lptim_is_enabled(priv);
		if (ret < 0)
			return ret;
		*val = ret;
		return IIO_VAL_INT;

	case IIO_CHAN_INFO_SCALE:
		/* Non-quadrature mode: scale = 1 */
		*val = 1;
		*val2 = 0;
		if (priv->quadrature_mode) {
			/*
			 * Quadrature encoder mode:
			 * - both edges, quarter cycle, scale is 0.25
			 * - either rising/falling edge scale is 0.5
			 */
			if (priv->polarity > 1)
				*val2 = 2;
			else
				*val2 = 1;
		}
		return IIO_VAL_FRACTIONAL_LOG2;

	default:
		return -EINVAL;
	}
}

static const struct iio_info stm32_lptim_cnt_iio_info = {
	.read_raw = stm32_lptim_read_raw,
	.write_raw = stm32_lptim_write_raw,
};

static const char *const stm32_lptim_quadrature_modes[] = {
	"non-quadrature",
	"quadrature",
};

static int stm32_lptim_get_quadrature_mode(struct iio_dev *indio_dev,
					   const struct iio_chan_spec *chan)
{
	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);

	return priv->quadrature_mode;
}

static int stm32_lptim_set_quadrature_mode(struct iio_dev *indio_dev,
					   const struct iio_chan_spec *chan,
					   unsigned int type)
{
	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);

	if (stm32_lptim_is_enabled(priv))
		return -EBUSY;

	priv->quadrature_mode = type;

	return 0;
}

static const struct iio_enum stm32_lptim_quadrature_mode_en = {
	.items = stm32_lptim_quadrature_modes,
	.num_items = ARRAY_SIZE(stm32_lptim_quadrature_modes),
	.get = stm32_lptim_get_quadrature_mode,
	.set = stm32_lptim_set_quadrature_mode,
};

static const char * const stm32_lptim_cnt_polarity[] = {
	"rising-edge", "falling-edge", "both-edges",
};

static int stm32_lptim_cnt_get_polarity(struct iio_dev *indio_dev,
					const struct iio_chan_spec *chan)
{
	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);

	return priv->polarity;
}

static int stm32_lptim_cnt_set_polarity(struct iio_dev *indio_dev,
					const struct iio_chan_spec *chan,
					unsigned int type)
{
	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);

	if (stm32_lptim_is_enabled(priv))
		return -EBUSY;

	priv->polarity = type;

	return 0;
}

static const struct iio_enum stm32_lptim_cnt_polarity_en = {
	.items = stm32_lptim_cnt_polarity,
	.num_items = ARRAY_SIZE(stm32_lptim_cnt_polarity),
	.get = stm32_lptim_cnt_get_polarity,
	.set = stm32_lptim_cnt_set_polarity,
};

static ssize_t stm32_lptim_cnt_get_ceiling(struct stm32_lptim_cnt *priv,
					   char *buf)
{
	return snprintf(buf, PAGE_SIZE, "%u\n", priv->ceiling);
}

static ssize_t stm32_lptim_cnt_set_ceiling(struct stm32_lptim_cnt *priv,
					   const char *buf, size_t len)
{
	int ret;

	if (stm32_lptim_is_enabled(priv))
		return -EBUSY;

	ret = kstrtouint(buf, 0, &priv->ceiling);
	if (ret)
		return ret;

	if (priv->ceiling > STM32_LPTIM_MAX_ARR)
		return -EINVAL;

	return len;
}

static ssize_t stm32_lptim_cnt_get_preset_iio(struct iio_dev *indio_dev,
					      uintptr_t private,
					      const struct iio_chan_spec *chan,
					      char *buf)
{
	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);

	return stm32_lptim_cnt_get_ceiling(priv, buf);
}

static ssize_t stm32_lptim_cnt_set_preset_iio(struct iio_dev *indio_dev,
					      uintptr_t private,
					      const struct iio_chan_spec *chan,
					      const char *buf, size_t len)
{
	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);

	return stm32_lptim_cnt_set_ceiling(priv, buf, len);
}

/* LP timer with encoder */
static const struct iio_chan_spec_ext_info stm32_lptim_enc_ext_info[] = {
	{
		.name = "preset",
		.shared = IIO_SEPARATE,
		.read = stm32_lptim_cnt_get_preset_iio,
		.write = stm32_lptim_cnt_set_preset_iio,
	},
	IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
	IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
	IIO_ENUM("quadrature_mode", IIO_SEPARATE,
		 &stm32_lptim_quadrature_mode_en),
	IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_lptim_quadrature_mode_en),
	{}
};

static const struct iio_chan_spec stm32_lptim_enc_channels = {
	.type = IIO_COUNT,
	.channel = 0,
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
			      BIT(IIO_CHAN_INFO_ENABLE) |
			      BIT(IIO_CHAN_INFO_SCALE),
	.ext_info = stm32_lptim_enc_ext_info,
	.indexed = 1,
};

/* LP timer without encoder (counter only) */
static const struct iio_chan_spec_ext_info stm32_lptim_cnt_ext_info[] = {
	{
		.name = "preset",
		.shared = IIO_SEPARATE,
		.read = stm32_lptim_cnt_get_preset_iio,
		.write = stm32_lptim_cnt_set_preset_iio,
	},
	IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
	IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
	{}
};

static const struct iio_chan_spec stm32_lptim_cnt_channels = {
	.type = IIO_COUNT,
	.channel = 0,
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
			      BIT(IIO_CHAN_INFO_ENABLE) |
			      BIT(IIO_CHAN_INFO_SCALE),
	.ext_info = stm32_lptim_cnt_ext_info,
	.indexed = 1,
};

/**
 * enum stm32_lptim_cnt_function - enumerates LPTimer counter & encoder modes
 * @STM32_LPTIM_COUNTER_INCREASE: up count on IN1 rising, falling or both edges
 * @STM32_LPTIM_ENCODER_BOTH_EDGE: count on both edges (IN1 & IN2 quadrature)
 */
enum stm32_lptim_cnt_function {
	STM32_LPTIM_COUNTER_INCREASE,
	STM32_LPTIM_ENCODER_BOTH_EDGE,
};

static enum counter_count_function stm32_lptim_cnt_functions[] = {
	[STM32_LPTIM_COUNTER_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
	[STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
};

enum stm32_lptim_synapse_action {
	STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
	STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
	STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
	STM32_LPTIM_SYNAPSE_ACTION_NONE,
};

static enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
	/* Index must match with stm32_lptim_cnt_polarity[] (priv->polarity) */
	[STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
	[STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
	[STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
	[STM32_LPTIM_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
};

static int stm32_lptim_cnt_read(struct counter_device *counter,
				struct counter_count *count, unsigned long *val)
{
	struct stm32_lptim_cnt *const priv = counter->priv;
	u32 cnt;
	int ret;

	ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
	if (ret)
		return ret;

	*val = cnt;

	return 0;
}

static int stm32_lptim_cnt_function_get(struct counter_device *counter,
					struct counter_count *count,
					size_t *function)
{
	struct stm32_lptim_cnt *const priv = counter->priv;

	if (!priv->quadrature_mode) {
		*function = STM32_LPTIM_COUNTER_INCREASE;
		return 0;
	}

	if (priv->polarity == STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES) {
		*function = STM32_LPTIM_ENCODER_BOTH_EDGE;
		return 0;
	}

	return -EINVAL;
}

static int stm32_lptim_cnt_function_set(struct counter_device *counter,
					struct counter_count *count,
					size_t function)
{
	struct stm32_lptim_cnt *const priv = counter->priv;

	if (stm32_lptim_is_enabled(priv))
		return -EBUSY;

	switch (function) {
	case STM32_LPTIM_COUNTER_INCREASE:
		priv->quadrature_mode = 0;
		return 0;
	case STM32_LPTIM_ENCODER_BOTH_EDGE:
		priv->quadrature_mode = 1;
		priv->polarity = STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES;
		return 0;
	}

	return -EINVAL;
}

static ssize_t stm32_lptim_cnt_enable_read(struct counter_device *counter,
					   struct counter_count *count,
					   void *private, char *buf)
{
	struct stm32_lptim_cnt *const priv = counter->priv;
	int ret;

	ret = stm32_lptim_is_enabled(priv);
	if (ret < 0)
		return ret;

	return scnprintf(buf, PAGE_SIZE, "%u\n", ret);
}

static ssize_t stm32_lptim_cnt_enable_write(struct counter_device *counter,
					    struct counter_count *count,
					    void *private,
					    const char *buf, size_t len)
{
	struct stm32_lptim_cnt *const priv = counter->priv;
	bool enable;
	int ret;

	ret = kstrtobool(buf, &enable);
	if (ret)
		return ret;

	/* Check nobody uses the timer, or already disabled/enabled */
	ret = stm32_lptim_is_enabled(priv);
	if ((ret < 0) || (!ret && !enable))
		return ret;
	if (enable && ret)
		return -EBUSY;

	ret = stm32_lptim_setup(priv, enable);
	if (ret)
		return ret;

	ret = stm32_lptim_set_enable_state(priv, enable);
	if (ret)
		return ret;

	return len;
}

static ssize_t stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
					    struct counter_count *count,
					    void *private, char *buf)
{
	struct stm32_lptim_cnt *const priv = counter->priv;

	return stm32_lptim_cnt_get_ceiling(priv, buf);
}

static ssize_t stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
					     struct counter_count *count,
					     void *private,
					     const char *buf, size_t len)
{
	struct stm32_lptim_cnt *const priv = counter->priv;

	return stm32_lptim_cnt_set_ceiling(priv, buf, len);
}

static const struct counter_count_ext stm32_lptim_cnt_ext[] = {
	{
		.name = "enable",
		.read = stm32_lptim_cnt_enable_read,
		.write = stm32_lptim_cnt_enable_write
	},
	{
		.name = "ceiling",
		.read = stm32_lptim_cnt_ceiling_read,
		.write = stm32_lptim_cnt_ceiling_write
	},
};

static int stm32_lptim_cnt_action_get(struct counter_device *counter,
				      struct counter_count *count,
				      struct counter_synapse *synapse,
				      size_t *action)
{
	struct stm32_lptim_cnt *const priv = counter->priv;
	size_t function;
	int err;

	err = stm32_lptim_cnt_function_get(counter, count, &function);
	if (err)
		return err;

	switch (function) {
	case STM32_LPTIM_COUNTER_INCREASE:
		/* LP Timer acts as up-counter on input 1 */
		if (synapse->signal->id == count->synapses[0].signal->id)
			*action = priv->polarity;
		else
			*action = STM32_LPTIM_SYNAPSE_ACTION_NONE;
		return 0;
	case STM32_LPTIM_ENCODER_BOTH_EDGE:
		*action = priv->polarity;
		return 0;
	}

	return -EINVAL;
}

static int stm32_lptim_cnt_action_set(struct counter_device *counter,
				      struct counter_count *count,
				      struct counter_synapse *synapse,
				      size_t action)
{
	struct stm32_lptim_cnt *const priv = counter->priv;
	size_t function;
	int err;

	if (stm32_lptim_is_enabled(priv))
		return -EBUSY;

	err = stm32_lptim_cnt_function_get(counter, count, &function);
	if (err)
		return err;

	/* only set polarity when in counter mode (on input 1) */
	if (function == STM32_LPTIM_COUNTER_INCREASE
	    && synapse->signal->id == count->synapses[0].signal->id) {
		switch (action) {
		case STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE:
		case STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE:
		case STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES:
			priv->polarity = action;
			return 0;
		}
	}

	return -EINVAL;
}

static const struct counter_ops stm32_lptim_cnt_ops = {
	.count_read = stm32_lptim_cnt_read,
	.function_get = stm32_lptim_cnt_function_get,
	.function_set = stm32_lptim_cnt_function_set,
	.action_get = stm32_lptim_cnt_action_get,
	.action_set = stm32_lptim_cnt_action_set,
};

static struct counter_signal stm32_lptim_cnt_signals[] = {
	{
		.id = 0,
		.name = "Channel 1 Quadrature A"
	},
	{
		.id = 1,
		.name = "Channel 1 Quadrature B"
	}
};

static struct counter_synapse stm32_lptim_cnt_synapses[] = {
	{
		.actions_list = stm32_lptim_cnt_synapse_actions,
		.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
		.signal = &stm32_lptim_cnt_signals[0]
	},
	{
		.actions_list = stm32_lptim_cnt_synapse_actions,
		.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
		.signal = &stm32_lptim_cnt_signals[1]
	}
};

/* LP timer with encoder */
static struct counter_count stm32_lptim_enc_counts = {
	.id = 0,
	.name = "LPTimer Count",
	.functions_list = stm32_lptim_cnt_functions,
	.num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
	.synapses = stm32_lptim_cnt_synapses,
	.num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
	.ext = stm32_lptim_cnt_ext,
	.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
};

/* LP timer without encoder (counter only) */
static struct counter_count stm32_lptim_in1_counts = {
	.id = 0,
	.name = "LPTimer Count",
	.functions_list = stm32_lptim_cnt_functions,
	.num_functions = 1,
	.synapses = stm32_lptim_cnt_synapses,
	.num_synapses = 1,
	.ext = stm32_lptim_cnt_ext,
	.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
};

static int stm32_lptim_cnt_probe(struct platform_device *pdev)
{
	struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
	struct stm32_lptim_cnt *priv;
	struct iio_dev *indio_dev;
	int ret;

	if (IS_ERR_OR_NULL(ddata))
		return -EINVAL;

	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
	if (!indio_dev)
		return -ENOMEM;

	priv = iio_priv(indio_dev);
	priv->dev = &pdev->dev;
	priv->regmap = ddata->regmap;
	priv->clk = ddata->clk;
	priv->ceiling = STM32_LPTIM_MAX_ARR;

	/* Initialize IIO device */
	indio_dev->name = dev_name(&pdev->dev);
	indio_dev->dev.of_node = pdev->dev.of_node;
	indio_dev->info = &stm32_lptim_cnt_iio_info;
	if (ddata->has_encoder)
		indio_dev->channels = &stm32_lptim_enc_channels;
	else
		indio_dev->channels = &stm32_lptim_cnt_channels;
	indio_dev->num_channels = 1;

	/* Initialize Counter device */
	priv->counter.name = dev_name(&pdev->dev);
	priv->counter.parent = &pdev->dev;
	priv->counter.ops = &stm32_lptim_cnt_ops;
	if (ddata->has_encoder) {
		priv->counter.counts = &stm32_lptim_enc_counts;
		priv->counter.num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
	} else {
		priv->counter.counts = &stm32_lptim_in1_counts;
		priv->counter.num_signals = 1;
	}
	priv->counter.num_counts = 1;
	priv->counter.signals = stm32_lptim_cnt_signals;
	priv->counter.priv = priv;

	platform_set_drvdata(pdev, priv);

	ret = devm_iio_device_register(&pdev->dev, indio_dev);
	if (ret)
		return ret;

	return devm_counter_register(&pdev->dev, &priv->counter);
}

#ifdef CONFIG_PM_SLEEP
static int stm32_lptim_cnt_suspend(struct device *dev)
{
	struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
	int ret;

	/* Only take care of enabled counter: don't disturb other MFD child */
	if (priv->enabled) {
		ret = stm32_lptim_setup(priv, 0);
		if (ret)
			return ret;

		ret = stm32_lptim_set_enable_state(priv, 0);
		if (ret)
			return ret;

		/* Force enable state for later resume */
		priv->enabled = true;
	}

	return pinctrl_pm_select_sleep_state(dev);
}

static int stm32_lptim_cnt_resume(struct device *dev)
{
	struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
	int ret;

	ret = pinctrl_pm_select_default_state(dev);
	if (ret)
		return ret;

	if (priv->enabled) {
		priv->enabled = false;
		ret = stm32_lptim_setup(priv, 1);
		if (ret)
			return ret;

		ret = stm32_lptim_set_enable_state(priv, 1);
		if (ret)
			return ret;
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend,
			 stm32_lptim_cnt_resume);

static const struct of_device_id stm32_lptim_cnt_of_match[] = {
	{ .compatible = "st,stm32-lptimer-counter", },
	{},
};
MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);

static struct platform_driver stm32_lptim_cnt_driver = {
	.probe = stm32_lptim_cnt_probe,
	.driver = {
		.name = "stm32-lptimer-counter",
		.of_match_table = stm32_lptim_cnt_of_match,
		.pm = &stm32_lptim_cnt_pm_ops,
	},
};
module_platform_driver(stm32_lptim_cnt_driver);

MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
MODULE_ALIAS("platform:stm32-lptimer-counter");
MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
6e93e261	1	// SPDX-License-Identifier: GPL-2.0
d8958824 FG	2	/*
	3	* STM32 Low-Power Timer Encoder and Counter driver
	4	*
	5	* Copyright (C) STMicroelectronics 2017
	6	*
	7	* Author: Fabrice Gasnier <fabrice.gasnier@st.com>
	8	*
	9	* Inspired by 104-quad-8 and stm32-timer-trigger drivers.
	10	*
d8958824 FG	11	*/
	12
	13	#include <linux/bitfield.h>
597f55e3	14	#include <linux/counter.h>
d8958824 FG	15	#include <linux/iio/iio.h>
	16	#include <linux/mfd/stm32-lptimer.h>
	17	#include <linux/module.h>
6dc3e36f	18	#include <linux/pinctrl/consumer.h>
d8958824 FG	19	#include <linux/platform_device.h>
	20
	21	struct stm32_lptim_cnt {
597f55e3	22	struct counter_device counter;
d8958824 FG	23	struct device *dev;
	24	struct regmap *regmap;
	25	struct clk *clk;
597f55e3	26	u32 ceiling;
d8958824 FG	27	u32 polarity;
d8958824 FG	28	u32 quadrature_mode;
6dc3e36f	29	bool enabled;
d8958824 FG	30	};
	31
	32	static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
	33	{
	34	u32 val;
	35	int ret;
	36
	37	ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
	38	if (ret)
	39	return ret;
	40
	41	return FIELD_GET(STM32_LPTIM_ENABLE, val);
	42	}
	43
	44	static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
	45	int enable)
	46	{
	47	int ret;
	48	u32 val;
	49
	50	val = FIELD_PREP(STM32_LPTIM_ENABLE, enable);
	51	ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);
	52	if (ret)
	53	return ret;
	54
	55	if (!enable) {
	56	clk_disable(priv->clk);
6dc3e36f	57	priv->enabled = false;
d8958824 FG	58	return 0;
	59	}
	60
	61	/* LP timer must be enabled before writing CMP & ARR */
597f55e3	62	ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
d8958824 FG	63	if (ret)
	64	return ret;
	65
	66	ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
	67	if (ret)
	68	return ret;
	69
	70	/* ensure CMP & ARR registers are properly written */
	71	ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
	72	(val & STM32_LPTIM_CMPOK_ARROK),
	73	100, 1000);
	74	if (ret)
	75	return ret;
	76
	77	ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
	78	STM32_LPTIM_CMPOKCF_ARROKCF);
	79	if (ret)
	80	return ret;
	81
	82	ret = clk_enable(priv->clk);
	83	if (ret) {
	84	regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
	85	return ret;
	86	}
6dc3e36f	87	priv->enabled = true;
d8958824 FG	88
	89	/* Start LP timer in continuous mode */
	90	return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
	91	STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
	92	}
	93
	94	static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
	95	{
	96	u32 mask = STM32_LPTIM_ENC \| STM32_LPTIM_COUNTMODE \|
	97	STM32_LPTIM_CKPOL \| STM32_LPTIM_PRESC;
	98	u32 val;
	99
	100	/* Setup LP timer encoder/counter and polarity, without prescaler */
	101	if (priv->quadrature_mode)
	102	val = enable ? STM32_LPTIM_ENC : 0;
	103	else
	104	val = enable ? STM32_LPTIM_COUNTMODE : 0;
	105	val \|= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);
	106
	107	return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);
	108	}
	109
	110	static int stm32_lptim_write_raw(struct iio_dev *indio_dev,
	111	struct iio_chan_spec const *chan,
	112	int val, int val2, long mask)
	113	{
	114	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	115	int ret;
	116
	117	switch (mask) {
	118	case IIO_CHAN_INFO_ENABLE:
	119	if (val < 0 \|\| val > 1)
	120	return -EINVAL;
	121
	122	/* Check nobody uses the timer, or already disabled/enabled */
	123	ret = stm32_lptim_is_enabled(priv);
	124	if ((ret < 0) \|\| (!ret && !val))
	125	return ret;
	126	if (val && ret)
	127	return -EBUSY;
	128
	129	ret = stm32_lptim_setup(priv, val);
	130	if (ret)
	131	return ret;
	132	return stm32_lptim_set_enable_state(priv, val);
	133
	134	default:
	135	return -EINVAL;
	136	}
	137	}
	138
	139	static int stm32_lptim_read_raw(struct iio_dev *indio_dev,
	140	struct iio_chan_spec const *chan,
	141	int val, int val2, long mask)
	142	{
	143	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	144	u32 dat;
	145	int ret;
	146
	147	switch (mask) {
	148	case IIO_CHAN_INFO_RAW:
	149	ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &dat);
	150	if (ret)
	151	return ret;
152	*val = dat;
153	return IIO_VAL_INT;
154
155	case IIO_CHAN_INFO_ENABLE:
156	ret = stm32_lptim_is_enabled(priv);
157	if (ret < 0)
158	return ret;
159	*val = ret;
160	return IIO_VAL_INT;
161
162	case IIO_CHAN_INFO_SCALE:
163	/* Non-quadrature mode: scale = 1 */
164	*val = 1;
165	*val2 = 0;
166	if (priv->quadrature_mode) {
167	/*
168	* Quadrature encoder mode:
169	* - both edges, quarter cycle, scale is 0.25
170	* - either rising/falling edge scale is 0.5
171	*/
172	if (priv->polarity > 1)
173	*val2 = 2;
174	else
175	*val2 = 1;
176	}
177	return IIO_VAL_FRACTIONAL_LOG2;
178
179	default:
180	return -EINVAL;
181	}
182	}
183
184	static const struct iio_info stm32_lptim_cnt_iio_info = {
185	.read_raw = stm32_lptim_read_raw,
186	.write_raw = stm32_lptim_write_raw,
d8958824 FG	187	};
	188
	189	static const char *const stm32_lptim_quadrature_modes[] = {
	190	"non-quadrature",
	191	"quadrature",
	192	};
	193
	194	static int stm32_lptim_get_quadrature_mode(struct iio_dev *indio_dev,
	195	const struct iio_chan_spec *chan)
	196	{
	197	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	198
	199	return priv->quadrature_mode;
	200	}
	201
	202	static int stm32_lptim_set_quadrature_mode(struct iio_dev *indio_dev,
	203	const struct iio_chan_spec *chan,
	204	unsigned int type)
	205	{
	206	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	207
	208	if (stm32_lptim_is_enabled(priv))
	209	return -EBUSY;
	210
	211	priv->quadrature_mode = type;
	212
	213	return 0;
	214	}
	215
	216	static const struct iio_enum stm32_lptim_quadrature_mode_en = {
	217	.items = stm32_lptim_quadrature_modes,
	218	.num_items = ARRAY_SIZE(stm32_lptim_quadrature_modes),
	219	.get = stm32_lptim_get_quadrature_mode,
	220	.set = stm32_lptim_set_quadrature_mode,
	221	};
	222
	223	static const char * const stm32_lptim_cnt_polarity[] = {
	224	"rising-edge", "falling-edge", "both-edges",
	225	};
	226
	227	static int stm32_lptim_cnt_get_polarity(struct iio_dev *indio_dev,
	228	const struct iio_chan_spec *chan)
	229	{
	230	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	231
	232	return priv->polarity;
	233	}
	234
	235	static int stm32_lptim_cnt_set_polarity(struct iio_dev *indio_dev,
	236	const struct iio_chan_spec *chan,
	237	unsigned int type)
	238	{
	239	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	240
	241	if (stm32_lptim_is_enabled(priv))
	242	return -EBUSY;
	243
	244	priv->polarity = type;
	245
	246	return 0;
	247	}
	248
	249	static const struct iio_enum stm32_lptim_cnt_polarity_en = {
	250	.items = stm32_lptim_cnt_polarity,
251	.num_items = ARRAY_SIZE(stm32_lptim_cnt_polarity),
252	.get = stm32_lptim_cnt_get_polarity,
253	.set = stm32_lptim_cnt_set_polarity,
254	};
255
597f55e3 FG	256	static ssize_t stm32_lptim_cnt_get_ceiling(struct stm32_lptim_cnt *priv,
597f55e3 FG	257	char *buf)
d8958824	258	{
597f55e3	259	return snprintf(buf, PAGE_SIZE, "%u\n", priv->ceiling);
d8958824 FG	260	}
d8958824 FG	261
597f55e3 FG	262	static ssize_t stm32_lptim_cnt_set_ceiling(struct stm32_lptim_cnt *priv,
597f55e3 FG	263	const char *buf, size_t len)
d8958824	264	{
d8958824 FG	265	int ret;
	266
	267	if (stm32_lptim_is_enabled(priv))
	268	return -EBUSY;
	269
597f55e3	270	ret = kstrtouint(buf, 0, &priv->ceiling);
d8958824 FG	271	if (ret)
	272	return ret;
	273
597f55e3	274	if (priv->ceiling > STM32_LPTIM_MAX_ARR)
d8958824 FG	275	return -EINVAL;
	276
	277	return len;
	278	}
	279
597f55e3 FG	280	static ssize_t stm32_lptim_cnt_get_preset_iio(struct iio_dev *indio_dev,
	281	uintptr_t private,
	282	const struct iio_chan_spec *chan,
	283	char *buf)
	284	{
	285	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	286
	287	return stm32_lptim_cnt_get_ceiling(priv, buf);
	288	}
	289
	290	static ssize_t stm32_lptim_cnt_set_preset_iio(struct iio_dev *indio_dev,
	291	uintptr_t private,
	292	const struct iio_chan_spec *chan,
	293	const char *buf, size_t len)
	294	{
	295	struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
	296
	297	return stm32_lptim_cnt_set_ceiling(priv, buf, len);
	298	}
	299
d8958824 FG	300	/* LP timer with encoder */
	301	static const struct iio_chan_spec_ext_info stm32_lptim_enc_ext_info[] = {
	302	{
	303	.name = "preset",
	304	.shared = IIO_SEPARATE,
597f55e3 FG	305	.read = stm32_lptim_cnt_get_preset_iio,
597f55e3 FG	306	.write = stm32_lptim_cnt_set_preset_iio,
d8958824 FG	307	},
	308	IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
	309	IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
	310	IIO_ENUM("quadrature_mode", IIO_SEPARATE,
	311	&stm32_lptim_quadrature_mode_en),
	312	IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_lptim_quadrature_mode_en),
	313	{}
	314	};
	315
	316	static const struct iio_chan_spec stm32_lptim_enc_channels = {
	317	.type = IIO_COUNT,
	318	.channel = 0,
	319	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \|
	320	BIT(IIO_CHAN_INFO_ENABLE) \|
	321	BIT(IIO_CHAN_INFO_SCALE),
	322	.ext_info = stm32_lptim_enc_ext_info,
	323	.indexed = 1,
	324	};
	325
	326	/* LP timer without encoder (counter only) */
	327	static const struct iio_chan_spec_ext_info stm32_lptim_cnt_ext_info[] = {
	328	{
	329	.name = "preset",
	330	.shared = IIO_SEPARATE,
597f55e3 FG	331	.read = stm32_lptim_cnt_get_preset_iio,
597f55e3 FG	332	.write = stm32_lptim_cnt_set_preset_iio,
d8958824 FG	333	},
	334	IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
	335	IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
	336	{}
	337	};
	338
	339	static const struct iio_chan_spec stm32_lptim_cnt_channels = {
	340	.type = IIO_COUNT,
	341	.channel = 0,
	342	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \|
	343	BIT(IIO_CHAN_INFO_ENABLE) \|
	344	BIT(IIO_CHAN_INFO_SCALE),
	345	.ext_info = stm32_lptim_cnt_ext_info,
	346	.indexed = 1,
	347	};
	348
597f55e3	349	/**
81ba7e85	350	* enum stm32_lptim_cnt_function - enumerates LPTimer counter & encoder modes
597f55e3 FG	351	* @STM32_LPTIM_COUNTER_INCREASE: up count on IN1 rising, falling or both edges
	352	* @STM32_LPTIM_ENCODER_BOTH_EDGE: count on both edges (IN1 & IN2 quadrature)
	353	*/
	354	enum stm32_lptim_cnt_function {
	355	STM32_LPTIM_COUNTER_INCREASE,
	356	STM32_LPTIM_ENCODER_BOTH_EDGE,
	357	};
	358
	359	static enum counter_count_function stm32_lptim_cnt_functions[] = {
	360	[STM32_LPTIM_COUNTER_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
	361	[STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
	362	};
	363
	364	enum stm32_lptim_synapse_action {
	365	STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
	366	STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
	367	STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
	368	STM32_LPTIM_SYNAPSE_ACTION_NONE,
	369	};
	370
	371	static enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
	372	/* Index must match with stm32_lptim_cnt_polarity[] (priv->polarity) */
	373	[STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
	374	[STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
	375	[STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
	376	[STM32_LPTIM_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
	377	};
	378
	379	static int stm32_lptim_cnt_read(struct counter_device *counter,
d49e6ee2	380	struct counter_count count, unsigned long val)
597f55e3 FG	381	{
	382	struct stm32_lptim_cnt *const priv = counter->priv;
	383	u32 cnt;
	384	int ret;
	385
	386	ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
	387	if (ret)
	388	return ret;
	389
d49e6ee2	390	*val = cnt;
597f55e3 FG	391
	392	return 0;
	393	}
	394
	395	static int stm32_lptim_cnt_function_get(struct counter_device *counter,
	396	struct counter_count *count,
	397	size_t *function)
	398	{
	399	struct stm32_lptim_cnt *const priv = counter->priv;
	400
	401	if (!priv->quadrature_mode) {
	402	*function = STM32_LPTIM_COUNTER_INCREASE;
	403	return 0;
	404	}
	405
	406	if (priv->polarity == STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES) {
	407	*function = STM32_LPTIM_ENCODER_BOTH_EDGE;
	408	return 0;
	409	}
	410
	411	return -EINVAL;
	412	}
	413
	414	static int stm32_lptim_cnt_function_set(struct counter_device *counter,
	415	struct counter_count *count,
	416	size_t function)
	417	{
	418	struct stm32_lptim_cnt *const priv = counter->priv;
	419
	420	if (stm32_lptim_is_enabled(priv))
	421	return -EBUSY;
	422
	423	switch (function) {
	424	case STM32_LPTIM_COUNTER_INCREASE:
	425	priv->quadrature_mode = 0;
	426	return 0;
	427	case STM32_LPTIM_ENCODER_BOTH_EDGE:
	428	priv->quadrature_mode = 1;
	429	priv->polarity = STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES;
	430	return 0;
	431	}
	432
	433	return -EINVAL;
	434	}
	435
	436	static ssize_t stm32_lptim_cnt_enable_read(struct counter_device *counter,
	437	struct counter_count *count,
	438	void private, char buf)
	439	{
	440	struct stm32_lptim_cnt *const priv = counter->priv;
	441	int ret;
	442
	443	ret = stm32_lptim_is_enabled(priv);
	444	if (ret < 0)
	445	return ret;
	446
	447	return scnprintf(buf, PAGE_SIZE, "%u\n", ret);
	448	}
	449
	450	static ssize_t stm32_lptim_cnt_enable_write(struct counter_device *counter,
	451	struct counter_count *count,
	452	void *private,
	453	const char *buf, size_t len)
	454	{
455	struct stm32_lptim_cnt *const priv = counter->priv;
456	bool enable;
457	int ret;
458
459	ret = kstrtobool(buf, &enable);
460	if (ret)
461	return ret;
462
463	/* Check nobody uses the timer, or already disabled/enabled */
464	ret = stm32_lptim_is_enabled(priv);
465	if ((ret < 0) \|\| (!ret && !enable))
466	return ret;
467	if (enable && ret)
468	return -EBUSY;
469
470	ret = stm32_lptim_setup(priv, enable);
471	if (ret)
472	return ret;
473
474	ret = stm32_lptim_set_enable_state(priv, enable);
475	if (ret)
476	return ret;
477
478	return len;
479	}
480
481	static ssize_t stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
482	struct counter_count *count,
483	void private, char buf)
484	{
485	struct stm32_lptim_cnt *const priv = counter->priv;
486
487	return stm32_lptim_cnt_get_ceiling(priv, buf);
488	}
489
490	static ssize_t stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
491	struct counter_count *count,
492	void *private,
493	const char *buf, size_t len)
494	{
495	struct stm32_lptim_cnt *const priv = counter->priv;
496
497	return stm32_lptim_cnt_set_ceiling(priv, buf, len);
498	}
499
500	static const struct counter_count_ext stm32_lptim_cnt_ext[] = {
501	{
502	.name = "enable",
503	.read = stm32_lptim_cnt_enable_read,
504	.write = stm32_lptim_cnt_enable_write
505	},
506	{
507	.name = "ceiling",
508	.read = stm32_lptim_cnt_ceiling_read,
509	.write = stm32_lptim_cnt_ceiling_write
510	},
511	};
512
513	static int stm32_lptim_cnt_action_get(struct counter_device *counter,
514	struct counter_count *count,
515	struct counter_synapse *synapse,
516	size_t *action)
517	{
518	struct stm32_lptim_cnt *const priv = counter->priv;
519	size_t function;
520	int err;
521
522	err = stm32_lptim_cnt_function_get(counter, count, &function);
523	if (err)
524	return err;
525
526	switch (function) {
527	case STM32_LPTIM_COUNTER_INCREASE:
528	/* LP Timer acts as up-counter on input 1 */
529	if (synapse->signal->id == count->synapses[0].signal->id)
530	*action = priv->polarity;
531	else
532	*action = STM32_LPTIM_SYNAPSE_ACTION_NONE;
533	return 0;
534	case STM32_LPTIM_ENCODER_BOTH_EDGE:
535	*action = priv->polarity;
536	return 0;
537	}
538
539	return -EINVAL;
540	}
541
542	static int stm32_lptim_cnt_action_set(struct counter_device *counter,
543	struct counter_count *count,
544	struct counter_synapse *synapse,
545	size_t action)
546	{
547	struct stm32_lptim_cnt *const priv = counter->priv;
548	size_t function;
549	int err;
550
551	if (stm32_lptim_is_enabled(priv))
552	return -EBUSY;
553
554	err = stm32_lptim_cnt_function_get(counter, count, &function);
555	if (err)
556	return err;
557
558	/* only set polarity when in counter mode (on input 1) */
559	if (function == STM32_LPTIM_COUNTER_INCREASE
560	&& synapse->signal->id == count->synapses[0].signal->id) {
561	switch (action) {
562	case STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE:
563	case STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE:
564	case STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES:
565	priv->polarity = action;
566	return 0;
567	}
568	}
569
570	return -EINVAL;
571	}
572
573	static const struct counter_ops stm32_lptim_cnt_ops = {
574	.count_read = stm32_lptim_cnt_read,
575	.function_get = stm32_lptim_cnt_function_get,
576	.function_set = stm32_lptim_cnt_function_set,
577	.action_get = stm32_lptim_cnt_action_get,
578	.action_set = stm32_lptim_cnt_action_set,
579	};
580
581	static struct counter_signal stm32_lptim_cnt_signals[] = {
582	{
583	.id = 0,
584	.name = "Channel 1 Quadrature A"
585	},
586	{
587	.id = 1,
588	.name = "Channel 1 Quadrature B"
589	}
590	};
591
592	static struct counter_synapse stm32_lptim_cnt_synapses[] = {
593	{
594	.actions_list = stm32_lptim_cnt_synapse_actions,
595	.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
596	.signal = &stm32_lptim_cnt_signals[0]
597	},
598	{
599	.actions_list = stm32_lptim_cnt_synapse_actions,
600	.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
601	.signal = &stm32_lptim_cnt_signals[1]
602	}
603	};
604
605	/* LP timer with encoder */
606	static struct counter_count stm32_lptim_enc_counts = {
607	.id = 0,
608	.name = "LPTimer Count",
609	.functions_list = stm32_lptim_cnt_functions,
610	.num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
611	.synapses = stm32_lptim_cnt_synapses,
612	.num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
613	.ext = stm32_lptim_cnt_ext,
614	.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
615	};
616
617	/* LP timer without encoder (counter only) */
618	static struct counter_count stm32_lptim_in1_counts = {
619	.id = 0,
620	.name = "LPTimer Count",
621	.functions_list = stm32_lptim_cnt_functions,
622	.num_functions = 1,
623	.synapses = stm32_lptim_cnt_synapses,
624	.num_synapses = 1,
625	.ext = stm32_lptim_cnt_ext,
626	.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
627	};
628
d8958824 FG	629	static int stm32_lptim_cnt_probe(struct platform_device *pdev)
	630	{
	631	struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
	632	struct stm32_lptim_cnt *priv;
	633	struct iio_dev *indio_dev;
597f55e3	634	int ret;
d8958824 FG	635
	636	if (IS_ERR_OR_NULL(ddata))
	637	return -EINVAL;
	638
	639	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
	640	if (!indio_dev)
	641	return -ENOMEM;
	642
	643	priv = iio_priv(indio_dev);
	644	priv->dev = &pdev->dev;
	645	priv->regmap = ddata->regmap;
	646	priv->clk = ddata->clk;
597f55e3	647	priv->ceiling = STM32_LPTIM_MAX_ARR;
d8958824	648
597f55e3	649	/* Initialize IIO device */
d8958824	650	indio_dev->name = dev_name(&pdev->dev);
d8958824 FG	651	indio_dev->dev.of_node = pdev->dev.of_node;
	652	indio_dev->info = &stm32_lptim_cnt_iio_info;
	653	if (ddata->has_encoder)
	654	indio_dev->channels = &stm32_lptim_enc_channels;
	655	else
	656	indio_dev->channels = &stm32_lptim_cnt_channels;
	657	indio_dev->num_channels = 1;
	658
597f55e3 FG	659	/* Initialize Counter device */
	660	priv->counter.name = dev_name(&pdev->dev);
	661	priv->counter.parent = &pdev->dev;
	662	priv->counter.ops = &stm32_lptim_cnt_ops;
	663	if (ddata->has_encoder) {
	664	priv->counter.counts = &stm32_lptim_enc_counts;
	665	priv->counter.num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
	666	} else {
	667	priv->counter.counts = &stm32_lptim_in1_counts;
	668	priv->counter.num_signals = 1;
	669	}
	670	priv->counter.num_counts = 1;
	671	priv->counter.signals = stm32_lptim_cnt_signals;
	672	priv->counter.priv = priv;
	673
d8958824 FG	674	platform_set_drvdata(pdev, priv);
d8958824 FG	675
597f55e3 FG	676	ret = devm_iio_device_register(&pdev->dev, indio_dev);
	677	if (ret)
	678	return ret;
	679
	680	return devm_counter_register(&pdev->dev, &priv->counter);
d8958824 FG	681	}
d8958824 FG	682
6dc3e36f FG	683	#ifdef CONFIG_PM_SLEEP
	684	static int stm32_lptim_cnt_suspend(struct device *dev)
	685	{
	686	struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
	687	int ret;
	688
	689	/* Only take care of enabled counter: don't disturb other MFD child */
	690	if (priv->enabled) {
	691	ret = stm32_lptim_setup(priv, 0);
	692	if (ret)
	693	return ret;
	694
	695	ret = stm32_lptim_set_enable_state(priv, 0);
	696	if (ret)
	697	return ret;
	698
	699	/* Force enable state for later resume */
	700	priv->enabled = true;
	701	}
	702
	703	return pinctrl_pm_select_sleep_state(dev);
	704	}
	705
	706	static int stm32_lptim_cnt_resume(struct device *dev)
	707	{
	708	struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
	709	int ret;
	710
	711	ret = pinctrl_pm_select_default_state(dev);
	712	if (ret)
	713	return ret;
	714
	715	if (priv->enabled) {
	716	priv->enabled = false;
	717	ret = stm32_lptim_setup(priv, 1);
	718	if (ret)
	719	return ret;
	720
	721	ret = stm32_lptim_set_enable_state(priv, 1);
	722	if (ret)
	723	return ret;
	724	}
	725
	726	return 0;
	727	}
	728	#endif
	729
	730	static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend,
	731	stm32_lptim_cnt_resume);
	732
d8958824 FG	733	static const struct of_device_id stm32_lptim_cnt_of_match[] = {
	734	{ .compatible = "st,stm32-lptimer-counter", },
	735	{},
	736	};
	737	MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);
	738
	739	static struct platform_driver stm32_lptim_cnt_driver = {
	740	.probe = stm32_lptim_cnt_probe,
	741	.driver = {
	742	.name = "stm32-lptimer-counter",
	743	.of_match_table = stm32_lptim_cnt_of_match,
6dc3e36f	744	.pm = &stm32_lptim_cnt_pm_ops,
d8958824 FG	745	},
	746	};
	747	module_platform_driver(stm32_lptim_cnt_driver);
	748
	749	MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
	750	MODULE_ALIAS("platform:stm32-lptimer-counter");
	751	MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver");
	752	MODULE_LICENSE("GPL v2");