[linux-block.git] / drivers / counter / microchip-tcb-capture.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2020 Microchip
 *
 * Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
 */
#include <linux/clk.h>
#include <linux/counter.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <soc/at91/atmel_tcb.h>

#define ATMEL_TC_CMR_MASK	(ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \
				 ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \
				 ATMEL_TC_LDBSTOP)

#define ATMEL_TC_QDEN			BIT(8)
#define ATMEL_TC_POSEN			BIT(9)

struct mchp_tc_data {
	const struct atmel_tcb_config *tc_cfg;
	struct regmap *regmap;
	int qdec_mode;
	int num_channels;
	int channel[2];
};

static const enum counter_function mchp_tc_count_functions[] = {
	COUNTER_FUNCTION_INCREASE,
	COUNTER_FUNCTION_QUADRATURE_X4,
};

static const enum counter_synapse_action mchp_tc_synapse_actions[] = {
	COUNTER_SYNAPSE_ACTION_NONE,
	COUNTER_SYNAPSE_ACTION_RISING_EDGE,
	COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
	COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
};

static struct counter_signal mchp_tc_count_signals[] = {
	{
		.id = 0,
		.name = "Channel A",
	},
	{
		.id = 1,
		.name = "Channel B",
	}
};

static struct counter_synapse mchp_tc_count_synapses[] = {
	{
		.actions_list = mchp_tc_synapse_actions,
		.num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
		.signal = &mchp_tc_count_signals[0]
	},
	{
		.actions_list = mchp_tc_synapse_actions,
		.num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
		.signal = &mchp_tc_count_signals[1]
	}
};

static int mchp_tc_count_function_read(struct counter_device *counter,
				       struct counter_count *count,
				       enum counter_function *function)
{
	struct mchp_tc_data *const priv = counter_priv(counter);

	if (priv->qdec_mode)
		*function = COUNTER_FUNCTION_QUADRATURE_X4;
	else
		*function = COUNTER_FUNCTION_INCREASE;

	return 0;
}

static int mchp_tc_count_function_write(struct counter_device *counter,
					struct counter_count *count,
					enum counter_function function)
{
	struct mchp_tc_data *const priv = counter_priv(counter);
	u32 bmr, cmr;

	regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);

	/* Set capture mode */
	cmr &= ~ATMEL_TC_WAVE;

	switch (function) {
	case COUNTER_FUNCTION_INCREASE:
		priv->qdec_mode = 0;
		/* Set highest rate based on whether soc has gclk or not */
		bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN);
		if (!priv->tc_cfg->has_gclk)
			cmr |= ATMEL_TC_TIMER_CLOCK2;
		else
			cmr |= ATMEL_TC_TIMER_CLOCK1;
		/* Setup the period capture mode */
		cmr |=  ATMEL_TC_CMR_MASK;
		cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0);
		break;
	case COUNTER_FUNCTION_QUADRATURE_X4:
		if (!priv->tc_cfg->has_qdec)
			return -EINVAL;
		/* In QDEC mode settings both channels 0 and 1 are required */
		if (priv->num_channels < 2 || priv->channel[0] != 0 ||
		    priv->channel[1] != 1) {
			pr_err("Invalid channels number or id for quadrature mode\n");
			return -EINVAL;
		}
		priv->qdec_mode = 1;
		bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN;
		cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0;
		break;
	default:
		/* should never reach this path */
		return -EINVAL;
	}

	regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
	regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);

	/* Enable clock and trigger counter */
	regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
		     ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);

	if (priv->qdec_mode) {
		regmap_write(priv->regmap,
			     ATMEL_TC_REG(priv->channel[1], CMR), cmr);
		regmap_write(priv->regmap,
			     ATMEL_TC_REG(priv->channel[1], CCR),
			     ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
	}

	return 0;
}

static int mchp_tc_count_signal_read(struct counter_device *counter,
				     struct counter_signal *signal,
				     enum counter_signal_level *lvl)
{
	struct mchp_tc_data *const priv = counter_priv(counter);
	bool sigstatus;
	u32 sr;

	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);

	if (signal->id == 1)
		sigstatus = (sr & ATMEL_TC_MTIOB);
	else
		sigstatus = (sr & ATMEL_TC_MTIOA);

	*lvl = sigstatus ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;

	return 0;
}

static int mchp_tc_count_action_read(struct counter_device *counter,
				     struct counter_count *count,
				     struct counter_synapse *synapse,
				     enum counter_synapse_action *action)
{
	struct mchp_tc_data *const priv = counter_priv(counter);
	u32 cmr;

	if (priv->qdec_mode) {
		*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
		return 0;
	}

	/* Only TIOA signal is evaluated in non-QDEC mode */
	if (synapse->signal->id != 0) {
		*action = COUNTER_SYNAPSE_ACTION_NONE;
		return 0;
	}

	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);

	switch (cmr & ATMEL_TC_ETRGEDG) {
	default:
		*action = COUNTER_SYNAPSE_ACTION_NONE;
		break;
	case ATMEL_TC_ETRGEDG_RISING:
		*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
		break;
	case ATMEL_TC_ETRGEDG_FALLING:
		*action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
		break;
	case ATMEL_TC_ETRGEDG_BOTH:
		*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
		break;
	}

	return 0;
}

static int mchp_tc_count_action_write(struct counter_device *counter,
				      struct counter_count *count,
				      struct counter_synapse *synapse,
				      enum counter_synapse_action action)
{
	struct mchp_tc_data *const priv = counter_priv(counter);
	u32 edge = ATMEL_TC_ETRGEDG_NONE;

	/* QDEC mode is rising edge only; only TIOA handled in non-QDEC mode */
	if (priv->qdec_mode || synapse->signal->id != 0)
		return -EINVAL;

	switch (action) {
	case COUNTER_SYNAPSE_ACTION_NONE:
		edge = ATMEL_TC_ETRGEDG_NONE;
		break;
	case COUNTER_SYNAPSE_ACTION_RISING_EDGE:
		edge = ATMEL_TC_ETRGEDG_RISING;
		break;
	case COUNTER_SYNAPSE_ACTION_FALLING_EDGE:
		edge = ATMEL_TC_ETRGEDG_FALLING;
		break;
	case COUNTER_SYNAPSE_ACTION_BOTH_EDGES:
		edge = ATMEL_TC_ETRGEDG_BOTH;
		break;
	default:
		/* should never reach this path */
		return -EINVAL;
	}

	return regmap_write_bits(priv->regmap,
				ATMEL_TC_REG(priv->channel[0], CMR),
				ATMEL_TC_ETRGEDG, edge);
}

static int mchp_tc_count_read(struct counter_device *counter,
			      struct counter_count *count, u64 *val)
{
	struct mchp_tc_data *const priv = counter_priv(counter);
	u32 cnt;

	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
	*val = cnt;

	return 0;
}

static struct counter_count mchp_tc_counts[] = {
	{
		.id = 0,
		.name = "Timer Counter",
		.functions_list = mchp_tc_count_functions,
		.num_functions = ARRAY_SIZE(mchp_tc_count_functions),
		.synapses = mchp_tc_count_synapses,
		.num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
	},
};

static const struct counter_ops mchp_tc_ops = {
	.signal_read    = mchp_tc_count_signal_read,
	.count_read     = mchp_tc_count_read,
	.function_read  = mchp_tc_count_function_read,
	.function_write = mchp_tc_count_function_write,
	.action_read    = mchp_tc_count_action_read,
	.action_write   = mchp_tc_count_action_write
};

static const struct atmel_tcb_config tcb_rm9200_config = {
		.counter_width = 16,
};

static const struct atmel_tcb_config tcb_sam9x5_config = {
		.counter_width = 32,
};

static const struct atmel_tcb_config tcb_sama5d2_config = {
		.counter_width = 32,
		.has_gclk = true,
		.has_qdec = true,
};

static const struct atmel_tcb_config tcb_sama5d3_config = {
		.counter_width = 32,
		.has_qdec = true,
};

static const struct of_device_id atmel_tc_of_match[] = {
	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
	{ .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
	{ /* sentinel */ }
};

static void mchp_tc_clk_remove(void *ptr)
{
	clk_disable_unprepare((struct clk *)ptr);
}

static int mchp_tc_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	const struct atmel_tcb_config *tcb_config;
	const struct of_device_id *match;
	struct counter_device *counter;
	struct mchp_tc_data *priv;
	char clk_name[7];
	struct regmap *regmap;
	struct clk *clk[3];
	int channel;
	int ret, i;

	counter = devm_counter_alloc(&pdev->dev, sizeof(*priv));
	if (!counter)
		return -ENOMEM;
	priv = counter_priv(counter);

	match = of_match_node(atmel_tc_of_match, np->parent);
	tcb_config = match->data;
	if (!tcb_config) {
		dev_err(&pdev->dev, "No matching parent node found\n");
		return -ENODEV;
	}

	regmap = syscon_node_to_regmap(np->parent);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	/* max. channels number is 2 when in QDEC mode */
	priv->num_channels = of_property_count_u32_elems(np, "reg");
	if (priv->num_channels < 0) {
		dev_err(&pdev->dev, "Invalid or missing channel\n");
		return -EINVAL;
	}

	/* Register channels and initialize clocks */
	for (i = 0; i < priv->num_channels; i++) {
		ret = of_property_read_u32_index(np, "reg", i, &channel);
		if (ret < 0 || channel > 2)
			return -ENODEV;

		priv->channel[i] = channel;

		snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);

		clk[i] = of_clk_get_by_name(np->parent, clk_name);
		if (IS_ERR(clk[i])) {
			/* Fallback to t0_clk */
			clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
			if (IS_ERR(clk[i]))
				return PTR_ERR(clk[i]);
		}

		ret = clk_prepare_enable(clk[i]);
		if (ret)
			return ret;

		ret = devm_add_action_or_reset(&pdev->dev,
					       mchp_tc_clk_remove,
					       clk[i]);
		if (ret)
			return ret;

		dev_dbg(&pdev->dev,
			"Initialized capture mode on channel %d\n",
			channel);
	}

	priv->tc_cfg = tcb_config;
	priv->regmap = regmap;
	counter->name = dev_name(&pdev->dev);
	counter->parent = &pdev->dev;
	counter->ops = &mchp_tc_ops;
	counter->num_counts = ARRAY_SIZE(mchp_tc_counts);
	counter->counts = mchp_tc_counts;
	counter->num_signals = ARRAY_SIZE(mchp_tc_count_signals);
	counter->signals = mchp_tc_count_signals;

	ret = devm_counter_add(&pdev->dev, counter);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n");

	return 0;
}

static const struct of_device_id mchp_tc_dt_ids[] = {
	{ .compatible = "microchip,tcb-capture", },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);

static struct platform_driver mchp_tc_driver = {
	.probe = mchp_tc_probe,
	.driver = {
		.name = "microchip-tcb-capture",
		.of_match_table = mchp_tc_dt_ids,
	},
};
module_platform_driver(mchp_tc_driver);

MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
MODULE_DESCRIPTION("Microchip TCB Capture driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(COUNTER);
Commit	Line	Data
106b1041	1	// SPDX-License-Identifier: GPL-2.0-only
fe90fcab	2	/*
106b1041 KB	3	* Copyright (C) 2020 Microchip
	4	*
	5	* Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
	6	*/
	7	#include <linux/clk.h>
	8	#include <linux/counter.h>
	9	#include <linux/mfd/syscon.h>
	10	#include <linux/module.h>
	11	#include <linux/mutex.h>
	12	#include <linux/of.h>
106b1041 KB	13	#include <linux/platform_device.h>
	14	#include <linux/regmap.h>
	15	#include <soc/at91/atmel_tcb.h>
	16
	17	#define ATMEL_TC_CMR_MASK (ATMEL_TC_LDRA_RISING \| ATMEL_TC_LDRB_FALLING \| \
	18	ATMEL_TC_ETRGEDG_RISING \| ATMEL_TC_LDBDIS \| \
	19	ATMEL_TC_LDBSTOP)
	20
	21	#define ATMEL_TC_QDEN BIT(8)
	22	#define ATMEL_TC_POSEN BIT(9)
	23
	24	struct mchp_tc_data {
	25	const struct atmel_tcb_config *tc_cfg;
106b1041 KB	26	struct regmap *regmap;
	27	int qdec_mode;
	28	int num_channels;
	29	int channel[2];
106b1041 KB	30	};
106b1041 KB	31
394a0150	32	static const enum counter_function mchp_tc_count_functions[] = {
aaec1a0f WBG	33	COUNTER_FUNCTION_INCREASE,
aaec1a0f WBG	34	COUNTER_FUNCTION_QUADRATURE_X4,
106b1041 KB	35	};
106b1041 KB	36
0056a405	37	static const enum counter_synapse_action mchp_tc_synapse_actions[] = {
aaec1a0f WBG	38	COUNTER_SYNAPSE_ACTION_NONE,
	39	COUNTER_SYNAPSE_ACTION_RISING_EDGE,
	40	COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
	41	COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
106b1041 KB	42	};
	43
	44	static struct counter_signal mchp_tc_count_signals[] = {
	45	{
	46	.id = 0,
	47	.name = "Channel A",
	48	},
	49	{
	50	.id = 1,
	51	.name = "Channel B",
	52	}
	53	};
	54
	55	static struct counter_synapse mchp_tc_count_synapses[] = {
	56	{
	57	.actions_list = mchp_tc_synapse_actions,
	58	.num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
	59	.signal = &mchp_tc_count_signals[0]
	60	},
	61	{
	62	.actions_list = mchp_tc_synapse_actions,
	63	.num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
	64	.signal = &mchp_tc_count_signals[1]
	65	}
	66	};
	67
aaec1a0f WBG	68	static int mchp_tc_count_function_read(struct counter_device *counter,
	69	struct counter_count *count,
	70	enum counter_function *function)
106b1041	71	{
a49ede82	72	struct mchp_tc_data *const priv = counter_priv(counter);
106b1041 KB	73
106b1041 KB	74	if (priv->qdec_mode)
aaec1a0f	75	*function = COUNTER_FUNCTION_QUADRATURE_X4;
106b1041	76	else
aaec1a0f	77	*function = COUNTER_FUNCTION_INCREASE;
106b1041 KB	78
	79	return 0;
	80	}
	81
aaec1a0f WBG	82	static int mchp_tc_count_function_write(struct counter_device *counter,
	83	struct counter_count *count,
	84	enum counter_function function)
106b1041	85	{
a49ede82	86	struct mchp_tc_data *const priv = counter_priv(counter);
106b1041 KB	87	u32 bmr, cmr;
	88
	89	regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
	90	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
	91
	92	/* Set capture mode */
	93	cmr &= ~ATMEL_TC_WAVE;
	94
	95	switch (function) {
aaec1a0f	96	case COUNTER_FUNCTION_INCREASE:
106b1041 KB	97	priv->qdec_mode = 0;
	98	/* Set highest rate based on whether soc has gclk or not */
	99	bmr &= ~(ATMEL_TC_QDEN \| ATMEL_TC_POSEN);
df8fdd01	100	if (!priv->tc_cfg->has_gclk)
106b1041 KB	101	cmr \|= ATMEL_TC_TIMER_CLOCK2;
	102	else
	103	cmr \|= ATMEL_TC_TIMER_CLOCK1;
	104	/* Setup the period capture mode */
	105	cmr \|= ATMEL_TC_CMR_MASK;
	106	cmr &= ~(ATMEL_TC_ABETRG \| ATMEL_TC_XC0);
	107	break;
aaec1a0f	108	case COUNTER_FUNCTION_QUADRATURE_X4:
106b1041 KB	109	if (!priv->tc_cfg->has_qdec)
	110	return -EINVAL;
	111	/* In QDEC mode settings both channels 0 and 1 are required */
	112	if (priv->num_channels < 2 \|\| priv->channel[0] != 0 \|\|
	113	priv->channel[1] != 1) {
	114	pr_err("Invalid channels number or id for quadrature mode\n");
	115	return -EINVAL;
	116	}
	117	priv->qdec_mode = 1;
	118	bmr \|= ATMEL_TC_QDEN \| ATMEL_TC_POSEN;
	119	cmr \|= ATMEL_TC_ETRGEDG_RISING \| ATMEL_TC_ABETRG \| ATMEL_TC_XC0;
	120	break;
b11eed15 WBG	121	default:
	122	/* should never reach this path */
	123	return -EINVAL;
106b1041 KB	124	}
	125
	126	regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
	127	regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
	128
	129	/* Enable clock and trigger counter */
	130	regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
	131	ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG);
	132
	133	if (priv->qdec_mode) {
	134	regmap_write(priv->regmap,
	135	ATMEL_TC_REG(priv->channel[1], CMR), cmr);
	136	regmap_write(priv->regmap,
	137	ATMEL_TC_REG(priv->channel[1], CCR),
	138	ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG);
	139	}
	140
	141	return 0;
	142	}
	143
	144	static int mchp_tc_count_signal_read(struct counter_device *counter,
	145	struct counter_signal *signal,
493b938a	146	enum counter_signal_level *lvl)
106b1041	147	{
a49ede82	148	struct mchp_tc_data *const priv = counter_priv(counter);
106b1041 KB	149	bool sigstatus;
	150	u32 sr;
	151
	152	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
	153
d917a62a	154	if (signal->id == 1)
106b1041 KB	155	sigstatus = (sr & ATMEL_TC_MTIOB);
	156	else
	157	sigstatus = (sr & ATMEL_TC_MTIOA);
	158
493b938a	159	*lvl = sigstatus ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
106b1041 KB	160
	161	return 0;
	162	}
	163
aaec1a0f WBG	164	static int mchp_tc_count_action_read(struct counter_device *counter,
	165	struct counter_count *count,
	166	struct counter_synapse *synapse,
	167	enum counter_synapse_action *action)
106b1041	168	{
a49ede82	169	struct mchp_tc_data *const priv = counter_priv(counter);
106b1041 KB	170	u32 cmr;
106b1041 KB	171
d917a62a WBG	172	if (priv->qdec_mode) {
	173	*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
	174	return 0;
	175	}
	176
	177	/* Only TIOA signal is evaluated in non-QDEC mode */
	178	if (synapse->signal->id != 0) {
	179	*action = COUNTER_SYNAPSE_ACTION_NONE;
	180	return 0;
	181	}
	182
106b1041 KB	183	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
106b1041 KB	184
3418bd7c WBG	185	switch (cmr & ATMEL_TC_ETRGEDG) {
3418bd7c WBG	186	default:
aaec1a0f	187	*action = COUNTER_SYNAPSE_ACTION_NONE;
3418bd7c WBG	188	break;
3418bd7c WBG	189	case ATMEL_TC_ETRGEDG_RISING:
aaec1a0f	190	*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
3418bd7c WBG	191	break;
3418bd7c WBG	192	case ATMEL_TC_ETRGEDG_FALLING:
aaec1a0f	193	*action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
3418bd7c WBG	194	break;
3418bd7c WBG	195	case ATMEL_TC_ETRGEDG_BOTH:
aaec1a0f	196	*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
3418bd7c WBG	197	break;
3418bd7c WBG	198	}
106b1041 KB	199
	200	return 0;
	201	}
	202
aaec1a0f WBG	203	static int mchp_tc_count_action_write(struct counter_device *counter,
	204	struct counter_count *count,
	205	struct counter_synapse *synapse,
	206	enum counter_synapse_action action)
106b1041	207	{
a49ede82	208	struct mchp_tc_data *const priv = counter_priv(counter);
106b1041 KB	209	u32 edge = ATMEL_TC_ETRGEDG_NONE;
106b1041 KB	210
d917a62a WBG	211	/* QDEC mode is rising edge only; only TIOA handled in non-QDEC mode */
d917a62a WBG	212	if (priv->qdec_mode \|\| synapse->signal->id != 0)
106b1041 KB	213	return -EINVAL;
	214
	215	switch (action) {
aaec1a0f	216	case COUNTER_SYNAPSE_ACTION_NONE:
106b1041 KB	217	edge = ATMEL_TC_ETRGEDG_NONE;
106b1041 KB	218	break;
aaec1a0f	219	case COUNTER_SYNAPSE_ACTION_RISING_EDGE:
106b1041 KB	220	edge = ATMEL_TC_ETRGEDG_RISING;
106b1041 KB	221	break;
aaec1a0f	222	case COUNTER_SYNAPSE_ACTION_FALLING_EDGE:
106b1041 KB	223	edge = ATMEL_TC_ETRGEDG_FALLING;
106b1041 KB	224	break;
aaec1a0f	225	case COUNTER_SYNAPSE_ACTION_BOTH_EDGES:
106b1041 KB	226	edge = ATMEL_TC_ETRGEDG_BOTH;
106b1041 KB	227	break;
b11eed15 WBG	228	default:
	229	/* should never reach this path */
	230	return -EINVAL;
106b1041 KB	231	}
	232
	233	return regmap_write_bits(priv->regmap,
	234	ATMEL_TC_REG(priv->channel[0], CMR),
	235	ATMEL_TC_ETRGEDG, edge);
	236	}
	237
	238	static int mchp_tc_count_read(struct counter_device *counter,
aaec1a0f	239	struct counter_count count, u64 val)
106b1041	240	{
a49ede82	241	struct mchp_tc_data *const priv = counter_priv(counter);
106b1041 KB	242	u32 cnt;
	243
	244	regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
	245	*val = cnt;
	246
	247	return 0;
	248	}
	249
	250	static struct counter_count mchp_tc_counts[] = {
	251	{
	252	.id = 0,
	253	.name = "Timer Counter",
	254	.functions_list = mchp_tc_count_functions,
	255	.num_functions = ARRAY_SIZE(mchp_tc_count_functions),
	256	.synapses = mchp_tc_count_synapses,
	257	.num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
	258	},
	259	};
	260
0854fa22	261	static const struct counter_ops mchp_tc_ops = {
aaec1a0f WBG	262	.signal_read = mchp_tc_count_signal_read,
	263	.count_read = mchp_tc_count_read,
	264	.function_read = mchp_tc_count_function_read,
	265	.function_write = mchp_tc_count_function_write,
	266	.action_read = mchp_tc_count_action_read,
	267	.action_write = mchp_tc_count_action_write
106b1041 KB	268	};
	269
	270	static const struct atmel_tcb_config tcb_rm9200_config = {
	271	.counter_width = 16,
	272	};
	273
	274	static const struct atmel_tcb_config tcb_sam9x5_config = {
	275	.counter_width = 32,
	276	};
	277
	278	static const struct atmel_tcb_config tcb_sama5d2_config = {
	279	.counter_width = 32,
	280	.has_gclk = true,
	281	.has_qdec = true,
	282	};
	283
	284	static const struct atmel_tcb_config tcb_sama5d3_config = {
	285	.counter_width = 32,
	286	.has_qdec = true,
	287	};
	288
	289	static const struct of_device_id atmel_tc_of_match[] = {
	290	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	291	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
	292	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
	293	{ .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
	294	{ /* sentinel */ }
	295	};
	296
	297	static void mchp_tc_clk_remove(void *ptr)
	298	{
	299	clk_disable_unprepare((struct clk *)ptr);
	300	}
	301
	302	static int mchp_tc_probe(struct platform_device *pdev)
	303	{
	304	struct device_node *np = pdev->dev.of_node;
	305	const struct atmel_tcb_config *tcb_config;
	306	const struct of_device_id *match;
5998ea62	307	struct counter_device *counter;
106b1041 KB	308	struct mchp_tc_data *priv;
	309	char clk_name[7];
	310	struct regmap *regmap;
	311	struct clk *clk[3];
	312	int channel;
	313	int ret, i;
	314
5998ea62 UKK	315	counter = devm_counter_alloc(&pdev->dev, sizeof(*priv));
5998ea62 UKK	316	if (!counter)
106b1041	317	return -ENOMEM;
5998ea62	318	priv = counter_priv(counter);
106b1041	319
106b1041 KB	320	match = of_match_node(atmel_tc_of_match, np->parent);
	321	tcb_config = match->data;
	322	if (!tcb_config) {
	323	dev_err(&pdev->dev, "No matching parent node found\n");
	324	return -ENODEV;
	325	}
	326
	327	regmap = syscon_node_to_regmap(np->parent);
ab3300de DC	328	if (IS_ERR(regmap))
ab3300de DC	329	return PTR_ERR(regmap);
106b1041 KB	330
	331	/* max. channels number is 2 when in QDEC mode */
	332	priv->num_channels = of_property_count_u32_elems(np, "reg");
	333	if (priv->num_channels < 0) {
	334	dev_err(&pdev->dev, "Invalid or missing channel\n");
	335	return -EINVAL;
	336	}
	337
	338	/* Register channels and initialize clocks */
	339	for (i = 0; i < priv->num_channels; i++) {
	340	ret = of_property_read_u32_index(np, "reg", i, &channel);
	341	if (ret < 0 \|\| channel > 2)
	342	return -ENODEV;
	343
	344	priv->channel[i] = channel;
	345
	346	snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);
	347
	348	clk[i] = of_clk_get_by_name(np->parent, clk_name);
	349	if (IS_ERR(clk[i])) {
	350	/* Fallback to t0_clk */
	351	clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
	352	if (IS_ERR(clk[i]))
	353	return PTR_ERR(clk[i]);
	354	}
	355
	356	ret = clk_prepare_enable(clk[i]);
	357	if (ret)
	358	return ret;
	359
	360	ret = devm_add_action_or_reset(&pdev->dev,
	361	mchp_tc_clk_remove,
	362	clk[i]);
	363	if (ret)
	364	return ret;
	365
	366	dev_dbg(&pdev->dev,
	367	"Initialized capture mode on channel %d\n",
	368	channel);
	369	}
	370
	371	priv->tc_cfg = tcb_config;
	372	priv->regmap = regmap;
5998ea62 UKK	373	counter->name = dev_name(&pdev->dev);
	374	counter->parent = &pdev->dev;
	375	counter->ops = &mchp_tc_ops;
	376	counter->num_counts = ARRAY_SIZE(mchp_tc_counts);
	377	counter->counts = mchp_tc_counts;
	378	counter->num_signals = ARRAY_SIZE(mchp_tc_count_signals);
	379	counter->signals = mchp_tc_count_signals;
	380
	381	ret = devm_counter_add(&pdev->dev, counter);
	382	if (ret < 0)
	383	return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n");
	384
	385	return 0;
106b1041 KB	386	}
	387
	388	static const struct of_device_id mchp_tc_dt_ids[] = {
	389	{ .compatible = "microchip,tcb-capture", },
	390	{ /* sentinel */ },
	391	};
	392	MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);
	393
	394	static struct platform_driver mchp_tc_driver = {
	395	.probe = mchp_tc_probe,
	396	.driver = {
	397	.name = "microchip-tcb-capture",
	398	.of_match_table = mchp_tc_dt_ids,
	399	},
	400	};
	401	module_platform_driver(mchp_tc_driver);
	402
	403	MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
	404	MODULE_DESCRIPTION("Microchip TCB Capture driver");
	405	MODULE_LICENSE("GPL v2");
3216e551	406	MODULE_IMPORT_NS(COUNTER);