Commit | Line | Data |
---|---|---|
e184e2be | 1 | // SPDX-License-Identifier: GPL-2.0+ |
8cb9b9fb | 2 | /* |
262a07ac HS |
3 | * adl_pci9111.c |
4 | * Hardware driver for PCI9111 ADLink cards: PCI-9111HR | |
5 | * Copyright (C) 2002-2005 Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr> | |
262a07ac | 6 | */ |
8cb9b9fb EP |
7 | |
8 | /* | |
262a07ac HS |
9 | * Driver: adl_pci9111 |
10 | * Description: Adlink PCI-9111HR | |
11 | * Devices: [ADLink] PCI-9111HR (adl_pci9111) | |
12 | * Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr> | |
13 | * Status: experimental | |
14 | * | |
15 | * Configuration options: not applicable, uses PCI auto config | |
16 | * | |
17 | * Supports: | |
18 | * - ai_insn read | |
19 | * - ao_insn read/write | |
20 | * - di_insn read | |
21 | * - do_insn read/write | |
22 | * - ai_do_cmd mode with the following sources: | |
23 | * - start_src TRIG_NOW | |
24 | * - scan_begin_src TRIG_FOLLOW TRIG_TIMER TRIG_EXT | |
25 | * - convert_src TRIG_TIMER TRIG_EXT | |
26 | * - scan_end_src TRIG_COUNT | |
27 | * - stop_src TRIG_COUNT TRIG_NONE | |
28 | * | |
29 | * The scanned channels must be consecutive and start from 0. They must | |
30 | * all have the same range and aref. | |
31 | */ | |
8cb9b9fb EP |
32 | |
33 | /* | |
262a07ac HS |
34 | * TODO: |
35 | * - Really test implemented functionality. | |
36 | * - Add support for the PCI-9111DG with a probe routine to identify | |
37 | * the card type (perhaps with the help of the channel number readback | |
38 | * of the A/D Data register). | |
39 | * - Add external multiplexer support. | |
40 | */ | |
8cb9b9fb | 41 | |
ce157f80 | 42 | #include <linux/module.h> |
8cb9b9fb | 43 | #include <linux/delay.h> |
70265d24 | 44 | #include <linux/interrupt.h> |
df0e68c1 | 45 | #include <linux/comedi/comedi_pci.h> |
44fb7aff | 46 | #include <linux/comedi/comedi_8254.h> |
33782dd5 | 47 | |
fc09ec34 | 48 | #include "plx9052.h" |
8cb9b9fb | 49 | |
8cb9b9fb EP |
50 | #define PCI9111_FIFO_HALF_SIZE 512 |
51 | ||
8cb9b9fb | 52 | #define PCI9111_AI_ACQUISITION_PERIOD_MIN_NS 10000 |
8cb9b9fb EP |
53 | |
54 | #define PCI9111_RANGE_SETTING_DELAY 10 | |
55 | #define PCI9111_AI_INSTANT_READ_UDELAY_US 2 | |
8cb9b9fb | 56 | |
8c7524e6 HS |
57 | /* |
58 | * IO address map and bit defines | |
59 | */ | |
60 | #define PCI9111_AI_FIFO_REG 0x00 | |
61 | #define PCI9111_AO_REG 0x00 | |
62 | #define PCI9111_DIO_REG 0x02 | |
63 | #define PCI9111_EDIO_REG 0x04 | |
64 | #define PCI9111_AI_CHANNEL_REG 0x06 | |
65 | #define PCI9111_AI_RANGE_STAT_REG 0x08 | |
f8d863cb HS |
66 | #define PCI9111_AI_STAT_AD_BUSY BIT(7) |
67 | #define PCI9111_AI_STAT_FF_FF BIT(6) | |
68 | #define PCI9111_AI_STAT_FF_HF BIT(5) | |
69 | #define PCI9111_AI_STAT_FF_EF BIT(4) | |
68e41298 HS |
70 | #define PCI9111_AI_RANGE(x) (((x) & 0x7) << 0) |
71 | #define PCI9111_AI_RANGE_MASK PCI9111_AI_RANGE(7) | |
8c7524e6 | 72 | #define PCI9111_AI_TRIG_CTRL_REG 0x0a |
f8d863cb HS |
73 | #define PCI9111_AI_TRIG_CTRL_TRGEVENT BIT(5) |
74 | #define PCI9111_AI_TRIG_CTRL_POTRG BIT(4) | |
75 | #define PCI9111_AI_TRIG_CTRL_PTRG BIT(3) | |
76 | #define PCI9111_AI_TRIG_CTRL_ETIS BIT(2) | |
77 | #define PCI9111_AI_TRIG_CTRL_TPST BIT(1) | |
78 | #define PCI9111_AI_TRIG_CTRL_ASCAN BIT(0) | |
8c7524e6 | 79 | #define PCI9111_INT_CTRL_REG 0x0c |
f8d863cb HS |
80 | #define PCI9111_INT_CTRL_ISC2 BIT(3) |
81 | #define PCI9111_INT_CTRL_FFEN BIT(2) | |
82 | #define PCI9111_INT_CTRL_ISC1 BIT(1) | |
83 | #define PCI9111_INT_CTRL_ISC0 BIT(0) | |
8c7524e6 HS |
84 | #define PCI9111_SOFT_TRIG_REG 0x0e |
85 | #define PCI9111_8254_BASE_REG 0x40 | |
86 | #define PCI9111_INT_CLR_REG 0x48 | |
8cb9b9fb | 87 | |
fc09ec34 HS |
88 | /* PLX 9052 Local Interrupt 1 enabled and active */ |
89 | #define PCI9111_LI1_ACTIVE (PLX9052_INTCSR_LI1ENAB | \ | |
90 | PLX9052_INTCSR_LI1STAT) | |
91 | ||
92 | /* PLX 9052 Local Interrupt 2 enabled and active */ | |
93 | #define PCI9111_LI2_ACTIVE (PLX9052_INTCSR_LI2ENAB | \ | |
94 | PLX9052_INTCSR_LI2STAT) | |
95 | ||
afa6ac4a | 96 | static const struct comedi_lrange pci9111_ai_range = { |
7cd10fa6 | 97 | 5, { |
afa6ac4a HS |
98 | BIP_RANGE(10), |
99 | BIP_RANGE(5), | |
100 | BIP_RANGE(2.5), | |
101 | BIP_RANGE(1.25), | |
102 | BIP_RANGE(0.625) | |
103 | } | |
8cb9b9fb EP |
104 | }; |
105 | ||
c350fa19 | 106 | struct pci9111_private_data { |
293b048a | 107 | unsigned long lcr_io_base; |
8cb9b9fb | 108 | |
8cb9b9fb | 109 | unsigned int scan_delay; |
8cb9b9fb EP |
110 | unsigned int chunk_counter; |
111 | unsigned int chunk_num_samples; | |
112 | ||
b909ba8f | 113 | unsigned short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE]; |
c350fa19 | 114 | }; |
8cb9b9fb | 115 | |
8cb9b9fb | 116 | static void plx9050_interrupt_control(unsigned long io_base, |
0756f8d7 HS |
117 | bool int1_enable, |
118 | bool int1_active_high, | |
119 | bool int2_enable, | |
120 | bool int2_active_high, | |
0a85b6f0 | 121 | bool interrupt_enable) |
8cb9b9fb EP |
122 | { |
123 | int flags = 0; | |
124 | ||
0756f8d7 | 125 | if (int1_enable) |
fc09ec34 | 126 | flags |= PLX9052_INTCSR_LI1ENAB; |
0756f8d7 | 127 | if (int1_active_high) |
fc09ec34 | 128 | flags |= PLX9052_INTCSR_LI1POL; |
0756f8d7 | 129 | if (int2_enable) |
fc09ec34 | 130 | flags |= PLX9052_INTCSR_LI2ENAB; |
0756f8d7 | 131 | if (int2_active_high) |
fc09ec34 | 132 | flags |= PLX9052_INTCSR_LI2POL; |
8cb9b9fb EP |
133 | |
134 | if (interrupt_enable) | |
fc09ec34 | 135 | flags |= PLX9052_INTCSR_PCIENAB; |
8cb9b9fb | 136 | |
fc09ec34 | 137 | outb(flags, io_base + PLX9052_INTCSR); |
8cb9b9fb EP |
138 | } |
139 | ||
3ba97b3c | 140 | enum pci9111_ISC0_sources { |
8cb9b9fb EP |
141 | irq_on_eoc, |
142 | irq_on_fifo_half_full | |
3ba97b3c | 143 | }; |
8cb9b9fb | 144 | |
52f8ac98 | 145 | enum pci9111_ISC1_sources { |
8cb9b9fb EP |
146 | irq_on_timer_tick, |
147 | irq_on_external_trigger | |
52f8ac98 | 148 | }; |
8cb9b9fb | 149 | |
da91b269 | 150 | static void pci9111_interrupt_source_set(struct comedi_device *dev, |
0a85b6f0 MT |
151 | enum pci9111_ISC0_sources irq_0_source, |
152 | enum pci9111_ISC1_sources irq_1_source) | |
8cb9b9fb EP |
153 | { |
154 | int flags; | |
155 | ||
2959bc21 | 156 | /* Read the current interrupt control bits */ |
8c7524e6 | 157 | flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
2959bc21 HS |
158 | /* Shift the bits so they are compatible with the write register */ |
159 | flags >>= 4; | |
160 | /* Mask off the ISCx bits */ | |
161 | flags &= 0xc0; | |
8cb9b9fb | 162 | |
2959bc21 | 163 | /* Now set the new ISCx bits */ |
8cb9b9fb | 164 | if (irq_0_source == irq_on_fifo_half_full) |
8c7524e6 | 165 | flags |= PCI9111_INT_CTRL_ISC0; |
8cb9b9fb EP |
166 | |
167 | if (irq_1_source == irq_on_external_trigger) | |
8c7524e6 | 168 | flags |= PCI9111_INT_CTRL_ISC1; |
8cb9b9fb | 169 | |
2959bc21 | 170 | outb(flags, dev->iobase + PCI9111_INT_CTRL_REG); |
8cb9b9fb EP |
171 | } |
172 | ||
6b228d8a HS |
173 | static void pci9111_fifo_reset(struct comedi_device *dev) |
174 | { | |
175 | unsigned long int_ctrl_reg = dev->iobase + PCI9111_INT_CTRL_REG; | |
176 | ||
177 | /* To reset the FIFO, set FFEN sequence as 0 -> 1 -> 0 */ | |
8c7524e6 HS |
178 | outb(0, int_ctrl_reg); |
179 | outb(PCI9111_INT_CTRL_FFEN, int_ctrl_reg); | |
180 | outb(0, int_ctrl_reg); | |
6b228d8a HS |
181 | } |
182 | ||
0a85b6f0 MT |
183 | static int pci9111_ai_cancel(struct comedi_device *dev, |
184 | struct comedi_subdevice *s) | |
8cb9b9fb | 185 | { |
98943079 HS |
186 | struct pci9111_private_data *dev_private = dev->private; |
187 | ||
52f8ac98 | 188 | /* Disable interrupts */ |
8cb9b9fb | 189 | plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true, |
0a85b6f0 | 190 | true, false); |
8cb9b9fb | 191 | |
3e18c528 HS |
192 | /* disable A/D triggers (software trigger mode) and auto scan off */ |
193 | outb(0, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); | |
8cb9b9fb | 194 | |
6b228d8a | 195 | pci9111_fifo_reset(dev); |
8cb9b9fb | 196 | |
8cb9b9fb EP |
197 | return 0; |
198 | } | |
199 | ||
8802cd84 HS |
200 | static int pci9111_ai_check_chanlist(struct comedi_device *dev, |
201 | struct comedi_subdevice *s, | |
202 | struct comedi_cmd *cmd) | |
203 | { | |
204 | unsigned int range0 = CR_RANGE(cmd->chanlist[0]); | |
205 | unsigned int aref0 = CR_AREF(cmd->chanlist[0]); | |
206 | int i; | |
207 | ||
208 | for (i = 1; i < cmd->chanlist_len; i++) { | |
209 | unsigned int chan = CR_CHAN(cmd->chanlist[i]); | |
210 | unsigned int range = CR_RANGE(cmd->chanlist[i]); | |
211 | unsigned int aref = CR_AREF(cmd->chanlist[i]); | |
212 | ||
213 | if (chan != i) { | |
214 | dev_dbg(dev->class_dev, | |
215 | "entries in chanlist must be consecutive channels,counting upwards from 0\n"); | |
216 | return -EINVAL; | |
217 | } | |
218 | ||
219 | if (range != range0) { | |
220 | dev_dbg(dev->class_dev, | |
221 | "entries in chanlist must all have the same gain\n"); | |
222 | return -EINVAL; | |
223 | } | |
224 | ||
225 | if (aref != aref0) { | |
226 | dev_dbg(dev->class_dev, | |
227 | "entries in chanlist must all have the same reference\n"); | |
228 | return -EINVAL; | |
229 | } | |
230 | } | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
97e01bb1 HS |
235 | static int pci9111_ai_do_cmd_test(struct comedi_device *dev, |
236 | struct comedi_subdevice *s, | |
237 | struct comedi_cmd *cmd) | |
8cb9b9fb | 238 | { |
c50a3982 | 239 | int err = 0; |
f1c51faa | 240 | unsigned int arg; |
8cb9b9fb | 241 | |
27020ffe | 242 | /* Step 1 : check if triggers are trivially valid */ |
8cb9b9fb | 243 | |
1a4888c1 IA |
244 | err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW); |
245 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, | |
97e01bb1 | 246 | TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); |
1a4888c1 | 247 | err |= comedi_check_trigger_src(&cmd->convert_src, |
97e01bb1 | 248 | TRIG_TIMER | TRIG_EXT); |
1a4888c1 IA |
249 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); |
250 | err |= comedi_check_trigger_src(&cmd->stop_src, | |
97e01bb1 | 251 | TRIG_COUNT | TRIG_NONE); |
8cb9b9fb | 252 | |
c50a3982 | 253 | if (err) |
8cb9b9fb EP |
254 | return 1; |
255 | ||
e990333d | 256 | /* Step 2a : make sure trigger sources are unique */ |
8cb9b9fb | 257 | |
1a4888c1 IA |
258 | err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); |
259 | err |= comedi_check_trigger_is_unique(cmd->convert_src); | |
260 | err |= comedi_check_trigger_is_unique(cmd->stop_src); | |
e990333d HS |
261 | |
262 | /* Step 2b : and mutually compatible */ | |
8cb9b9fb | 263 | |
0fb21b2c HS |
264 | if (cmd->scan_begin_src != TRIG_FOLLOW) { |
265 | if (cmd->scan_begin_src != cmd->convert_src) | |
266 | err |= -EINVAL; | |
267 | } | |
8cb9b9fb | 268 | |
c50a3982 | 269 | if (err) |
8cb9b9fb EP |
270 | return 2; |
271 | ||
430f87da | 272 | /* Step 3: check if arguments are trivially valid */ |
8cb9b9fb | 273 | |
1a4888c1 | 274 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
8cb9b9fb | 275 | |
1a4888c1 IA |
276 | if (cmd->convert_src == TRIG_TIMER) { |
277 | err |= comedi_check_trigger_arg_min(&cmd->convert_arg, | |
430f87da | 278 | PCI9111_AI_ACQUISITION_PERIOD_MIN_NS); |
1a4888c1 IA |
279 | } else { /* TRIG_EXT */ |
280 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); | |
281 | } | |
8cb9b9fb | 282 | |
1a4888c1 IA |
283 | if (cmd->scan_begin_src == TRIG_TIMER) { |
284 | err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, | |
430f87da | 285 | PCI9111_AI_ACQUISITION_PERIOD_MIN_NS); |
1a4888c1 IA |
286 | } else { /* TRIG_FOLLOW || TRIG_EXT */ |
287 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0); | |
288 | } | |
8cb9b9fb | 289 | |
1a4888c1 IA |
290 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
291 | cmd->chanlist_len); | |
8cb9b9fb | 292 | |
430f87da | 293 | if (cmd->stop_src == TRIG_COUNT) |
1a4888c1 | 294 | err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); |
430f87da | 295 | else /* TRIG_NONE */ |
1a4888c1 | 296 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
8cb9b9fb | 297 | |
c50a3982 | 298 | if (err) |
8cb9b9fb EP |
299 | return 3; |
300 | ||
f1c51faa | 301 | /* Step 4: fix up any arguments */ |
8cb9b9fb EP |
302 | |
303 | if (cmd->convert_src == TRIG_TIMER) { | |
f1c51faa | 304 | arg = cmd->convert_arg; |
0880acf8 | 305 | comedi_8254_cascade_ns_to_timer(dev->pacer, &arg, cmd->flags); |
1a4888c1 | 306 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg); |
8cb9b9fb | 307 | } |
8cb9b9fb | 308 | |
f1c51faa HS |
309 | /* |
310 | * There's only one timer on this card, so the scan_begin timer | |
311 | * must be a multiple of chanlist_len*convert_arg | |
312 | */ | |
8cb9b9fb | 313 | if (cmd->scan_begin_src == TRIG_TIMER) { |
f1c51faa | 314 | arg = cmd->chanlist_len * cmd->convert_arg; |
8cb9b9fb | 315 | |
f1c51faa HS |
316 | if (arg < cmd->scan_begin_arg) |
317 | arg *= (cmd->scan_begin_arg / arg); | |
318 | ||
1a4888c1 | 319 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg); |
8cb9b9fb EP |
320 | } |
321 | ||
c50a3982 | 322 | if (err) |
8cb9b9fb EP |
323 | return 4; |
324 | ||
8802cd84 HS |
325 | /* Step 5: check channel list if it exists */ |
326 | if (cmd->chanlist && cmd->chanlist_len > 0) | |
c50a3982 | 327 | err |= pci9111_ai_check_chanlist(dev, s, cmd); |
8cb9b9fb | 328 | |
c50a3982 | 329 | if (err) |
8cb9b9fb EP |
330 | return 5; |
331 | ||
332 | return 0; | |
8cb9b9fb EP |
333 | } |
334 | ||
0a85b6f0 | 335 | static int pci9111_ai_do_cmd(struct comedi_device *dev, |
d1d7b20d | 336 | struct comedi_subdevice *s) |
8cb9b9fb | 337 | { |
98943079 | 338 | struct pci9111_private_data *dev_private = dev->private; |
8eb18913 | 339 | struct comedi_cmd *cmd = &s->async->cmd; |
3e18c528 | 340 | unsigned int last_chan = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); |
68e41298 | 341 | unsigned int range0 = CR_RANGE(cmd->chanlist[0]); |
3e18c528 | 342 | unsigned int trig = 0; |
8cb9b9fb | 343 | |
52f8ac98 BP |
344 | /* Set channel scan limit */ |
345 | /* PCI9111 allows only scanning from channel 0 to channel n */ | |
346 | /* TODO: handle the case of an external multiplexer */ | |
8cb9b9fb | 347 | |
3e18c528 HS |
348 | if (cmd->chanlist_len > 1) |
349 | trig |= PCI9111_AI_TRIG_CTRL_ASCAN; | |
350 | ||
351 | outb(last_chan, dev->iobase + PCI9111_AI_CHANNEL_REG); | |
8cb9b9fb | 352 | |
68e41298 HS |
353 | /* Set gain - all channels use the same range */ |
354 | outb(PCI9111_AI_RANGE(range0), dev->iobase + PCI9111_AI_RANGE_STAT_REG); | |
8cb9b9fb | 355 | |
52f8ac98 | 356 | /* Set timer pacer */ |
8cb9b9fb | 357 | dev_private->scan_delay = 0; |
8eb18913 | 358 | if (cmd->convert_src == TRIG_TIMER) { |
3e18c528 | 359 | trig |= PCI9111_AI_TRIG_CTRL_TPST; |
0880acf8 HS |
360 | comedi_8254_update_divisors(dev->pacer); |
361 | comedi_8254_pacer_enable(dev->pacer, 1, 2, true); | |
6b228d8a | 362 | pci9111_fifo_reset(dev); |
8cb9b9fb | 363 | pci9111_interrupt_source_set(dev, irq_on_fifo_half_full, |
0a85b6f0 | 364 | irq_on_timer_tick); |
8cb9b9fb | 365 | plx9050_interrupt_control(dev_private->lcr_io_base, true, true, |
0a85b6f0 | 366 | false, true, true); |
8cb9b9fb | 367 | |
8eb18913 HS |
368 | if (cmd->scan_begin_src == TRIG_TIMER) { |
369 | dev_private->scan_delay = (cmd->scan_begin_arg / | |
370 | (cmd->convert_arg * cmd->chanlist_len)) - 1; | |
6c2fd308 | 371 | } |
bb73fc99 | 372 | } else { /* TRIG_EXT */ |
3e18c528 | 373 | trig |= PCI9111_AI_TRIG_CTRL_ETIS; |
6b228d8a | 374 | pci9111_fifo_reset(dev); |
8cb9b9fb | 375 | pci9111_interrupt_source_set(dev, irq_on_fifo_half_full, |
0a85b6f0 | 376 | irq_on_timer_tick); |
8cb9b9fb | 377 | plx9050_interrupt_control(dev_private->lcr_io_base, true, true, |
0a85b6f0 | 378 | false, true, true); |
8cb9b9fb | 379 | } |
3e18c528 | 380 | outb(trig, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
8cb9b9fb | 381 | |
8cb9b9fb | 382 | dev_private->chunk_counter = 0; |
cae5c9fb HS |
383 | dev_private->chunk_num_samples = cmd->chanlist_len * |
384 | (1 + dev_private->scan_delay); | |
8cb9b9fb | 385 | |
8cb9b9fb EP |
386 | return 0; |
387 | } | |
388 | ||
0a85b6f0 MT |
389 | static void pci9111_ai_munge(struct comedi_device *dev, |
390 | struct comedi_subdevice *s, void *data, | |
391 | unsigned int num_bytes, | |
392 | unsigned int start_chan_index) | |
8cb9b9fb | 393 | { |
b909ba8f | 394 | unsigned short *array = data; |
af031edf HS |
395 | unsigned int maxdata = s->maxdata; |
396 | unsigned int invert = (maxdata + 1) >> 1; | |
397 | unsigned int shift = (maxdata == 0xffff) ? 0 : 4; | |
287a143a | 398 | unsigned int num_samples = comedi_bytes_to_samples(s, num_bytes); |
af031edf HS |
399 | unsigned int i; |
400 | ||
401 | for (i = 0; i < num_samples; i++) | |
402 | array[i] = ((array[i] >> shift) & maxdata) ^ invert; | |
8cb9b9fb EP |
403 | } |
404 | ||
9a8805bb HS |
405 | static void pci9111_handle_fifo_half_full(struct comedi_device *dev, |
406 | struct comedi_subdevice *s) | |
407 | { | |
408 | struct pci9111_private_data *devpriv = dev->private; | |
409 | struct comedi_cmd *cmd = &s->async->cmd; | |
64a4e72e | 410 | unsigned short *buf = devpriv->ai_bounce_buffer; |
9a8805bb HS |
411 | unsigned int samples; |
412 | ||
b6bc224f | 413 | samples = comedi_nsamples_left(s, PCI9111_FIFO_HALF_SIZE); |
64a4e72e | 414 | insw(dev->iobase + PCI9111_AI_FIFO_REG, buf, samples); |
9a8805bb HS |
415 | |
416 | if (devpriv->scan_delay < 1) { | |
64a4e72e | 417 | comedi_buf_write_samples(s, buf, samples); |
9a8805bb HS |
418 | } else { |
419 | unsigned int pos = 0; | |
420 | unsigned int to_read; | |
421 | ||
422 | while (pos < samples) { | |
423 | if (devpriv->chunk_counter < cmd->chanlist_len) { | |
424 | to_read = cmd->chanlist_len - | |
425 | devpriv->chunk_counter; | |
426 | ||
427 | if (to_read > samples - pos) | |
428 | to_read = samples - pos; | |
429 | ||
64a4e72e | 430 | comedi_buf_write_samples(s, buf + pos, to_read); |
9a8805bb HS |
431 | } else { |
432 | to_read = devpriv->chunk_num_samples - | |
433 | devpriv->chunk_counter; | |
434 | ||
435 | if (to_read > samples - pos) | |
436 | to_read = samples - pos; | |
9a8805bb HS |
437 | } |
438 | ||
439 | pos += to_read; | |
440 | devpriv->chunk_counter += to_read; | |
441 | ||
442 | if (devpriv->chunk_counter >= | |
443 | devpriv->chunk_num_samples) | |
444 | devpriv->chunk_counter = 0; | |
445 | } | |
446 | } | |
9a8805bb HS |
447 | } |
448 | ||
70265d24 | 449 | static irqreturn_t pci9111_interrupt(int irq, void *p_device) |
8cb9b9fb | 450 | { |
71b5f4f1 | 451 | struct comedi_device *dev = p_device; |
98943079 | 452 | struct pci9111_private_data *dev_private = dev->private; |
d1d7b20d | 453 | struct comedi_subdevice *s = dev->read_subdev; |
d163679c | 454 | struct comedi_async *async; |
b978052b | 455 | struct comedi_cmd *cmd; |
96764373 | 456 | unsigned int status; |
8cb9b9fb EP |
457 | unsigned long irq_flags; |
458 | unsigned char intcsr; | |
459 | ||
460 | if (!dev->attached) { | |
52f8ac98 BP |
461 | /* Ignore interrupt before device fully attached. */ |
462 | /* Might not even have allocated subdevices yet! */ | |
8cb9b9fb EP |
463 | return IRQ_NONE; |
464 | } | |
465 | ||
d1d7b20d | 466 | async = s->async; |
b978052b | 467 | cmd = &async->cmd; |
8cb9b9fb | 468 | |
5f74ea14 | 469 | spin_lock_irqsave(&dev->spinlock, irq_flags); |
8cb9b9fb | 470 | |
52f8ac98 | 471 | /* Check if we are source of interrupt */ |
fc09ec34 HS |
472 | intcsr = inb(dev_private->lcr_io_base + PLX9052_INTCSR); |
473 | if (!(((intcsr & PLX9052_INTCSR_PCIENAB) != 0) && | |
474 | (((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) || | |
475 | ((intcsr & PCI9111_LI2_ACTIVE) == PCI9111_LI2_ACTIVE)))) { | |
52f8ac98 | 476 | /* Not the source of the interrupt. */ |
fc09ec34 | 477 | /* (N.B. not using PLX9052_INTCSR_SOFTINT) */ |
5f74ea14 | 478 | spin_unlock_irqrestore(&dev->spinlock, irq_flags); |
8cb9b9fb EP |
479 | return IRQ_NONE; |
480 | } | |
481 | ||
fc09ec34 | 482 | if ((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) { |
52f8ac98 | 483 | /* Interrupt comes from fifo_half-full signal */ |
8cb9b9fb | 484 | |
8c7524e6 | 485 | status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); |
96764373 HS |
486 | |
487 | /* '0' means FIFO is full, data may have been lost */ | |
8c7524e6 | 488 | if (!(status & PCI9111_AI_STAT_FF_FF)) { |
0a85b6f0 | 489 | spin_unlock_irqrestore(&dev->spinlock, irq_flags); |
64b99c4c | 490 | dev_dbg(dev->class_dev, "fifo overflow\n"); |
f123f287 | 491 | outb(0, dev->iobase + PCI9111_INT_CLR_REG); |
3e6cb74f | 492 | async->events |= COMEDI_CB_ERROR; |
aa59d88f | 493 | comedi_handle_events(dev, s); |
8cb9b9fb EP |
494 | |
495 | return IRQ_HANDLED; | |
496 | } | |
497 | ||
96764373 | 498 | /* '0' means FIFO is half-full */ |
9a8805bb HS |
499 | if (!(status & PCI9111_AI_STAT_FF_HF)) |
500 | pci9111_handle_fifo_half_full(dev, s); | |
8cb9b9fb EP |
501 | } |
502 | ||
b6bc224f | 503 | if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg) |
8cb9b9fb | 504 | async->events |= COMEDI_CB_EOA; |
8cb9b9fb | 505 | |
f123f287 | 506 | outb(0, dev->iobase + PCI9111_INT_CLR_REG); |
8cb9b9fb | 507 | |
5f74ea14 | 508 | spin_unlock_irqrestore(&dev->spinlock, irq_flags); |
8cb9b9fb | 509 | |
aa59d88f | 510 | comedi_handle_events(dev, s); |
8cb9b9fb EP |
511 | |
512 | return IRQ_HANDLED; | |
513 | } | |
514 | ||
5e1a65ae HS |
515 | static int pci9111_ai_eoc(struct comedi_device *dev, |
516 | struct comedi_subdevice *s, | |
517 | struct comedi_insn *insn, | |
518 | unsigned long context) | |
519 | { | |
520 | unsigned int status; | |
521 | ||
522 | status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); | |
523 | if (status & PCI9111_AI_STAT_FF_EF) | |
524 | return 0; | |
525 | return -EBUSY; | |
526 | } | |
527 | ||
da91b269 | 528 | static int pci9111_ai_insn_read(struct comedi_device *dev, |
d1d7b20d | 529 | struct comedi_subdevice *s, |
0a85b6f0 | 530 | struct comedi_insn *insn, unsigned int *data) |
8cb9b9fb | 531 | { |
ae479ee5 HS |
532 | unsigned int chan = CR_CHAN(insn->chanspec); |
533 | unsigned int range = CR_RANGE(insn->chanspec); | |
2f002cc9 HS |
534 | unsigned int maxdata = s->maxdata; |
535 | unsigned int invert = (maxdata + 1) >> 1; | |
536 | unsigned int shift = (maxdata == 0xffff) ? 0 : 4; | |
96764373 | 537 | unsigned int status; |
5e1a65ae | 538 | int ret; |
2f002cc9 | 539 | int i; |
8cb9b9fb | 540 | |
0f0bde92 | 541 | outb(chan, dev->iobase + PCI9111_AI_CHANNEL_REG); |
8cb9b9fb | 542 | |
8c7524e6 HS |
543 | status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); |
544 | if ((status & PCI9111_AI_RANGE_MASK) != range) { | |
68e41298 | 545 | outb(PCI9111_AI_RANGE(range), |
6c7d2c8b | 546 | dev->iobase + PCI9111_AI_RANGE_STAT_REG); |
c514bab7 | 547 | } |
8cb9b9fb | 548 | |
6b228d8a | 549 | pci9111_fifo_reset(dev); |
8cb9b9fb EP |
550 | |
551 | for (i = 0; i < insn->n; i++) { | |
3eb60d73 | 552 | /* Generate a software trigger */ |
8c7524e6 | 553 | outb(0, dev->iobase + PCI9111_SOFT_TRIG_REG); |
8cb9b9fb | 554 | |
5e1a65ae HS |
555 | ret = comedi_timeout(dev, s, insn, pci9111_ai_eoc, 0); |
556 | if (ret) { | |
5e1a65ae HS |
557 | pci9111_fifo_reset(dev); |
558 | return ret; | |
8cb9b9fb EP |
559 | } |
560 | ||
2f002cc9 HS |
561 | data[i] = inw(dev->iobase + PCI9111_AI_FIFO_REG); |
562 | data[i] = ((data[i] >> shift) & maxdata) ^ invert; | |
8cb9b9fb EP |
563 | } |
564 | ||
8cb9b9fb EP |
565 | return i; |
566 | } | |
567 | ||
2084fd19 HS |
568 | static int pci9111_ao_insn_write(struct comedi_device *dev, |
569 | struct comedi_subdevice *s, | |
570 | struct comedi_insn *insn, | |
571 | unsigned int *data) | |
8cb9b9fb | 572 | { |
80024255 HS |
573 | unsigned int chan = CR_CHAN(insn->chanspec); |
574 | unsigned int val = s->readback[chan]; | |
8cb9b9fb EP |
575 | int i; |
576 | ||
577 | for (i = 0; i < insn->n; i++) { | |
2084fd19 HS |
578 | val = data[i]; |
579 | outw(val, dev->iobase + PCI9111_AO_REG); | |
8cb9b9fb | 580 | } |
80024255 | 581 | s->readback[chan] = val; |
8cb9b9fb | 582 | |
b3450faf | 583 | return insn->n; |
8cb9b9fb EP |
584 | } |
585 | ||
da91b269 | 586 | static int pci9111_di_insn_bits(struct comedi_device *dev, |
d1d7b20d | 587 | struct comedi_subdevice *s, |
bfa6d3b8 HS |
588 | struct comedi_insn *insn, |
589 | unsigned int *data) | |
8cb9b9fb | 590 | { |
bfa6d3b8 | 591 | data[1] = inw(dev->iobase + PCI9111_DIO_REG); |
8cb9b9fb | 592 | |
a2714e3e | 593 | return insn->n; |
8cb9b9fb EP |
594 | } |
595 | ||
da91b269 | 596 | static int pci9111_do_insn_bits(struct comedi_device *dev, |
d1d7b20d | 597 | struct comedi_subdevice *s, |
83dcfee0 HS |
598 | struct comedi_insn *insn, |
599 | unsigned int *data) | |
8cb9b9fb | 600 | { |
97f4289a | 601 | if (comedi_dio_update_state(s, data)) |
83dcfee0 | 602 | outw(s->state, dev->iobase + PCI9111_DIO_REG); |
8cb9b9fb | 603 | |
83dcfee0 | 604 | data[1] = s->state; |
8cb9b9fb | 605 | |
a2714e3e | 606 | return insn->n; |
8cb9b9fb EP |
607 | } |
608 | ||
da91b269 | 609 | static int pci9111_reset(struct comedi_device *dev) |
8cb9b9fb | 610 | { |
98943079 HS |
611 | struct pci9111_private_data *dev_private = dev->private; |
612 | ||
52f8ac98 | 613 | /* Set trigger source to software */ |
8cb9b9fb | 614 | plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true, |
0a85b6f0 | 615 | true, false); |
8cb9b9fb | 616 | |
3e18c528 HS |
617 | /* disable A/D triggers (software trigger mode) and auto scan off */ |
618 | outb(0, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); | |
8cb9b9fb | 619 | |
8cb9b9fb EP |
620 | return 0; |
621 | } | |
622 | ||
a690b7e5 | 623 | static int pci9111_auto_attach(struct comedi_device *dev, |
6c7d2c8b | 624 | unsigned long context_unused) |
8cb9b9fb | 625 | { |
750af5e5 | 626 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
98943079 | 627 | struct pci9111_private_data *dev_private; |
d1d7b20d | 628 | struct comedi_subdevice *s; |
98943079 | 629 | int ret; |
3e5a0ba0 | 630 | |
0bdab509 | 631 | dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private)); |
c34fa261 HS |
632 | if (!dev_private) |
633 | return -ENOMEM; | |
98943079 | 634 | |
818f569f | 635 | ret = comedi_pci_enable(dev); |
3e5a0ba0 HS |
636 | if (ret) |
637 | return ret; | |
638 | dev_private->lcr_io_base = pci_resource_start(pcidev, 1); | |
639 | dev->iobase = pci_resource_start(pcidev, 2); | |
8cb9b9fb EP |
640 | |
641 | pci9111_reset(dev); | |
642 | ||
66d10158 | 643 | if (pcidev->irq) { |
48108fe3 | 644 | ret = request_irq(pcidev->irq, pci9111_interrupt, |
3e5a0ba0 | 645 | IRQF_SHARED, dev->board_name, dev); |
66d10158 HS |
646 | if (ret == 0) |
647 | dev->irq = pcidev->irq; | |
8cb9b9fb | 648 | } |
8cb9b9fb | 649 | |
fade5e5b IA |
650 | dev->pacer = comedi_8254_io_alloc(dev->iobase + PCI9111_8254_BASE_REG, |
651 | I8254_OSC_BASE_2MHZ, I8254_IO16, 0); | |
652 | if (IS_ERR(dev->pacer)) | |
653 | return PTR_ERR(dev->pacer); | |
0880acf8 | 654 | |
98943079 HS |
655 | ret = comedi_alloc_subdevices(dev, 4); |
656 | if (ret) | |
657 | return ret; | |
8cb9b9fb | 658 | |
573e31af | 659 | s = &dev->subdevices[0]; |
02baee8c | 660 | s->type = COMEDI_SUBD_AI; |
66d10158 | 661 | s->subdev_flags = SDF_READABLE | SDF_COMMON; |
02baee8c HS |
662 | s->n_chan = 16; |
663 | s->maxdata = 0xffff; | |
afa6ac4a | 664 | s->range_table = &pci9111_ai_range; |
02baee8c | 665 | s->insn_read = pci9111_ai_insn_read; |
66d10158 HS |
666 | if (dev->irq) { |
667 | dev->read_subdev = s; | |
668 | s->subdev_flags |= SDF_CMD_READ; | |
669 | s->len_chanlist = s->n_chan; | |
670 | s->do_cmdtest = pci9111_ai_do_cmd_test; | |
671 | s->do_cmd = pci9111_ai_do_cmd; | |
672 | s->cancel = pci9111_ai_cancel; | |
673 | s->munge = pci9111_ai_munge; | |
674 | } | |
d1d7b20d | 675 | |
573e31af | 676 | s = &dev->subdevices[1]; |
05841b36 HS |
677 | s->type = COMEDI_SUBD_AO; |
678 | s->subdev_flags = SDF_WRITABLE | SDF_COMMON; | |
679 | s->n_chan = 1; | |
680 | s->maxdata = 0x0fff; | |
681 | s->len_chanlist = 1; | |
682 | s->range_table = &range_bipolar10; | |
683 | s->insn_write = pci9111_ao_insn_write; | |
80024255 HS |
684 | |
685 | ret = comedi_alloc_subdev_readback(s); | |
686 | if (ret) | |
687 | return ret; | |
d1d7b20d | 688 | |
573e31af | 689 | s = &dev->subdevices[2]; |
3acf3176 HS |
690 | s->type = COMEDI_SUBD_DI; |
691 | s->subdev_flags = SDF_READABLE; | |
692 | s->n_chan = 16; | |
693 | s->maxdata = 1; | |
694 | s->range_table = &range_digital; | |
695 | s->insn_bits = pci9111_di_insn_bits; | |
d1d7b20d | 696 | |
573e31af | 697 | s = &dev->subdevices[3]; |
3acf3176 | 698 | s->type = COMEDI_SUBD_DO; |
453fd2b3 | 699 | s->subdev_flags = SDF_WRITABLE; |
3acf3176 HS |
700 | s->n_chan = 16; |
701 | s->maxdata = 1; | |
702 | s->range_table = &range_digital; | |
703 | s->insn_bits = pci9111_do_insn_bits; | |
8cb9b9fb | 704 | |
8cb9b9fb EP |
705 | return 0; |
706 | } | |
707 | ||
484ecc95 | 708 | static void pci9111_detach(struct comedi_device *dev) |
8cb9b9fb | 709 | { |
893be483 HS |
710 | if (dev->iobase) |
711 | pci9111_reset(dev); | |
aac307f9 | 712 | comedi_pci_detach(dev); |
8cb9b9fb | 713 | } |
90f703d3 | 714 | |
75e6301b HS |
715 | static struct comedi_driver adl_pci9111_driver = { |
716 | .driver_name = "adl_pci9111", | |
e68a83fe | 717 | .module = THIS_MODULE, |
750af5e5 | 718 | .auto_attach = pci9111_auto_attach, |
e68a83fe HS |
719 | .detach = pci9111_detach, |
720 | }; | |
721 | ||
a690b7e5 | 722 | static int pci9111_pci_probe(struct pci_dev *dev, |
b8f4ac23 | 723 | const struct pci_device_id *id) |
e68a83fe | 724 | { |
b8f4ac23 HS |
725 | return comedi_pci_auto_config(dev, &adl_pci9111_driver, |
726 | id->driver_data); | |
e68a83fe HS |
727 | } |
728 | ||
41e043fc | 729 | static const struct pci_device_id pci9111_pci_table[] = { |
d76fdfcc | 730 | { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, 0x9111) }, |
e68a83fe HS |
731 | /* { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HG_DEVICE_ID) }, */ |
732 | { 0 } | |
733 | }; | |
734 | MODULE_DEVICE_TABLE(pci, pci9111_pci_table); | |
735 | ||
75e6301b HS |
736 | static struct pci_driver adl_pci9111_pci_driver = { |
737 | .name = "adl_pci9111", | |
e68a83fe | 738 | .id_table = pci9111_pci_table, |
75e6301b | 739 | .probe = pci9111_pci_probe, |
9901a4d7 | 740 | .remove = comedi_pci_auto_unconfig, |
e68a83fe | 741 | }; |
75e6301b | 742 | module_comedi_pci_driver(adl_pci9111_driver, adl_pci9111_pci_driver); |
e68a83fe | 743 | |
a5fc6f6d | 744 | MODULE_AUTHOR("Comedi https://www.comedi.org"); |
90f703d3 AT |
745 | MODULE_DESCRIPTION("Comedi low-level driver"); |
746 | MODULE_LICENSE("GPL"); |