[linux-block.git] / drivers / clocksource / timer-vt8500.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  arch/arm/mach-vt8500/timer.c
 *
 *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
 */

/*
 * This file is copied and modified from the original timer.c provided by
 * Alexey Charkov. Minor changes have been made for Device Tree Support.
 */

#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/delay.h>

#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define VT8500_TIMER_OFFSET	0x0100
#define VT8500_TIMER_HZ		3000000
#define TIMER_MATCH_VAL		0x0000
#define TIMER_COUNT_VAL		0x0010
#define TIMER_STATUS_VAL	0x0014
#define TIMER_IER_VAL		0x001c		/* interrupt enable */
#define TIMER_CTRL_VAL		0x0020
#define TIMER_AS_VAL		0x0024		/* access status */
#define TIMER_COUNT_R_ACTIVE	(1 << 5)	/* not ready for read */
#define TIMER_COUNT_W_ACTIVE	(1 << 4)	/* not ready for write */
#define TIMER_MATCH_W_ACTIVE	(1 << 0)	/* not ready for write */

#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)

#define MIN_OSCR_DELTA		16

static void __iomem *regbase;

static u64 vt8500_timer_read(struct clocksource *cs)
{
	int loops = msecs_to_loops(10);
	writel(3, regbase + TIMER_CTRL_VAL);
	while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
						&& --loops)
		cpu_relax();
	return readl(regbase + TIMER_COUNT_VAL);
}

static struct clocksource clocksource = {
	.name           = "vt8500_timer",
	.rating         = 200,
	.read           = vt8500_timer_read,
	.mask           = CLOCKSOURCE_MASK(32),
	.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
};

static int vt8500_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	int loops = msecs_to_loops(10);
	u64 alarm = clocksource.read(&clocksource) + cycles;
	while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
						&& --loops)
		cpu_relax();
	writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);

	if ((signed)(alarm - clocksource.read(&clocksource)) <= MIN_OSCR_DELTA)
		return -ETIME;

	writel(1, regbase + TIMER_IER_VAL);

	return 0;
}

static int vt8500_shutdown(struct clock_event_device *evt)
{
	writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL);
	writel(0, regbase + TIMER_IER_VAL);
	return 0;
}

static struct clock_event_device clockevent = {
	.name			= "vt8500_timer",
	.features		= CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 200,
	.set_next_event		= vt8500_timer_set_next_event,
	.set_state_shutdown	= vt8500_shutdown,
	.set_state_oneshot	= vt8500_shutdown,
};

static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	writel(0xf, regbase + TIMER_STATUS_VAL);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int __init vt8500_timer_init(struct device_node *np)
{
	int timer_irq, ret;

	regbase = of_iomap(np, 0);
	if (!regbase) {
		pr_err("%s: Missing iobase description in Device Tree\n",
								__func__);
		return -ENXIO;
	}

	timer_irq = irq_of_parse_and_map(np, 0);
	if (!timer_irq) {
		pr_err("%s: Missing irq description in Device Tree\n",
								__func__);
		return -EINVAL;
	}

	writel(1, regbase + TIMER_CTRL_VAL);
	writel(0xf, regbase + TIMER_STATUS_VAL);
	writel(~0, regbase + TIMER_MATCH_VAL);

	ret = clocksource_register_hz(&clocksource, VT8500_TIMER_HZ);
	if (ret) {
		pr_err("%s: clocksource_register failed for %s\n",
		       __func__, clocksource.name);
		return ret;
	}

	clockevent.cpumask = cpumask_of(0);

	ret = request_irq(timer_irq, vt8500_timer_interrupt,
			  IRQF_TIMER | IRQF_IRQPOLL, "vt8500_timer",
			  &clockevent);
	if (ret) {
		pr_err("%s: setup_irq failed for %s\n", __func__,
							clockevent.name);
		return ret;
	}

	clockevents_config_and_register(&clockevent, VT8500_TIMER_HZ,
					MIN_OSCR_DELTA * 2, 0xf0000000);

	return 0;
}

TIMER_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
21f47fbc	2	/*
83cc7690	3	* arch/arm/mach-vt8500/timer.c
21f47fbc	4	*
e9a91de7	5	* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
21f47fbc	6	* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
21f47fbc AC	7	*/
21f47fbc AC	8
e9a91de7 TP	9	/*
	10	* This file is copied and modified from the original timer.c provided by
	11	* Alexey Charkov. Minor changes have been made for Device Tree Support.
	12	*/
	13
21f47fbc AC	14	#include <linux/io.h>
	15	#include <linux/irq.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/clocksource.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/delay.h>
21f47fbc	20
e9a91de7 TP	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
21f47fbc AC	24
21f47fbc AC	25	#define VT8500_TIMER_OFFSET 0x0100
e9a91de7	26	#define VT8500_TIMER_HZ 3000000
21f47fbc AC	27	#define TIMER_MATCH_VAL 0x0000
	28	#define TIMER_COUNT_VAL 0x0010
	29	#define TIMER_STATUS_VAL 0x0014
	30	#define TIMER_IER_VAL 0x001c /* interrupt enable */
	31	#define TIMER_CTRL_VAL 0x0020
	32	#define TIMER_AS_VAL 0x0024 /* access status */
	33	#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */
	34	#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */
	35	#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */
21f47fbc AC	36
	37	#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
	38
f9eccf24 RV	39	#define MIN_OSCR_DELTA 16
f9eccf24 RV	40
21f47fbc AC	41	static void __iomem *regbase;
21f47fbc AC	42
a5a1d1c2	43	static u64 vt8500_timer_read(struct clocksource *cs)
21f47fbc AC	44	{
	45	int loops = msecs_to_loops(10);
	46	writel(3, regbase + TIMER_CTRL_VAL);
	47	while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
	48	&& --loops)
	49	cpu_relax();
	50	return readl(regbase + TIMER_COUNT_VAL);
	51	}
	52
e9a91de7	53	static struct clocksource clocksource = {
21f47fbc AC	54	.name = "vt8500_timer",
	55	.rating = 200,
	56	.read = vt8500_timer_read,
	57	.mask = CLOCKSOURCE_MASK(32),
	58	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	59	};
	60
	61	static int vt8500_timer_set_next_event(unsigned long cycles,
	62	struct clock_event_device *evt)
	63	{
	64	int loops = msecs_to_loops(10);
a5a1d1c2	65	u64 alarm = clocksource.read(&clocksource) + cycles;
21f47fbc AC	66	while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
	67	&& --loops)
	68	cpu_relax();
	69	writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
	70
f9eccf24	71	if ((signed)(alarm - clocksource.read(&clocksource)) <= MIN_OSCR_DELTA)
21f47fbc AC	72	return -ETIME;
	73
	74	writel(1, regbase + TIMER_IER_VAL);
	75
	76	return 0;
	77	}
	78
214bc755	79	static int vt8500_shutdown(struct clock_event_device *evt)
21f47fbc	80	{
214bc755 VK	81	writel(readl(regbase + TIMER_CTRL_VAL) \| 1, regbase + TIMER_CTRL_VAL);
	82	writel(0, regbase + TIMER_IER_VAL);
	83	return 0;
21f47fbc AC	84	}
21f47fbc AC	85
e9a91de7	86	static struct clock_event_device clockevent = {
214bc755 VK	87	.name = "vt8500_timer",
	88	.features = CLOCK_EVT_FEAT_ONESHOT,
	89	.rating = 200,
	90	.set_next_event = vt8500_timer_set_next_event,
	91	.set_state_shutdown = vt8500_shutdown,
	92	.set_state_oneshot = vt8500_shutdown,
21f47fbc AC	93	};
	94
	95	static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
	96	{
	97	struct clock_event_device *evt = dev_id;
	98	writel(0xf, regbase + TIMER_STATUS_VAL);
	99	evt->event_handler(evt);
	100
	101	return IRQ_HANDLED;
	102	}
	103
979d7f28	104	static int __init vt8500_timer_init(struct device_node *np)
21f47fbc	105	{
979d7f28	106	int timer_irq, ret;
e9a91de7	107
e9a91de7 TP	108	regbase = of_iomap(np, 0);
	109	if (!regbase) {
	110	pr_err("%s: Missing iobase description in Device Tree\n",
	111	__func__);
979d7f28	112	return -ENXIO;
e9a91de7	113	}
979d7f28	114
e9a91de7 TP	115	timer_irq = irq_of_parse_and_map(np, 0);
	116	if (!timer_irq) {
	117	pr_err("%s: Missing irq description in Device Tree\n",
	118	__func__);
979d7f28	119	return -EINVAL;
e9a91de7	120	}
21f47fbc AC	121
	122	writel(1, regbase + TIMER_CTRL_VAL);
	123	writel(0xf, regbase + TIMER_STATUS_VAL);
	124	writel(~0, regbase + TIMER_MATCH_VAL);
	125
979d7f28 DL	126	ret = clocksource_register_hz(&clocksource, VT8500_TIMER_HZ);
979d7f28 DL	127	if (ret) {
30a85eb6	128	pr_err("%s: clocksource_register failed for %s\n",
979d7f28 DL	129	__func__, clocksource.name);
	130	return ret;
	131	}
21f47fbc	132
21f47fbc AC	133	clockevent.cpumask = cpumask_of(0);
21f47fbc AC	134
cc2550b4	135	ret = request_irq(timer_irq, vt8500_timer_interrupt,
	136	IRQF_TIMER \| IRQF_IRQPOLL, "vt8500_timer",
	137	&clockevent);
979d7f28	138	if (ret) {
e9a91de7 TP	139	pr_err("%s: setup_irq failed for %s\n", __func__,
e9a91de7 TP	140	clockevent.name);
979d7f28 DL	141	return ret;
	142	}
	143
838a2ae8	144	clockevents_config_and_register(&clockevent, VT8500_TIMER_HZ,
f9eccf24	145	MIN_OSCR_DELTA * 2, 0xf0000000);
979d7f28 DL	146
979d7f28 DL	147	return 0;
21f47fbc AC	148	}
21f47fbc AC	149
17273395	150	TIMER_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init);