Commit | Line | Data |
---|---|---|
341e8cba | 1 | // SPDX-License-Identifier: GPL-2.0+ |
92105bb7 TL |
2 | /* |
3 | * linux/arch/arm/plat-omap/dmtimer.c | |
4 | * | |
5 | * OMAP Dual-Mode Timers | |
6 | * | |
dcf30fc0 | 7 | * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ |
97933d6c TKD |
8 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> |
9 | * Thara Gopinath <thara@ti.com> | |
10 | * | |
11 | * dmtimer adaptation to platform_driver. | |
12 | * | |
92105bb7 | 13 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
14 | * OMAP2 support by Juha Yrjola |
15 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 16 | * |
44169075 SS |
17 | * Copyright (C) 2009 Texas Instruments |
18 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
92105bb7 TL |
19 | */ |
20 | ||
b1538832 | 21 | #include <linux/clk.h> |
ea05d2ea | 22 | #include <linux/clk-provider.h> |
b34677b0 | 23 | #include <linux/cpu_pm.h> |
869dec15 | 24 | #include <linux/module.h> |
fced80c7 | 25 | #include <linux/io.h> |
74dd9ec6 | 26 | #include <linux/device.h> |
3392cdd3 | 27 | #include <linux/err.h> |
ffe07cea | 28 | #include <linux/pm_runtime.h> |
9725f445 JH |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
40fc3bb5 JH |
31 | #include <linux/platform_device.h> |
32 | #include <linux/platform_data/dmtimer-omap.h> | |
44169075 | 33 | |
5ca467c4 | 34 | #include <clocksource/timer-ti-dm.h> |
2c799cef | 35 | |
b7b4ff76 | 36 | static u32 omap_reserved_systimers; |
df28472a | 37 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 38 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 39 | |
8fc7fcb5 JH |
40 | enum { |
41 | REQUEST_ANY = 0, | |
42 | REQUEST_BY_ID, | |
43 | REQUEST_BY_CAP, | |
44 | REQUEST_BY_NODE, | |
45 | }; | |
46 | ||
3392cdd3 TKD |
47 | /** |
48 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
49 | * @timer: timer pointer over which read operation to perform | |
50 | * @reg: lowest byte holds the register offset | |
51 | * | |
52 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
53 | * pending bit must be checked. Otherwise a read of a non completed write | |
54 | * will produce an error. | |
0f0d0807 RW |
55 | */ |
56 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 57 | { |
ee17f114 TL |
58 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
59 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 60 | } |
92105bb7 | 61 | |
3392cdd3 TKD |
62 | /** |
63 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
64 | * @timer: timer pointer over which write operation is to perform | |
65 | * @reg: lowest byte holds the register offset | |
66 | * @value: data to write into the register | |
67 | * | |
68 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
69 | * pending bit must be checked. Otherwise a write on a register which has a | |
70 | * pending write will be lost. | |
0f0d0807 RW |
71 | */ |
72 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
73 | u32 value) | |
92105bb7 | 74 | { |
ee17f114 TL |
75 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
76 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
77 | } |
78 | ||
b481113a TKD |
79 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
80 | { | |
9517c577 TL |
81 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, |
82 | timer->context.ocp_cfg, 0); | |
83 | ||
b481113a TKD |
84 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
85 | timer->context.twer); | |
86 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
87 | timer->context.tcrr); | |
88 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
89 | timer->context.tldr); | |
90 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
91 | timer->context.tmar); | |
92 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
93 | timer->context.tsicr); | |
834cacfb | 94 | writel_relaxed(timer->context.tier, timer->irq_ena); |
b481113a TKD |
95 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, |
96 | timer->context.tclr); | |
97 | } | |
98 | ||
b34677b0 LV |
99 | static void omap_timer_save_context(struct omap_dm_timer *timer) |
100 | { | |
9517c577 TL |
101 | timer->context.ocp_cfg = |
102 | __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
103 | ||
b34677b0 LV |
104 | timer->context.tclr = |
105 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
106 | timer->context.twer = | |
107 | omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG); | |
108 | timer->context.tldr = | |
109 | omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG); | |
110 | timer->context.tmar = | |
111 | omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG); | |
112 | timer->context.tier = readl_relaxed(timer->irq_ena); | |
113 | timer->context.tsicr = | |
114 | omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG); | |
115 | } | |
116 | ||
117 | static int omap_timer_context_notifier(struct notifier_block *nb, | |
118 | unsigned long cmd, void *v) | |
119 | { | |
120 | struct omap_dm_timer *timer; | |
121 | ||
122 | timer = container_of(nb, struct omap_dm_timer, nb); | |
123 | ||
124 | switch (cmd) { | |
125 | case CPU_CLUSTER_PM_ENTER: | |
126 | if ((timer->capability & OMAP_TIMER_ALWON) || | |
127 | !atomic_read(&timer->enabled)) | |
128 | break; | |
129 | omap_timer_save_context(timer); | |
130 | break; | |
3d41fff3 TL |
131 | case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ |
132 | break; | |
b34677b0 LV |
133 | case CPU_CLUSTER_PM_EXIT: |
134 | if ((timer->capability & OMAP_TIMER_ALWON) || | |
135 | !atomic_read(&timer->enabled)) | |
136 | break; | |
137 | omap_timer_restore_context(timer); | |
138 | break; | |
139 | } | |
140 | ||
141 | return NOTIFY_OK; | |
142 | } | |
143 | ||
ae6672cb | 144 | static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
92105bb7 | 145 | { |
ae6672cb | 146 | u32 l, timeout = 100000; |
77900a2f | 147 | |
ae6672cb JH |
148 | if (timer->revision != 1) |
149 | return -EINVAL; | |
ee17f114 | 150 | |
ae6672cb JH |
151 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
152 | ||
153 | do { | |
154 | l = __omap_dm_timer_read(timer, | |
155 | OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); | |
156 | } while (!l && timeout--); | |
157 | ||
158 | if (!timeout) { | |
159 | dev_err(&timer->pdev->dev, "Timer failed to reset\n"); | |
160 | return -ETIMEDOUT; | |
77900a2f | 161 | } |
92105bb7 | 162 | |
ae6672cb JH |
163 | /* Configure timer for smart-idle mode */ |
164 | l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
165 | l |= 0x2 << 0x3; | |
166 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); | |
167 | ||
168 | timer->posted = 0; | |
169 | ||
170 | return 0; | |
77900a2f TT |
171 | } |
172 | ||
592ea6bd LM |
173 | static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
174 | { | |
175 | int ret; | |
ad6e4b6f | 176 | const char *parent_name; |
592ea6bd LM |
177 | struct clk *parent; |
178 | struct dmtimer_platform_data *pdata; | |
179 | ||
ad6e4b6f | 180 | if (unlikely(!timer) || IS_ERR(timer->fclk)) |
592ea6bd LM |
181 | return -EINVAL; |
182 | ||
ad6e4b6f LM |
183 | switch (source) { |
184 | case OMAP_TIMER_SRC_SYS_CLK: | |
185 | parent_name = "timer_sys_ck"; | |
186 | break; | |
187 | case OMAP_TIMER_SRC_32_KHZ: | |
188 | parent_name = "timer_32k_ck"; | |
189 | break; | |
190 | case OMAP_TIMER_SRC_EXT_CLK: | |
191 | parent_name = "timer_ext_ck"; | |
192 | break; | |
193 | default: | |
592ea6bd | 194 | return -EINVAL; |
ad6e4b6f LM |
195 | } |
196 | ||
197 | pdata = timer->pdev->dev.platform_data; | |
592ea6bd LM |
198 | |
199 | /* | |
200 | * FIXME: Used for OMAP1 devices only because they do not currently | |
201 | * use the clock framework to set the parent clock. To be removed | |
202 | * once OMAP1 migrated to using clock framework for dmtimers | |
203 | */ | |
204 | if (pdata && pdata->set_timer_src) | |
205 | return pdata->set_timer_src(timer->pdev, source); | |
206 | ||
592ea6bd LM |
207 | #if defined(CONFIG_COMMON_CLK) |
208 | /* Check if the clock has configurable parents */ | |
209 | if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) | |
210 | return 0; | |
211 | #endif | |
212 | ||
592ea6bd LM |
213 | parent = clk_get(&timer->pdev->dev, parent_name); |
214 | if (IS_ERR(parent)) { | |
215 | pr_err("%s: %s not found\n", __func__, parent_name); | |
216 | return -EINVAL; | |
217 | } | |
218 | ||
219 | ret = clk_set_parent(timer->fclk, parent); | |
220 | if (ret < 0) | |
221 | pr_err("%s: failed to set %s as parent\n", __func__, | |
222 | parent_name); | |
223 | ||
224 | clk_put(parent); | |
225 | ||
226 | return ret; | |
227 | } | |
228 | ||
229 | static void omap_dm_timer_enable(struct omap_dm_timer *timer) | |
230 | { | |
592ea6bd | 231 | pm_runtime_get_sync(&timer->pdev->dev); |
592ea6bd LM |
232 | } |
233 | ||
234 | static void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
235 | { | |
236 | pm_runtime_put_sync(&timer->pdev->dev); | |
237 | } | |
238 | ||
b0cadb3c | 239 | static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 240 | { |
ae6672cb JH |
241 | int rc; |
242 | ||
bca45808 JH |
243 | /* |
244 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
245 | * do not call clk_get() for these devices. | |
246 | */ | |
247 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
248 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
86287958 | 249 | if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { |
bca45808 JH |
250 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); |
251 | return -EINVAL; | |
252 | } | |
3392cdd3 TKD |
253 | } |
254 | ||
7b44cf2c JH |
255 | omap_dm_timer_enable(timer); |
256 | ||
ae6672cb JH |
257 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
258 | rc = omap_dm_timer_reset(timer); | |
259 | if (rc) { | |
260 | omap_dm_timer_disable(timer); | |
261 | return rc; | |
262 | } | |
263 | } | |
3392cdd3 | 264 | |
7b44cf2c JH |
265 | __omap_dm_timer_enable_posted(timer); |
266 | omap_dm_timer_disable(timer); | |
3392cdd3 | 267 | |
264418e2 | 268 | return 0; |
77900a2f TT |
269 | } |
270 | ||
b7b4ff76 JH |
271 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
272 | { | |
273 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
274 | } | |
275 | ||
276 | int omap_dm_timer_reserve_systimer(int id) | |
277 | { | |
278 | if (omap_dm_timer_reserved_systimer(id)) | |
279 | return -ENODEV; | |
280 | ||
281 | omap_reserved_systimers |= (1 << (id - 1)); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
8fc7fcb5 | 286 | static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) |
77900a2f | 287 | { |
3392cdd3 | 288 | struct omap_dm_timer *timer = NULL, *t; |
8fc7fcb5 | 289 | struct device_node *np = NULL; |
77900a2f | 290 | unsigned long flags; |
8fc7fcb5 JH |
291 | u32 cap = 0; |
292 | int id = 0; | |
293 | ||
294 | switch (req_type) { | |
295 | case REQUEST_BY_ID: | |
296 | id = *(int *)data; | |
297 | break; | |
298 | case REQUEST_BY_CAP: | |
299 | cap = *(u32 *)data; | |
300 | break; | |
301 | case REQUEST_BY_NODE: | |
302 | np = (struct device_node *)data; | |
303 | break; | |
304 | default: | |
305 | /* REQUEST_ANY */ | |
306 | break; | |
307 | } | |
77900a2f TT |
308 | |
309 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
310 | list_for_each_entry(t, &omap_timer_list, node) { |
311 | if (t->reserved) | |
77900a2f TT |
312 | continue; |
313 | ||
8fc7fcb5 JH |
314 | switch (req_type) { |
315 | case REQUEST_BY_ID: | |
316 | if (id == t->pdev->id) { | |
317 | timer = t; | |
318 | timer->reserved = 1; | |
319 | goto found; | |
320 | } | |
321 | break; | |
322 | case REQUEST_BY_CAP: | |
323 | if (cap == (t->capability & cap)) { | |
324 | /* | |
325 | * If timer is not NULL, we have already found | |
28fd7e99 ME |
326 | * one timer. But it was not an exact match |
327 | * because it had more capabilities than what | |
8fc7fcb5 JH |
328 | * was required. Therefore, unreserve the last |
329 | * timer found and see if this one is a better | |
330 | * match. | |
331 | */ | |
332 | if (timer) | |
333 | timer->reserved = 0; | |
334 | timer = t; | |
335 | timer->reserved = 1; | |
336 | ||
337 | /* Exit loop early if we find an exact match */ | |
338 | if (t->capability == cap) | |
339 | goto found; | |
340 | } | |
341 | break; | |
342 | case REQUEST_BY_NODE: | |
343 | if (np == t->pdev->dev.of_node) { | |
344 | timer = t; | |
345 | timer->reserved = 1; | |
346 | goto found; | |
347 | } | |
348 | break; | |
349 | default: | |
350 | /* REQUEST_ANY */ | |
351 | timer = t; | |
352 | timer->reserved = 1; | |
353 | goto found; | |
354 | } | |
77900a2f | 355 | } |
8fc7fcb5 | 356 | found: |
c5491d1a | 357 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 | 358 | |
8fc7fcb5 JH |
359 | if (timer && omap_dm_timer_prepare(timer)) { |
360 | timer->reserved = 0; | |
361 | timer = NULL; | |
3392cdd3 | 362 | } |
77900a2f | 363 | |
3392cdd3 TKD |
364 | if (!timer) |
365 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 366 | |
77900a2f TT |
367 | return timer; |
368 | } | |
8fc7fcb5 | 369 | |
592ea6bd | 370 | static struct omap_dm_timer *omap_dm_timer_request(void) |
8fc7fcb5 JH |
371 | { |
372 | return _omap_dm_timer_request(REQUEST_ANY, NULL); | |
373 | } | |
77900a2f | 374 | |
592ea6bd | 375 | static struct omap_dm_timer *omap_dm_timer_request_specific(int id) |
92105bb7 | 376 | { |
9725f445 JH |
377 | /* Requesting timer by ID is not supported when device tree is used */ |
378 | if (of_have_populated_dt()) { | |
592ea6bd | 379 | pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", |
9725f445 JH |
380 | __func__); |
381 | return NULL; | |
382 | } | |
383 | ||
8fc7fcb5 | 384 | return _omap_dm_timer_request(REQUEST_BY_ID, &id); |
92105bb7 TL |
385 | } |
386 | ||
373fe0bd JH |
387 | /** |
388 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
389 | * @cap: Bit mask of capabilities to match | |
390 | * | |
391 | * Find a timer based upon capabilities bit mask. Callers of this function | |
392 | * should use the definitions found in the plat/dmtimer.h file under the | |
393 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
394 | * timer handle on success and a NULL pointer on failure. | |
395 | */ | |
396 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
397 | { | |
8fc7fcb5 JH |
398 | return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); |
399 | } | |
373fe0bd | 400 | |
8fc7fcb5 JH |
401 | /** |
402 | * omap_dm_timer_request_by_node - Request a timer by device-tree node | |
403 | * @np: Pointer to device-tree timer node | |
404 | * | |
405 | * Request a timer based upon a device node pointer. Returns pointer to | |
406 | * timer handle on success and a NULL pointer on failure. | |
407 | */ | |
592ea6bd | 408 | static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) |
8fc7fcb5 JH |
409 | { |
410 | if (!np) | |
373fe0bd JH |
411 | return NULL; |
412 | ||
8fc7fcb5 | 413 | return _omap_dm_timer_request(REQUEST_BY_NODE, np); |
373fe0bd | 414 | } |
373fe0bd | 415 | |
592ea6bd | 416 | static int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 417 | { |
ab4eb8b0 TKD |
418 | if (unlikely(!timer)) |
419 | return -EINVAL; | |
420 | ||
3392cdd3 | 421 | clk_put(timer->fclk); |
fa4bb626 | 422 | |
77900a2f TT |
423 | WARN_ON(!timer->reserved); |
424 | timer->reserved = 0; | |
ab4eb8b0 | 425 | return 0; |
77900a2f TT |
426 | } |
427 | ||
428 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) | |
429 | { | |
ab4eb8b0 TKD |
430 | if (timer) |
431 | return timer->irq; | |
432 | return -EINVAL; | |
77900a2f TT |
433 | } |
434 | ||
435 | #if defined(CONFIG_ARCH_OMAP1) | |
7136f8d8 | 436 | #include <mach/hardware.h> |
592ea6bd LM |
437 | |
438 | static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) | |
439 | { | |
440 | return NULL; | |
441 | } | |
442 | ||
a569c6ec TL |
443 | /** |
444 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
445 | * @inputmask: current value of idlect mask | |
446 | */ | |
447 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
448 | { | |
3392cdd3 TKD |
449 | int i = 0; |
450 | struct omap_dm_timer *timer = NULL; | |
451 | unsigned long flags; | |
a569c6ec TL |
452 | |
453 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
454 | if (!(inputmask & (1 << 1))) | |
455 | return inputmask; | |
456 | ||
457 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
458 | spin_lock_irqsave(&dm_timer_lock, flags); |
459 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
460 | u32 l; |
461 | ||
3392cdd3 | 462 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
463 | if (l & OMAP_TIMER_CTRL_ST) { |
464 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
465 | inputmask &= ~(1 << 1); |
466 | else | |
467 | inputmask &= ~(1 << 2); | |
468 | } | |
3392cdd3 | 469 | i++; |
77900a2f | 470 | } |
3392cdd3 | 471 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
472 | |
473 | return inputmask; | |
474 | } | |
475 | ||
140455fa | 476 | #else |
a569c6ec | 477 | |
592ea6bd | 478 | static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 479 | { |
86287958 | 480 | if (timer && !IS_ERR(timer->fclk)) |
ab4eb8b0 TKD |
481 | return timer->fclk; |
482 | return NULL; | |
77900a2f | 483 | } |
92105bb7 | 484 | |
77900a2f TT |
485 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
486 | { | |
487 | BUG(); | |
2121880e DB |
488 | |
489 | return 0; | |
92105bb7 TL |
490 | } |
491 | ||
77900a2f | 492 | #endif |
92105bb7 | 493 | |
ab4eb8b0 | 494 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 495 | { |
5e20931c | 496 | if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
ab4eb8b0 TKD |
497 | pr_err("%s: timer not available or enabled.\n", __func__); |
498 | return -EINVAL; | |
b481113a TKD |
499 | } |
500 | ||
77900a2f | 501 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 502 | return 0; |
92105bb7 TL |
503 | } |
504 | ||
592ea6bd | 505 | static int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
506 | { |
507 | u32 l; | |
92105bb7 | 508 | |
ab4eb8b0 TKD |
509 | if (unlikely(!timer)) |
510 | return -EINVAL; | |
511 | ||
b481113a TKD |
512 | omap_dm_timer_enable(timer); |
513 | ||
77900a2f TT |
514 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
515 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
516 | l |= OMAP_TIMER_CTRL_ST; | |
517 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
518 | } | |
b481113a | 519 | |
ab4eb8b0 | 520 | return 0; |
77900a2f | 521 | } |
92105bb7 | 522 | |
592ea6bd | 523 | static int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 524 | { |
caf64f2f | 525 | unsigned long rate = 0; |
92105bb7 | 526 | |
ab4eb8b0 TKD |
527 | if (unlikely(!timer)) |
528 | return -EINVAL; | |
529 | ||
6615975b | 530 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 531 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 532 | |
ee17f114 | 533 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 534 | |
dffc9dae | 535 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 536 | return 0; |
92105bb7 TL |
537 | } |
538 | ||
02e6d546 | 539 | static int omap_dm_timer_set_load(struct omap_dm_timer *timer, |
592ea6bd | 540 | unsigned int load) |
92105bb7 | 541 | { |
ab4eb8b0 TKD |
542 | if (unlikely(!timer)) |
543 | return -EINVAL; | |
544 | ||
b481113a | 545 | omap_dm_timer_enable(timer); |
77900a2f | 546 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 547 | |
b481113a | 548 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 549 | return 0; |
92105bb7 TL |
550 | } |
551 | ||
592ea6bd LM |
552 | static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
553 | unsigned int match) | |
92105bb7 TL |
554 | { |
555 | u32 l; | |
556 | ||
ab4eb8b0 TKD |
557 | if (unlikely(!timer)) |
558 | return -EINVAL; | |
559 | ||
b481113a | 560 | omap_dm_timer_enable(timer); |
92105bb7 | 561 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 562 | if (enable) |
77900a2f TT |
563 | l |= OMAP_TIMER_CTRL_CE; |
564 | else | |
565 | l &= ~OMAP_TIMER_CTRL_CE; | |
77900a2f | 566 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
991ad16a | 567 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a | 568 | |
b481113a | 569 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 570 | return 0; |
92105bb7 TL |
571 | } |
572 | ||
592ea6bd | 573 | static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
02e6d546 | 574 | int toggle, int trigger, int autoreload) |
92105bb7 TL |
575 | { |
576 | u32 l; | |
577 | ||
ab4eb8b0 TKD |
578 | if (unlikely(!timer)) |
579 | return -EINVAL; | |
580 | ||
b481113a | 581 | omap_dm_timer_enable(timer); |
92105bb7 | 582 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f | 583 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
02e6d546 | 584 | OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); |
77900a2f TT |
585 | if (def_on) |
586 | l |= OMAP_TIMER_CTRL_SCPWM; | |
587 | if (toggle) | |
588 | l |= OMAP_TIMER_CTRL_PT; | |
589 | l |= trigger << 10; | |
02e6d546 LV |
590 | if (autoreload) |
591 | l |= OMAP_TIMER_CTRL_AR; | |
92105bb7 | 592 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a | 593 | |
b481113a | 594 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 595 | return 0; |
92105bb7 TL |
596 | } |
597 | ||
92fd8686 LV |
598 | static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer) |
599 | { | |
600 | u32 l; | |
601 | ||
602 | if (unlikely(!timer)) | |
603 | return -EINVAL; | |
604 | ||
605 | omap_dm_timer_enable(timer); | |
606 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
607 | omap_dm_timer_disable(timer); | |
608 | ||
609 | return l; | |
610 | } | |
611 | ||
592ea6bd LM |
612 | static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, |
613 | int prescaler) | |
92105bb7 TL |
614 | { |
615 | u32 l; | |
616 | ||
58a54f03 | 617 | if (unlikely(!timer) || prescaler < -1 || prescaler > 7) |
ab4eb8b0 TKD |
618 | return -EINVAL; |
619 | ||
b481113a | 620 | omap_dm_timer_enable(timer); |
92105bb7 | 621 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f | 622 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
58a54f03 | 623 | if (prescaler >= 0) { |
77900a2f TT |
624 | l |= OMAP_TIMER_CTRL_PRE; |
625 | l |= prescaler << 2; | |
626 | } | |
92105bb7 | 627 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a | 628 | |
b481113a | 629 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 630 | return 0; |
92105bb7 TL |
631 | } |
632 | ||
592ea6bd LM |
633 | static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
634 | unsigned int value) | |
92105bb7 | 635 | { |
ab4eb8b0 TKD |
636 | if (unlikely(!timer)) |
637 | return -EINVAL; | |
638 | ||
b481113a | 639 | omap_dm_timer_enable(timer); |
ee17f114 | 640 | __omap_dm_timer_int_enable(timer, value); |
b481113a | 641 | |
b481113a | 642 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 643 | return 0; |
92105bb7 TL |
644 | } |
645 | ||
4249d96c JH |
646 | /** |
647 | * omap_dm_timer_set_int_disable - disable timer interrupts | |
648 | * @timer: pointer to timer handle | |
649 | * @mask: bit mask of interrupts to be disabled | |
650 | * | |
651 | * Disables the specified timer interrupts for a timer. | |
652 | */ | |
592ea6bd | 653 | static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) |
4249d96c JH |
654 | { |
655 | u32 l = mask; | |
656 | ||
657 | if (unlikely(!timer)) | |
658 | return -EINVAL; | |
659 | ||
660 | omap_dm_timer_enable(timer); | |
661 | ||
662 | if (timer->revision == 1) | |
834cacfb | 663 | l = readl_relaxed(timer->irq_ena) & ~mask; |
4249d96c | 664 | |
834cacfb | 665 | writel_relaxed(l, timer->irq_dis); |
4249d96c JH |
666 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; |
667 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); | |
668 | ||
4249d96c JH |
669 | omap_dm_timer_disable(timer); |
670 | return 0; | |
671 | } | |
4249d96c | 672 | |
592ea6bd | 673 | static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 674 | { |
fa4bb626 TT |
675 | unsigned int l; |
676 | ||
5e20931c | 677 | if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
ab4eb8b0 | 678 | pr_err("%s: timer not available or enabled.\n", __func__); |
b481113a TKD |
679 | return 0; |
680 | } | |
681 | ||
834cacfb | 682 | l = readl_relaxed(timer->irq_stat); |
fa4bb626 TT |
683 | |
684 | return l; | |
92105bb7 TL |
685 | } |
686 | ||
592ea6bd | 687 | static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 688 | { |
5e20931c | 689 | if (unlikely(!timer || !atomic_read(&timer->enabled))) |
ab4eb8b0 TKD |
690 | return -EINVAL; |
691 | ||
ee17f114 | 692 | __omap_dm_timer_write_status(timer, value); |
1eaff710 | 693 | |
ab4eb8b0 | 694 | return 0; |
92105bb7 TL |
695 | } |
696 | ||
592ea6bd | 697 | static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 698 | { |
5e20931c | 699 | if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
ab4eb8b0 | 700 | pr_err("%s: timer not iavailable or enabled.\n", __func__); |
b481113a TKD |
701 | return 0; |
702 | } | |
703 | ||
ee17f114 | 704 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 TL |
705 | } |
706 | ||
592ea6bd | 707 | static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 708 | { |
5e20931c | 709 | if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
ab4eb8b0 TKD |
710 | pr_err("%s: timer not available or enabled.\n", __func__); |
711 | return -EINVAL; | |
b481113a TKD |
712 | } |
713 | ||
fa4bb626 | 714 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
715 | |
716 | /* Save the context */ | |
717 | timer->context.tcrr = value; | |
ab4eb8b0 | 718 | return 0; |
83379c81 TT |
719 | } |
720 | ||
77900a2f | 721 | int omap_dm_timers_active(void) |
92105bb7 | 722 | { |
3392cdd3 | 723 | struct omap_dm_timer *timer; |
12583a70 | 724 | |
3392cdd3 | 725 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 726 | if (!timer->reserved) |
12583a70 TT |
727 | continue; |
728 | ||
77900a2f | 729 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 730 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 731 | return 1; |
fa4bb626 | 732 | } |
77900a2f TT |
733 | } |
734 | return 0; | |
735 | } | |
92105bb7 | 736 | |
5e20931c TL |
737 | static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) |
738 | { | |
739 | struct omap_dm_timer *timer = dev_get_drvdata(dev); | |
740 | ||
741 | atomic_set(&timer->enabled, 0); | |
742 | ||
b34677b0 LV |
743 | if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base) |
744 | return 0; | |
745 | ||
746 | omap_timer_save_context(timer); | |
747 | ||
5e20931c TL |
748 | return 0; |
749 | } | |
750 | ||
751 | static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) | |
752 | { | |
753 | struct omap_dm_timer *timer = dev_get_drvdata(dev); | |
754 | ||
b34677b0 LV |
755 | if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) |
756 | omap_timer_restore_context(timer); | |
757 | ||
5e20931c TL |
758 | atomic_set(&timer->enabled, 1); |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
763 | static const struct dev_pm_ops omap_dm_timer_pm_ops = { | |
764 | SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend, | |
765 | omap_dm_timer_runtime_resume, NULL) | |
766 | }; | |
767 | ||
d1c6ccfe JH |
768 | static const struct of_device_id omap_timer_match[]; |
769 | ||
df28472a TKD |
770 | /** |
771 | * omap_dm_timer_probe - probe function called for every registered device | |
772 | * @pdev: pointer to current timer platform device | |
773 | * | |
774 | * Called by driver framework at the end of device registration for all | |
775 | * timer devices. | |
776 | */ | |
351a102d | 777 | static int omap_dm_timer_probe(struct platform_device *pdev) |
df28472a | 778 | { |
df28472a TKD |
779 | unsigned long flags; |
780 | struct omap_dm_timer *timer; | |
74dd9ec6 | 781 | struct device *dev = &pdev->dev; |
d1c6ccfe | 782 | const struct dmtimer_platform_data *pdata; |
a76fc9dd | 783 | int ret; |
d1c6ccfe | 784 | |
1a3acad2 LM |
785 | pdata = of_device_get_match_data(dev); |
786 | if (!pdata) | |
787 | pdata = dev_get_platdata(dev); | |
788 | else | |
789 | dev->platform_data = (void *)pdata; | |
df28472a | 790 | |
1a3acad2 | 791 | if (!pdata) { |
74dd9ec6 | 792 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
793 | return -ENODEV; |
794 | } | |
795 | ||
16e7ea53 | 796 | timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); |
d679950c | 797 | if (!timer) |
74dd9ec6 | 798 | return -ENOMEM; |
df28472a | 799 | |
4341067c TL |
800 | timer->irq = platform_get_irq(pdev, 0); |
801 | if (timer->irq < 0) | |
802 | return timer->irq; | |
803 | ||
86287958 | 804 | timer->fclk = ERR_PTR(-ENODEV); |
cdab83f9 | 805 | timer->io_base = devm_platform_ioremap_resource(pdev, 0); |
5857bd98 TR |
806 | if (IS_ERR(timer->io_base)) |
807 | return PTR_ERR(timer->io_base); | |
df28472a | 808 | |
5e20931c TL |
809 | platform_set_drvdata(pdev, timer); |
810 | ||
9725f445 JH |
811 | if (dev->of_node) { |
812 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
813 | timer->capability |= OMAP_TIMER_ALWON; | |
814 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
815 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
816 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
817 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
818 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
819 | timer->capability |= OMAP_TIMER_SECURE; | |
820 | } else { | |
821 | timer->id = pdev->id; | |
822 | timer->capability = pdata->timer_capability; | |
823 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
b34677b0 LV |
824 | } |
825 | ||
826 | if (!(timer->capability & OMAP_TIMER_ALWON)) { | |
827 | timer->nb.notifier_call = omap_timer_context_notifier; | |
828 | cpu_pm_register_notifier(&timer->nb); | |
9725f445 JH |
829 | } |
830 | ||
d1c6ccfe JH |
831 | if (pdata) |
832 | timer->errata = pdata->timer_errata; | |
833 | ||
df28472a | 834 | timer->pdev = pdev; |
df28472a | 835 | |
ba688783 | 836 | pm_runtime_enable(dev); |
ffe07cea | 837 | |
0dad9fae | 838 | if (!timer->reserved) { |
a76fc9dd SA |
839 | ret = pm_runtime_get_sync(dev); |
840 | if (ret < 0) { | |
841 | dev_err(dev, "%s: pm_runtime_get_sync failed!\n", | |
842 | __func__); | |
843 | goto err_get_sync; | |
844 | } | |
0dad9fae | 845 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 846 | pm_runtime_put(dev); |
0dad9fae TL |
847 | } |
848 | ||
df28472a TKD |
849 | /* add the timer element to the list */ |
850 | spin_lock_irqsave(&dm_timer_lock, flags); | |
851 | list_add_tail(&timer->node, &omap_timer_list); | |
852 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
853 | ||
74dd9ec6 | 854 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
855 | |
856 | return 0; | |
a76fc9dd SA |
857 | |
858 | err_get_sync: | |
859 | pm_runtime_put_noidle(dev); | |
860 | pm_runtime_disable(dev); | |
861 | return ret; | |
df28472a TKD |
862 | } |
863 | ||
864 | /** | |
865 | * omap_dm_timer_remove - cleanup a registered timer device | |
866 | * @pdev: pointer to current timer platform device | |
867 | * | |
868 | * Called by driver framework whenever a timer device is unregistered. | |
869 | * In addition to freeing platform resources it also deletes the timer | |
870 | * entry from the local list. | |
871 | */ | |
351a102d | 872 | static int omap_dm_timer_remove(struct platform_device *pdev) |
df28472a TKD |
873 | { |
874 | struct omap_dm_timer *timer; | |
875 | unsigned long flags; | |
876 | int ret = -EINVAL; | |
877 | ||
878 | spin_lock_irqsave(&dm_timer_lock, flags); | |
879 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
880 | if (!strcmp(dev_name(&timer->pdev->dev), |
881 | dev_name(&pdev->dev))) { | |
b34677b0 LV |
882 | if (!(timer->capability & OMAP_TIMER_ALWON)) |
883 | cpu_pm_unregister_notifier(&timer->nb); | |
df28472a | 884 | list_del(&timer->node); |
df28472a TKD |
885 | ret = 0; |
886 | break; | |
887 | } | |
888 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
889 | ||
51b7e572 SA |
890 | pm_runtime_disable(&pdev->dev); |
891 | ||
df28472a TKD |
892 | return ret; |
893 | } | |
894 | ||
cda03a9a | 895 | static const struct omap_dm_timer_ops dmtimer_ops = { |
76234f7c K |
896 | .request_by_node = omap_dm_timer_request_by_node, |
897 | .request_specific = omap_dm_timer_request_specific, | |
898 | .request = omap_dm_timer_request, | |
899 | .set_source = omap_dm_timer_set_source, | |
900 | .get_irq = omap_dm_timer_get_irq, | |
901 | .set_int_enable = omap_dm_timer_set_int_enable, | |
902 | .set_int_disable = omap_dm_timer_set_int_disable, | |
903 | .free = omap_dm_timer_free, | |
904 | .enable = omap_dm_timer_enable, | |
905 | .disable = omap_dm_timer_disable, | |
906 | .get_fclk = omap_dm_timer_get_fclk, | |
907 | .start = omap_dm_timer_start, | |
908 | .stop = omap_dm_timer_stop, | |
909 | .set_load = omap_dm_timer_set_load, | |
910 | .set_match = omap_dm_timer_set_match, | |
911 | .set_pwm = omap_dm_timer_set_pwm, | |
92fd8686 | 912 | .get_pwm_status = omap_dm_timer_get_pwm_status, |
76234f7c K |
913 | .set_prescaler = omap_dm_timer_set_prescaler, |
914 | .read_counter = omap_dm_timer_read_counter, | |
915 | .write_counter = omap_dm_timer_write_counter, | |
916 | .read_status = omap_dm_timer_read_status, | |
917 | .write_status = omap_dm_timer_write_status, | |
918 | }; | |
919 | ||
d1c6ccfe JH |
920 | static const struct dmtimer_platform_data omap3plus_pdata = { |
921 | .timer_errata = OMAP_TIMER_ERRATA_I103_I767, | |
76234f7c | 922 | .timer_ops = &dmtimer_ops, |
d1c6ccfe JH |
923 | }; |
924 | ||
9725f445 | 925 | static const struct of_device_id omap_timer_match[] = { |
d1c6ccfe JH |
926 | { |
927 | .compatible = "ti,omap2420-timer", | |
928 | }, | |
929 | { | |
930 | .compatible = "ti,omap3430-timer", | |
931 | .data = &omap3plus_pdata, | |
932 | }, | |
933 | { | |
934 | .compatible = "ti,omap4430-timer", | |
935 | .data = &omap3plus_pdata, | |
936 | }, | |
937 | { | |
938 | .compatible = "ti,omap5430-timer", | |
939 | .data = &omap3plus_pdata, | |
940 | }, | |
941 | { | |
942 | .compatible = "ti,am335x-timer", | |
943 | .data = &omap3plus_pdata, | |
944 | }, | |
945 | { | |
946 | .compatible = "ti,am335x-timer-1ms", | |
947 | .data = &omap3plus_pdata, | |
948 | }, | |
8c0cabd7 NA |
949 | { |
950 | .compatible = "ti,dm816-timer", | |
951 | .data = &omap3plus_pdata, | |
952 | }, | |
9725f445 JH |
953 | {}, |
954 | }; | |
955 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
956 | ||
df28472a TKD |
957 | static struct platform_driver omap_dm_timer_driver = { |
958 | .probe = omap_dm_timer_probe, | |
351a102d | 959 | .remove = omap_dm_timer_remove, |
df28472a TKD |
960 | .driver = { |
961 | .name = "omap_timer", | |
9725f445 | 962 | .of_match_table = of_match_ptr(omap_timer_match), |
5e20931c | 963 | .pm = &omap_dm_timer_pm_ops, |
df28472a TKD |
964 | }, |
965 | }; | |
966 | ||
e4e9f7ea | 967 | module_platform_driver(omap_dm_timer_driver); |
df28472a TKD |
968 | |
969 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
970 | MODULE_LICENSE("GPL"); | |
df28472a | 971 | MODULE_AUTHOR("Texas Instruments Inc"); |