Commit | Line | Data |
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341e8cba | 1 | // SPDX-License-Identifier: GPL-2.0+ |
92105bb7 TL |
2 | /* |
3 | * linux/arch/arm/plat-omap/dmtimer.c | |
4 | * | |
5 | * OMAP Dual-Mode Timers | |
6 | * | |
dcf30fc0 | 7 | * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ |
97933d6c TKD |
8 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> |
9 | * Thara Gopinath <thara@ti.com> | |
10 | * | |
11 | * dmtimer adaptation to platform_driver. | |
12 | * | |
92105bb7 | 13 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
14 | * OMAP2 support by Juha Yrjola |
15 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 16 | * |
44169075 SS |
17 | * Copyright (C) 2009 Texas Instruments |
18 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
92105bb7 TL |
19 | */ |
20 | ||
b1538832 | 21 | #include <linux/clk.h> |
ea05d2ea | 22 | #include <linux/clk-provider.h> |
b34677b0 | 23 | #include <linux/cpu_pm.h> |
869dec15 | 24 | #include <linux/module.h> |
fced80c7 | 25 | #include <linux/io.h> |
74dd9ec6 | 26 | #include <linux/device.h> |
3392cdd3 | 27 | #include <linux/err.h> |
ffe07cea | 28 | #include <linux/pm_runtime.h> |
9725f445 JH |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
40fc3bb5 JH |
31 | #include <linux/platform_device.h> |
32 | #include <linux/platform_data/dmtimer-omap.h> | |
44169075 | 33 | |
5ca467c4 | 34 | #include <clocksource/timer-ti-dm.h> |
2c799cef | 35 | |
b7b4ff76 | 36 | static u32 omap_reserved_systimers; |
df28472a | 37 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 38 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 39 | |
8fc7fcb5 JH |
40 | enum { |
41 | REQUEST_ANY = 0, | |
42 | REQUEST_BY_ID, | |
43 | REQUEST_BY_CAP, | |
44 | REQUEST_BY_NODE, | |
45 | }; | |
46 | ||
3392cdd3 TKD |
47 | /** |
48 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
49 | * @timer: timer pointer over which read operation to perform | |
50 | * @reg: lowest byte holds the register offset | |
51 | * | |
52 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
53 | * pending bit must be checked. Otherwise a read of a non completed write | |
54 | * will produce an error. | |
0f0d0807 RW |
55 | */ |
56 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 57 | { |
ee17f114 TL |
58 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
59 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 60 | } |
92105bb7 | 61 | |
3392cdd3 TKD |
62 | /** |
63 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
64 | * @timer: timer pointer over which write operation is to perform | |
65 | * @reg: lowest byte holds the register offset | |
66 | * @value: data to write into the register | |
67 | * | |
68 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
69 | * pending bit must be checked. Otherwise a write on a register which has a | |
70 | * pending write will be lost. | |
0f0d0807 RW |
71 | */ |
72 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
73 | u32 value) | |
92105bb7 | 74 | { |
ee17f114 TL |
75 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
76 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
77 | } |
78 | ||
b481113a TKD |
79 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
80 | { | |
b481113a TKD |
81 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
82 | timer->context.twer); | |
83 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
84 | timer->context.tcrr); | |
85 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
86 | timer->context.tldr); | |
87 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
88 | timer->context.tmar); | |
89 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
90 | timer->context.tsicr); | |
834cacfb | 91 | writel_relaxed(timer->context.tier, timer->irq_ena); |
b481113a TKD |
92 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, |
93 | timer->context.tclr); | |
94 | } | |
95 | ||
b34677b0 LV |
96 | static void omap_timer_save_context(struct omap_dm_timer *timer) |
97 | { | |
98 | timer->context.tclr = | |
99 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
100 | timer->context.twer = | |
101 | omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG); | |
102 | timer->context.tldr = | |
103 | omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG); | |
104 | timer->context.tmar = | |
105 | omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG); | |
106 | timer->context.tier = readl_relaxed(timer->irq_ena); | |
107 | timer->context.tsicr = | |
108 | omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG); | |
109 | } | |
110 | ||
111 | static int omap_timer_context_notifier(struct notifier_block *nb, | |
112 | unsigned long cmd, void *v) | |
113 | { | |
114 | struct omap_dm_timer *timer; | |
115 | ||
116 | timer = container_of(nb, struct omap_dm_timer, nb); | |
117 | ||
118 | switch (cmd) { | |
119 | case CPU_CLUSTER_PM_ENTER: | |
120 | if ((timer->capability & OMAP_TIMER_ALWON) || | |
121 | !atomic_read(&timer->enabled)) | |
122 | break; | |
123 | omap_timer_save_context(timer); | |
124 | break; | |
125 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
126 | case CPU_CLUSTER_PM_EXIT: | |
127 | if ((timer->capability & OMAP_TIMER_ALWON) || | |
128 | !atomic_read(&timer->enabled)) | |
129 | break; | |
130 | omap_timer_restore_context(timer); | |
131 | break; | |
132 | } | |
133 | ||
134 | return NOTIFY_OK; | |
135 | } | |
136 | ||
ae6672cb | 137 | static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
92105bb7 | 138 | { |
ae6672cb | 139 | u32 l, timeout = 100000; |
77900a2f | 140 | |
ae6672cb JH |
141 | if (timer->revision != 1) |
142 | return -EINVAL; | |
ee17f114 | 143 | |
ae6672cb JH |
144 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
145 | ||
146 | do { | |
147 | l = __omap_dm_timer_read(timer, | |
148 | OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); | |
149 | } while (!l && timeout--); | |
150 | ||
151 | if (!timeout) { | |
152 | dev_err(&timer->pdev->dev, "Timer failed to reset\n"); | |
153 | return -ETIMEDOUT; | |
77900a2f | 154 | } |
92105bb7 | 155 | |
ae6672cb JH |
156 | /* Configure timer for smart-idle mode */ |
157 | l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
158 | l |= 0x2 << 0x3; | |
159 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); | |
160 | ||
161 | timer->posted = 0; | |
162 | ||
163 | return 0; | |
77900a2f TT |
164 | } |
165 | ||
592ea6bd LM |
166 | static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
167 | { | |
168 | int ret; | |
ad6e4b6f | 169 | const char *parent_name; |
592ea6bd LM |
170 | struct clk *parent; |
171 | struct dmtimer_platform_data *pdata; | |
172 | ||
ad6e4b6f | 173 | if (unlikely(!timer) || IS_ERR(timer->fclk)) |
592ea6bd LM |
174 | return -EINVAL; |
175 | ||
ad6e4b6f LM |
176 | switch (source) { |
177 | case OMAP_TIMER_SRC_SYS_CLK: | |
178 | parent_name = "timer_sys_ck"; | |
179 | break; | |
180 | case OMAP_TIMER_SRC_32_KHZ: | |
181 | parent_name = "timer_32k_ck"; | |
182 | break; | |
183 | case OMAP_TIMER_SRC_EXT_CLK: | |
184 | parent_name = "timer_ext_ck"; | |
185 | break; | |
186 | default: | |
592ea6bd | 187 | return -EINVAL; |
ad6e4b6f LM |
188 | } |
189 | ||
190 | pdata = timer->pdev->dev.platform_data; | |
592ea6bd LM |
191 | |
192 | /* | |
193 | * FIXME: Used for OMAP1 devices only because they do not currently | |
194 | * use the clock framework to set the parent clock. To be removed | |
195 | * once OMAP1 migrated to using clock framework for dmtimers | |
196 | */ | |
197 | if (pdata && pdata->set_timer_src) | |
198 | return pdata->set_timer_src(timer->pdev, source); | |
199 | ||
592ea6bd LM |
200 | #if defined(CONFIG_COMMON_CLK) |
201 | /* Check if the clock has configurable parents */ | |
202 | if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) | |
203 | return 0; | |
204 | #endif | |
205 | ||
592ea6bd LM |
206 | parent = clk_get(&timer->pdev->dev, parent_name); |
207 | if (IS_ERR(parent)) { | |
208 | pr_err("%s: %s not found\n", __func__, parent_name); | |
209 | return -EINVAL; | |
210 | } | |
211 | ||
212 | ret = clk_set_parent(timer->fclk, parent); | |
213 | if (ret < 0) | |
214 | pr_err("%s: failed to set %s as parent\n", __func__, | |
215 | parent_name); | |
216 | ||
217 | clk_put(parent); | |
218 | ||
219 | return ret; | |
220 | } | |
221 | ||
222 | static void omap_dm_timer_enable(struct omap_dm_timer *timer) | |
223 | { | |
592ea6bd | 224 | pm_runtime_get_sync(&timer->pdev->dev); |
592ea6bd LM |
225 | } |
226 | ||
227 | static void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
228 | { | |
229 | pm_runtime_put_sync(&timer->pdev->dev); | |
230 | } | |
231 | ||
b0cadb3c | 232 | static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 233 | { |
ae6672cb JH |
234 | int rc; |
235 | ||
bca45808 JH |
236 | /* |
237 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
238 | * do not call clk_get() for these devices. | |
239 | */ | |
240 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
241 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
86287958 | 242 | if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { |
bca45808 JH |
243 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); |
244 | return -EINVAL; | |
245 | } | |
3392cdd3 TKD |
246 | } |
247 | ||
7b44cf2c JH |
248 | omap_dm_timer_enable(timer); |
249 | ||
ae6672cb JH |
250 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
251 | rc = omap_dm_timer_reset(timer); | |
252 | if (rc) { | |
253 | omap_dm_timer_disable(timer); | |
254 | return rc; | |
255 | } | |
256 | } | |
3392cdd3 | 257 | |
7b44cf2c JH |
258 | __omap_dm_timer_enable_posted(timer); |
259 | omap_dm_timer_disable(timer); | |
3392cdd3 | 260 | |
264418e2 | 261 | return 0; |
77900a2f TT |
262 | } |
263 | ||
b7b4ff76 JH |
264 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
265 | { | |
266 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
267 | } | |
268 | ||
269 | int omap_dm_timer_reserve_systimer(int id) | |
270 | { | |
271 | if (omap_dm_timer_reserved_systimer(id)) | |
272 | return -ENODEV; | |
273 | ||
274 | omap_reserved_systimers |= (1 << (id - 1)); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
8fc7fcb5 | 279 | static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) |
77900a2f | 280 | { |
3392cdd3 | 281 | struct omap_dm_timer *timer = NULL, *t; |
8fc7fcb5 | 282 | struct device_node *np = NULL; |
77900a2f | 283 | unsigned long flags; |
8fc7fcb5 JH |
284 | u32 cap = 0; |
285 | int id = 0; | |
286 | ||
287 | switch (req_type) { | |
288 | case REQUEST_BY_ID: | |
289 | id = *(int *)data; | |
290 | break; | |
291 | case REQUEST_BY_CAP: | |
292 | cap = *(u32 *)data; | |
293 | break; | |
294 | case REQUEST_BY_NODE: | |
295 | np = (struct device_node *)data; | |
296 | break; | |
297 | default: | |
298 | /* REQUEST_ANY */ | |
299 | break; | |
300 | } | |
77900a2f TT |
301 | |
302 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
303 | list_for_each_entry(t, &omap_timer_list, node) { |
304 | if (t->reserved) | |
77900a2f TT |
305 | continue; |
306 | ||
8fc7fcb5 JH |
307 | switch (req_type) { |
308 | case REQUEST_BY_ID: | |
309 | if (id == t->pdev->id) { | |
310 | timer = t; | |
311 | timer->reserved = 1; | |
312 | goto found; | |
313 | } | |
314 | break; | |
315 | case REQUEST_BY_CAP: | |
316 | if (cap == (t->capability & cap)) { | |
317 | /* | |
318 | * If timer is not NULL, we have already found | |
28fd7e99 ME |
319 | * one timer. But it was not an exact match |
320 | * because it had more capabilities than what | |
8fc7fcb5 JH |
321 | * was required. Therefore, unreserve the last |
322 | * timer found and see if this one is a better | |
323 | * match. | |
324 | */ | |
325 | if (timer) | |
326 | timer->reserved = 0; | |
327 | timer = t; | |
328 | timer->reserved = 1; | |
329 | ||
330 | /* Exit loop early if we find an exact match */ | |
331 | if (t->capability == cap) | |
332 | goto found; | |
333 | } | |
334 | break; | |
335 | case REQUEST_BY_NODE: | |
336 | if (np == t->pdev->dev.of_node) { | |
337 | timer = t; | |
338 | timer->reserved = 1; | |
339 | goto found; | |
340 | } | |
341 | break; | |
342 | default: | |
343 | /* REQUEST_ANY */ | |
344 | timer = t; | |
345 | timer->reserved = 1; | |
346 | goto found; | |
347 | } | |
77900a2f | 348 | } |
8fc7fcb5 | 349 | found: |
c5491d1a | 350 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 | 351 | |
8fc7fcb5 JH |
352 | if (timer && omap_dm_timer_prepare(timer)) { |
353 | timer->reserved = 0; | |
354 | timer = NULL; | |
3392cdd3 | 355 | } |
77900a2f | 356 | |
3392cdd3 TKD |
357 | if (!timer) |
358 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 359 | |
77900a2f TT |
360 | return timer; |
361 | } | |
8fc7fcb5 | 362 | |
592ea6bd | 363 | static struct omap_dm_timer *omap_dm_timer_request(void) |
8fc7fcb5 JH |
364 | { |
365 | return _omap_dm_timer_request(REQUEST_ANY, NULL); | |
366 | } | |
77900a2f | 367 | |
592ea6bd | 368 | static struct omap_dm_timer *omap_dm_timer_request_specific(int id) |
92105bb7 | 369 | { |
9725f445 JH |
370 | /* Requesting timer by ID is not supported when device tree is used */ |
371 | if (of_have_populated_dt()) { | |
592ea6bd | 372 | pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", |
9725f445 JH |
373 | __func__); |
374 | return NULL; | |
375 | } | |
376 | ||
8fc7fcb5 | 377 | return _omap_dm_timer_request(REQUEST_BY_ID, &id); |
92105bb7 TL |
378 | } |
379 | ||
373fe0bd JH |
380 | /** |
381 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
382 | * @cap: Bit mask of capabilities to match | |
383 | * | |
384 | * Find a timer based upon capabilities bit mask. Callers of this function | |
385 | * should use the definitions found in the plat/dmtimer.h file under the | |
386 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
387 | * timer handle on success and a NULL pointer on failure. | |
388 | */ | |
389 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
390 | { | |
8fc7fcb5 JH |
391 | return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); |
392 | } | |
373fe0bd | 393 | |
8fc7fcb5 JH |
394 | /** |
395 | * omap_dm_timer_request_by_node - Request a timer by device-tree node | |
396 | * @np: Pointer to device-tree timer node | |
397 | * | |
398 | * Request a timer based upon a device node pointer. Returns pointer to | |
399 | * timer handle on success and a NULL pointer on failure. | |
400 | */ | |
592ea6bd | 401 | static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) |
8fc7fcb5 JH |
402 | { |
403 | if (!np) | |
373fe0bd JH |
404 | return NULL; |
405 | ||
8fc7fcb5 | 406 | return _omap_dm_timer_request(REQUEST_BY_NODE, np); |
373fe0bd | 407 | } |
373fe0bd | 408 | |
592ea6bd | 409 | static int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 410 | { |
ab4eb8b0 TKD |
411 | if (unlikely(!timer)) |
412 | return -EINVAL; | |
413 | ||
3392cdd3 | 414 | clk_put(timer->fclk); |
fa4bb626 | 415 | |
77900a2f TT |
416 | WARN_ON(!timer->reserved); |
417 | timer->reserved = 0; | |
ab4eb8b0 | 418 | return 0; |
77900a2f TT |
419 | } |
420 | ||
421 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) | |
422 | { | |
ab4eb8b0 TKD |
423 | if (timer) |
424 | return timer->irq; | |
425 | return -EINVAL; | |
77900a2f TT |
426 | } |
427 | ||
428 | #if defined(CONFIG_ARCH_OMAP1) | |
7136f8d8 | 429 | #include <mach/hardware.h> |
592ea6bd LM |
430 | |
431 | static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) | |
432 | { | |
433 | return NULL; | |
434 | } | |
435 | ||
a569c6ec TL |
436 | /** |
437 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
438 | * @inputmask: current value of idlect mask | |
439 | */ | |
440 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
441 | { | |
3392cdd3 TKD |
442 | int i = 0; |
443 | struct omap_dm_timer *timer = NULL; | |
444 | unsigned long flags; | |
a569c6ec TL |
445 | |
446 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
447 | if (!(inputmask & (1 << 1))) | |
448 | return inputmask; | |
449 | ||
450 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
451 | spin_lock_irqsave(&dm_timer_lock, flags); |
452 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
453 | u32 l; |
454 | ||
3392cdd3 | 455 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
456 | if (l & OMAP_TIMER_CTRL_ST) { |
457 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
458 | inputmask &= ~(1 << 1); |
459 | else | |
460 | inputmask &= ~(1 << 2); | |
461 | } | |
3392cdd3 | 462 | i++; |
77900a2f | 463 | } |
3392cdd3 | 464 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
465 | |
466 | return inputmask; | |
467 | } | |
468 | ||
140455fa | 469 | #else |
a569c6ec | 470 | |
592ea6bd | 471 | static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 472 | { |
86287958 | 473 | if (timer && !IS_ERR(timer->fclk)) |
ab4eb8b0 TKD |
474 | return timer->fclk; |
475 | return NULL; | |
77900a2f | 476 | } |
92105bb7 | 477 | |
77900a2f TT |
478 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
479 | { | |
480 | BUG(); | |
2121880e DB |
481 | |
482 | return 0; | |
92105bb7 TL |
483 | } |
484 | ||
77900a2f | 485 | #endif |
92105bb7 | 486 | |
ab4eb8b0 | 487 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 488 | { |
5e20931c | 489 | if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
ab4eb8b0 TKD |
490 | pr_err("%s: timer not available or enabled.\n", __func__); |
491 | return -EINVAL; | |
b481113a TKD |
492 | } |
493 | ||
77900a2f | 494 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 495 | return 0; |
92105bb7 TL |
496 | } |
497 | ||
592ea6bd | 498 | static int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
499 | { |
500 | u32 l; | |
92105bb7 | 501 | |
ab4eb8b0 TKD |
502 | if (unlikely(!timer)) |
503 | return -EINVAL; | |
504 | ||
b481113a TKD |
505 | omap_dm_timer_enable(timer); |
506 | ||
77900a2f TT |
507 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
508 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
509 | l |= OMAP_TIMER_CTRL_ST; | |
510 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
511 | } | |
b481113a | 512 | |
ab4eb8b0 | 513 | return 0; |
77900a2f | 514 | } |
92105bb7 | 515 | |
592ea6bd | 516 | static int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 517 | { |
caf64f2f | 518 | unsigned long rate = 0; |
92105bb7 | 519 | |
ab4eb8b0 TKD |
520 | if (unlikely(!timer)) |
521 | return -EINVAL; | |
522 | ||
6615975b | 523 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 524 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 525 | |
ee17f114 | 526 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 527 | |
dffc9dae | 528 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 529 | return 0; |
92105bb7 TL |
530 | } |
531 | ||
02e6d546 | 532 | static int omap_dm_timer_set_load(struct omap_dm_timer *timer, |
592ea6bd | 533 | unsigned int load) |
92105bb7 | 534 | { |
ab4eb8b0 TKD |
535 | if (unlikely(!timer)) |
536 | return -EINVAL; | |
537 | ||
b481113a | 538 | omap_dm_timer_enable(timer); |
77900a2f | 539 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 540 | |
b481113a | 541 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 542 | return 0; |
92105bb7 TL |
543 | } |
544 | ||
592ea6bd LM |
545 | static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
546 | unsigned int match) | |
92105bb7 TL |
547 | { |
548 | u32 l; | |
549 | ||
ab4eb8b0 TKD |
550 | if (unlikely(!timer)) |
551 | return -EINVAL; | |
552 | ||
b481113a | 553 | omap_dm_timer_enable(timer); |
92105bb7 | 554 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 555 | if (enable) |
77900a2f TT |
556 | l |= OMAP_TIMER_CTRL_CE; |
557 | else | |
558 | l &= ~OMAP_TIMER_CTRL_CE; | |
77900a2f | 559 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
991ad16a | 560 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a | 561 | |
b481113a | 562 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 563 | return 0; |
92105bb7 TL |
564 | } |
565 | ||
592ea6bd | 566 | static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
02e6d546 | 567 | int toggle, int trigger, int autoreload) |
92105bb7 TL |
568 | { |
569 | u32 l; | |
570 | ||
ab4eb8b0 TKD |
571 | if (unlikely(!timer)) |
572 | return -EINVAL; | |
573 | ||
b481113a | 574 | omap_dm_timer_enable(timer); |
92105bb7 | 575 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f | 576 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
02e6d546 | 577 | OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); |
77900a2f TT |
578 | if (def_on) |
579 | l |= OMAP_TIMER_CTRL_SCPWM; | |
580 | if (toggle) | |
581 | l |= OMAP_TIMER_CTRL_PT; | |
582 | l |= trigger << 10; | |
02e6d546 LV |
583 | if (autoreload) |
584 | l |= OMAP_TIMER_CTRL_AR; | |
92105bb7 | 585 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a | 586 | |
b481113a | 587 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 588 | return 0; |
92105bb7 TL |
589 | } |
590 | ||
92fd8686 LV |
591 | static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer) |
592 | { | |
593 | u32 l; | |
594 | ||
595 | if (unlikely(!timer)) | |
596 | return -EINVAL; | |
597 | ||
598 | omap_dm_timer_enable(timer); | |
599 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
600 | omap_dm_timer_disable(timer); | |
601 | ||
602 | return l; | |
603 | } | |
604 | ||
592ea6bd LM |
605 | static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, |
606 | int prescaler) | |
92105bb7 TL |
607 | { |
608 | u32 l; | |
609 | ||
58a54f03 | 610 | if (unlikely(!timer) || prescaler < -1 || prescaler > 7) |
ab4eb8b0 TKD |
611 | return -EINVAL; |
612 | ||
b481113a | 613 | omap_dm_timer_enable(timer); |
92105bb7 | 614 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f | 615 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
58a54f03 | 616 | if (prescaler >= 0) { |
77900a2f TT |
617 | l |= OMAP_TIMER_CTRL_PRE; |
618 | l |= prescaler << 2; | |
619 | } | |
92105bb7 | 620 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a | 621 | |
b481113a | 622 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 623 | return 0; |
92105bb7 TL |
624 | } |
625 | ||
592ea6bd LM |
626 | static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
627 | unsigned int value) | |
92105bb7 | 628 | { |
ab4eb8b0 TKD |
629 | if (unlikely(!timer)) |
630 | return -EINVAL; | |
631 | ||
b481113a | 632 | omap_dm_timer_enable(timer); |
ee17f114 | 633 | __omap_dm_timer_int_enable(timer, value); |
b481113a | 634 | |
b481113a | 635 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 636 | return 0; |
92105bb7 TL |
637 | } |
638 | ||
4249d96c JH |
639 | /** |
640 | * omap_dm_timer_set_int_disable - disable timer interrupts | |
641 | * @timer: pointer to timer handle | |
642 | * @mask: bit mask of interrupts to be disabled | |
643 | * | |
644 | * Disables the specified timer interrupts for a timer. | |
645 | */ | |
592ea6bd | 646 | static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) |
4249d96c JH |
647 | { |
648 | u32 l = mask; | |
649 | ||
650 | if (unlikely(!timer)) | |
651 | return -EINVAL; | |
652 | ||
653 | omap_dm_timer_enable(timer); | |
654 | ||
655 | if (timer->revision == 1) | |
834cacfb | 656 | l = readl_relaxed(timer->irq_ena) & ~mask; |
4249d96c | 657 | |
834cacfb | 658 | writel_relaxed(l, timer->irq_dis); |
4249d96c JH |
659 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; |
660 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); | |
661 | ||
4249d96c JH |
662 | omap_dm_timer_disable(timer); |
663 | return 0; | |
664 | } | |
4249d96c | 665 | |
592ea6bd | 666 | static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 667 | { |
fa4bb626 TT |
668 | unsigned int l; |
669 | ||
5e20931c | 670 | if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
ab4eb8b0 | 671 | pr_err("%s: timer not available or enabled.\n", __func__); |
b481113a TKD |
672 | return 0; |
673 | } | |
674 | ||
834cacfb | 675 | l = readl_relaxed(timer->irq_stat); |
fa4bb626 TT |
676 | |
677 | return l; | |
92105bb7 TL |
678 | } |
679 | ||
592ea6bd | 680 | static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 681 | { |
5e20931c | 682 | if (unlikely(!timer || !atomic_read(&timer->enabled))) |
ab4eb8b0 TKD |
683 | return -EINVAL; |
684 | ||
ee17f114 | 685 | __omap_dm_timer_write_status(timer, value); |
1eaff710 | 686 | |
ab4eb8b0 | 687 | return 0; |
92105bb7 TL |
688 | } |
689 | ||
592ea6bd | 690 | static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 691 | { |
5e20931c | 692 | if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
ab4eb8b0 | 693 | pr_err("%s: timer not iavailable or enabled.\n", __func__); |
b481113a TKD |
694 | return 0; |
695 | } | |
696 | ||
ee17f114 | 697 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 TL |
698 | } |
699 | ||
592ea6bd | 700 | static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 701 | { |
5e20931c | 702 | if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
ab4eb8b0 TKD |
703 | pr_err("%s: timer not available or enabled.\n", __func__); |
704 | return -EINVAL; | |
b481113a TKD |
705 | } |
706 | ||
fa4bb626 | 707 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
708 | |
709 | /* Save the context */ | |
710 | timer->context.tcrr = value; | |
ab4eb8b0 | 711 | return 0; |
83379c81 TT |
712 | } |
713 | ||
77900a2f | 714 | int omap_dm_timers_active(void) |
92105bb7 | 715 | { |
3392cdd3 | 716 | struct omap_dm_timer *timer; |
12583a70 | 717 | |
3392cdd3 | 718 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 719 | if (!timer->reserved) |
12583a70 TT |
720 | continue; |
721 | ||
77900a2f | 722 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 723 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 724 | return 1; |
fa4bb626 | 725 | } |
77900a2f TT |
726 | } |
727 | return 0; | |
728 | } | |
92105bb7 | 729 | |
5e20931c TL |
730 | static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) |
731 | { | |
732 | struct omap_dm_timer *timer = dev_get_drvdata(dev); | |
733 | ||
734 | atomic_set(&timer->enabled, 0); | |
735 | ||
b34677b0 LV |
736 | if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base) |
737 | return 0; | |
738 | ||
739 | omap_timer_save_context(timer); | |
740 | ||
5e20931c TL |
741 | return 0; |
742 | } | |
743 | ||
744 | static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) | |
745 | { | |
746 | struct omap_dm_timer *timer = dev_get_drvdata(dev); | |
747 | ||
b34677b0 LV |
748 | if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) |
749 | omap_timer_restore_context(timer); | |
750 | ||
5e20931c TL |
751 | atomic_set(&timer->enabled, 1); |
752 | ||
753 | return 0; | |
754 | } | |
755 | ||
756 | static const struct dev_pm_ops omap_dm_timer_pm_ops = { | |
757 | SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend, | |
758 | omap_dm_timer_runtime_resume, NULL) | |
759 | }; | |
760 | ||
d1c6ccfe JH |
761 | static const struct of_device_id omap_timer_match[]; |
762 | ||
df28472a TKD |
763 | /** |
764 | * omap_dm_timer_probe - probe function called for every registered device | |
765 | * @pdev: pointer to current timer platform device | |
766 | * | |
767 | * Called by driver framework at the end of device registration for all | |
768 | * timer devices. | |
769 | */ | |
351a102d | 770 | static int omap_dm_timer_probe(struct platform_device *pdev) |
df28472a | 771 | { |
df28472a TKD |
772 | unsigned long flags; |
773 | struct omap_dm_timer *timer; | |
74dd9ec6 | 774 | struct device *dev = &pdev->dev; |
d1c6ccfe | 775 | const struct dmtimer_platform_data *pdata; |
a76fc9dd | 776 | int ret; |
d1c6ccfe | 777 | |
1a3acad2 LM |
778 | pdata = of_device_get_match_data(dev); |
779 | if (!pdata) | |
780 | pdata = dev_get_platdata(dev); | |
781 | else | |
782 | dev->platform_data = (void *)pdata; | |
df28472a | 783 | |
1a3acad2 | 784 | if (!pdata) { |
74dd9ec6 | 785 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
786 | return -ENODEV; |
787 | } | |
788 | ||
16e7ea53 | 789 | timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); |
d679950c | 790 | if (!timer) |
74dd9ec6 | 791 | return -ENOMEM; |
df28472a | 792 | |
4341067c TL |
793 | timer->irq = platform_get_irq(pdev, 0); |
794 | if (timer->irq < 0) | |
795 | return timer->irq; | |
796 | ||
86287958 | 797 | timer->fclk = ERR_PTR(-ENODEV); |
cdab83f9 | 798 | timer->io_base = devm_platform_ioremap_resource(pdev, 0); |
5857bd98 TR |
799 | if (IS_ERR(timer->io_base)) |
800 | return PTR_ERR(timer->io_base); | |
df28472a | 801 | |
5e20931c TL |
802 | platform_set_drvdata(pdev, timer); |
803 | ||
9725f445 JH |
804 | if (dev->of_node) { |
805 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
806 | timer->capability |= OMAP_TIMER_ALWON; | |
807 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
808 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
809 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
810 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
811 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
812 | timer->capability |= OMAP_TIMER_SECURE; | |
813 | } else { | |
814 | timer->id = pdev->id; | |
815 | timer->capability = pdata->timer_capability; | |
816 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
b34677b0 LV |
817 | } |
818 | ||
819 | if (!(timer->capability & OMAP_TIMER_ALWON)) { | |
820 | timer->nb.notifier_call = omap_timer_context_notifier; | |
821 | cpu_pm_register_notifier(&timer->nb); | |
9725f445 JH |
822 | } |
823 | ||
d1c6ccfe JH |
824 | if (pdata) |
825 | timer->errata = pdata->timer_errata; | |
826 | ||
df28472a | 827 | timer->pdev = pdev; |
df28472a | 828 | |
ba688783 | 829 | pm_runtime_enable(dev); |
ffe07cea | 830 | |
0dad9fae | 831 | if (!timer->reserved) { |
a76fc9dd SA |
832 | ret = pm_runtime_get_sync(dev); |
833 | if (ret < 0) { | |
834 | dev_err(dev, "%s: pm_runtime_get_sync failed!\n", | |
835 | __func__); | |
836 | goto err_get_sync; | |
837 | } | |
0dad9fae | 838 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 839 | pm_runtime_put(dev); |
0dad9fae TL |
840 | } |
841 | ||
df28472a TKD |
842 | /* add the timer element to the list */ |
843 | spin_lock_irqsave(&dm_timer_lock, flags); | |
844 | list_add_tail(&timer->node, &omap_timer_list); | |
845 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
846 | ||
74dd9ec6 | 847 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
848 | |
849 | return 0; | |
a76fc9dd SA |
850 | |
851 | err_get_sync: | |
852 | pm_runtime_put_noidle(dev); | |
853 | pm_runtime_disable(dev); | |
854 | return ret; | |
df28472a TKD |
855 | } |
856 | ||
857 | /** | |
858 | * omap_dm_timer_remove - cleanup a registered timer device | |
859 | * @pdev: pointer to current timer platform device | |
860 | * | |
861 | * Called by driver framework whenever a timer device is unregistered. | |
862 | * In addition to freeing platform resources it also deletes the timer | |
863 | * entry from the local list. | |
864 | */ | |
351a102d | 865 | static int omap_dm_timer_remove(struct platform_device *pdev) |
df28472a TKD |
866 | { |
867 | struct omap_dm_timer *timer; | |
868 | unsigned long flags; | |
869 | int ret = -EINVAL; | |
870 | ||
871 | spin_lock_irqsave(&dm_timer_lock, flags); | |
872 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
873 | if (!strcmp(dev_name(&timer->pdev->dev), |
874 | dev_name(&pdev->dev))) { | |
b34677b0 LV |
875 | if (!(timer->capability & OMAP_TIMER_ALWON)) |
876 | cpu_pm_unregister_notifier(&timer->nb); | |
df28472a | 877 | list_del(&timer->node); |
df28472a TKD |
878 | ret = 0; |
879 | break; | |
880 | } | |
881 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
882 | ||
51b7e572 SA |
883 | pm_runtime_disable(&pdev->dev); |
884 | ||
df28472a TKD |
885 | return ret; |
886 | } | |
887 | ||
cda03a9a | 888 | static const struct omap_dm_timer_ops dmtimer_ops = { |
76234f7c K |
889 | .request_by_node = omap_dm_timer_request_by_node, |
890 | .request_specific = omap_dm_timer_request_specific, | |
891 | .request = omap_dm_timer_request, | |
892 | .set_source = omap_dm_timer_set_source, | |
893 | .get_irq = omap_dm_timer_get_irq, | |
894 | .set_int_enable = omap_dm_timer_set_int_enable, | |
895 | .set_int_disable = omap_dm_timer_set_int_disable, | |
896 | .free = omap_dm_timer_free, | |
897 | .enable = omap_dm_timer_enable, | |
898 | .disable = omap_dm_timer_disable, | |
899 | .get_fclk = omap_dm_timer_get_fclk, | |
900 | .start = omap_dm_timer_start, | |
901 | .stop = omap_dm_timer_stop, | |
902 | .set_load = omap_dm_timer_set_load, | |
903 | .set_match = omap_dm_timer_set_match, | |
904 | .set_pwm = omap_dm_timer_set_pwm, | |
92fd8686 | 905 | .get_pwm_status = omap_dm_timer_get_pwm_status, |
76234f7c K |
906 | .set_prescaler = omap_dm_timer_set_prescaler, |
907 | .read_counter = omap_dm_timer_read_counter, | |
908 | .write_counter = omap_dm_timer_write_counter, | |
909 | .read_status = omap_dm_timer_read_status, | |
910 | .write_status = omap_dm_timer_write_status, | |
911 | }; | |
912 | ||
d1c6ccfe JH |
913 | static const struct dmtimer_platform_data omap3plus_pdata = { |
914 | .timer_errata = OMAP_TIMER_ERRATA_I103_I767, | |
76234f7c | 915 | .timer_ops = &dmtimer_ops, |
d1c6ccfe JH |
916 | }; |
917 | ||
9725f445 | 918 | static const struct of_device_id omap_timer_match[] = { |
d1c6ccfe JH |
919 | { |
920 | .compatible = "ti,omap2420-timer", | |
921 | }, | |
922 | { | |
923 | .compatible = "ti,omap3430-timer", | |
924 | .data = &omap3plus_pdata, | |
925 | }, | |
926 | { | |
927 | .compatible = "ti,omap4430-timer", | |
928 | .data = &omap3plus_pdata, | |
929 | }, | |
930 | { | |
931 | .compatible = "ti,omap5430-timer", | |
932 | .data = &omap3plus_pdata, | |
933 | }, | |
934 | { | |
935 | .compatible = "ti,am335x-timer", | |
936 | .data = &omap3plus_pdata, | |
937 | }, | |
938 | { | |
939 | .compatible = "ti,am335x-timer-1ms", | |
940 | .data = &omap3plus_pdata, | |
941 | }, | |
8c0cabd7 NA |
942 | { |
943 | .compatible = "ti,dm816-timer", | |
944 | .data = &omap3plus_pdata, | |
945 | }, | |
9725f445 JH |
946 | {}, |
947 | }; | |
948 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
949 | ||
df28472a TKD |
950 | static struct platform_driver omap_dm_timer_driver = { |
951 | .probe = omap_dm_timer_probe, | |
351a102d | 952 | .remove = omap_dm_timer_remove, |
df28472a TKD |
953 | .driver = { |
954 | .name = "omap_timer", | |
9725f445 | 955 | .of_match_table = of_match_ptr(omap_timer_match), |
5e20931c | 956 | .pm = &omap_dm_timer_pm_ops, |
df28472a TKD |
957 | }, |
958 | }; | |
959 | ||
e4e9f7ea | 960 | module_platform_driver(omap_dm_timer_driver); |
df28472a TKD |
961 | |
962 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
963 | MODULE_LICENSE("GPL"); | |
df28472a | 964 | MODULE_AUTHOR("Texas Instruments Inc"); |