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52762fbd TL |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | #include <linux/clk.h> | |
3 | #include <linux/clocksource.h> | |
4 | #include <linux/clockchips.h> | |
25de4ce5 | 5 | #include <linux/cpuhotplug.h> |
52762fbd TL |
6 | #include <linux/interrupt.h> |
7 | #include <linux/io.h> | |
8 | #include <linux/iopoll.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/of.h> | |
11 | #include <linux/of_address.h> | |
12 | #include <linux/of_irq.h> | |
13 | #include <linux/sched_clock.h> | |
14 | ||
15 | #include <linux/clk/clk-conf.h> | |
16 | ||
17 | #include <clocksource/timer-ti-dm.h> | |
18 | #include <dt-bindings/bus/ti-sysc.h> | |
19 | ||
20 | /* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */ | |
21 | #define DMTIMER_TYPE1_ENABLE ((1 << 9) | (SYSC_IDLE_SMART << 3) | \ | |
22 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE) | |
6cfcd556 | 23 | #define DMTIMER_TYPE1_DISABLE (SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE) |
52762fbd TL |
24 | #define DMTIMER_TYPE2_ENABLE (SYSC_IDLE_SMART_WKUP << 2) |
25 | #define DMTIMER_RESET_WAIT 100000 | |
26 | ||
27 | #define DMTIMER_INST_DONT_CARE ~0U | |
28 | ||
29 | static int counter_32k; | |
30 | static u32 clocksource; | |
31 | static u32 clockevent; | |
32 | ||
33 | /* | |
34 | * Subset of the timer registers we use. Note that the register offsets | |
35 | * depend on the timer revision detected. | |
36 | */ | |
37 | struct dmtimer_systimer { | |
38 | void __iomem *base; | |
39 | u8 sysc; | |
40 | u8 irq_stat; | |
41 | u8 irq_ena; | |
42 | u8 pend; | |
43 | u8 load; | |
44 | u8 counter; | |
45 | u8 ctrl; | |
46 | u8 wakeup; | |
47 | u8 ifctrl; | |
6cfcd556 TL |
48 | struct clk *fck; |
49 | struct clk *ick; | |
52762fbd TL |
50 | unsigned long rate; |
51 | }; | |
52 | ||
53 | struct dmtimer_clockevent { | |
54 | struct clock_event_device dev; | |
55 | struct dmtimer_systimer t; | |
56 | u32 period; | |
57 | }; | |
58 | ||
59 | struct dmtimer_clocksource { | |
60 | struct clocksource dev; | |
61 | struct dmtimer_systimer t; | |
62 | unsigned int loadval; | |
63 | }; | |
64 | ||
65 | /* Assumes v1 ip if bits [31:16] are zero */ | |
66 | static bool dmtimer_systimer_revision1(struct dmtimer_systimer *t) | |
67 | { | |
68 | u32 tidr = readl_relaxed(t->base); | |
69 | ||
70 | return !(tidr >> 16); | |
71 | } | |
72 | ||
16480515 TL |
73 | static void dmtimer_systimer_enable(struct dmtimer_systimer *t) |
74 | { | |
75 | u32 val; | |
76 | ||
77 | if (dmtimer_systimer_revision1(t)) | |
78 | val = DMTIMER_TYPE1_ENABLE; | |
79 | else | |
80 | val = DMTIMER_TYPE2_ENABLE; | |
81 | ||
82 | writel_relaxed(val, t->base + t->sysc); | |
83 | } | |
84 | ||
85 | static void dmtimer_systimer_disable(struct dmtimer_systimer *t) | |
86 | { | |
87 | if (!dmtimer_systimer_revision1(t)) | |
88 | return; | |
89 | ||
90 | writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc); | |
91 | } | |
92 | ||
52762fbd TL |
93 | static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t) |
94 | { | |
95 | void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET; | |
96 | int ret; | |
97 | u32 l; | |
98 | ||
16480515 | 99 | dmtimer_systimer_enable(t); |
52762fbd TL |
100 | writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl); |
101 | ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100, | |
102 | DMTIMER_RESET_WAIT); | |
103 | ||
104 | return ret; | |
105 | } | |
106 | ||
107 | /* Note we must use io_base instead of func_base for type2 OCP regs */ | |
108 | static int __init dmtimer_systimer_type2_reset(struct dmtimer_systimer *t) | |
109 | { | |
110 | void __iomem *sysc = t->base + t->sysc; | |
111 | u32 l; | |
112 | ||
16480515 | 113 | dmtimer_systimer_enable(t); |
52762fbd TL |
114 | l = readl_relaxed(sysc); |
115 | l |= BIT(0); | |
116 | writel_relaxed(l, sysc); | |
117 | ||
118 | return readl_poll_timeout_atomic(sysc, l, !(l & BIT(0)), 100, | |
119 | DMTIMER_RESET_WAIT); | |
120 | } | |
121 | ||
122 | static int __init dmtimer_systimer_reset(struct dmtimer_systimer *t) | |
123 | { | |
124 | int ret; | |
125 | ||
126 | if (dmtimer_systimer_revision1(t)) | |
127 | ret = dmtimer_systimer_type1_reset(t); | |
128 | else | |
129 | ret = dmtimer_systimer_type2_reset(t); | |
130 | if (ret < 0) { | |
131 | pr_err("%s failed with %i\n", __func__, ret); | |
132 | ||
133 | return ret; | |
134 | } | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | static const struct of_device_id counter_match_table[] = { | |
140 | { .compatible = "ti,omap-counter32k" }, | |
141 | { /* Sentinel */ }, | |
142 | }; | |
143 | ||
144 | /* | |
145 | * Check if the SoC als has a usable working 32 KiHz counter. The 32 KiHz | |
146 | * counter is handled by timer-ti-32k, but we need to detect it as it | |
147 | * affects the preferred dmtimer system timer configuration. There is | |
148 | * typically no use for a dmtimer clocksource if the 32 KiHz counter is | |
149 | * present, except on am437x as described below. | |
150 | */ | |
151 | static void __init dmtimer_systimer_check_counter32k(void) | |
152 | { | |
153 | struct device_node *np; | |
154 | ||
155 | if (counter_32k) | |
156 | return; | |
157 | ||
158 | np = of_find_matching_node(NULL, counter_match_table); | |
159 | if (!np) { | |
160 | counter_32k = -ENODEV; | |
161 | ||
162 | return; | |
163 | } | |
164 | ||
165 | if (of_device_is_available(np)) | |
166 | counter_32k = 1; | |
167 | else | |
168 | counter_32k = -ENODEV; | |
169 | ||
170 | of_node_put(np); | |
171 | } | |
172 | ||
173 | static const struct of_device_id dmtimer_match_table[] = { | |
174 | { .compatible = "ti,omap2420-timer", }, | |
175 | { .compatible = "ti,omap3430-timer", }, | |
176 | { .compatible = "ti,omap4430-timer", }, | |
177 | { .compatible = "ti,omap5430-timer", }, | |
178 | { .compatible = "ti,am335x-timer", }, | |
179 | { .compatible = "ti,am335x-timer-1ms", }, | |
180 | { .compatible = "ti,dm814-timer", }, | |
181 | { .compatible = "ti,dm816-timer", }, | |
182 | { /* Sentinel */ }, | |
183 | }; | |
184 | ||
185 | /* | |
186 | * Checks that system timers are configured to not reset and idle during | |
187 | * the generic timer-ti-dm device driver probe. And that the system timer | |
188 | * source clocks are properly configured. Also, let's not hog any DSP and | |
189 | * PWM capable timers unnecessarily as system timers. | |
190 | */ | |
191 | static bool __init dmtimer_is_preferred(struct device_node *np) | |
192 | { | |
193 | if (!of_device_is_available(np)) | |
194 | return false; | |
195 | ||
196 | if (!of_property_read_bool(np->parent, | |
197 | "ti,no-reset-on-init")) | |
198 | return false; | |
199 | ||
200 | if (!of_property_read_bool(np->parent, "ti,no-idle")) | |
201 | return false; | |
202 | ||
203 | /* Secure gptimer12 is always clocked with a fixed source */ | |
204 | if (!of_property_read_bool(np, "ti,timer-secure")) { | |
205 | if (!of_property_read_bool(np, "assigned-clocks")) | |
206 | return false; | |
207 | ||
208 | if (!of_property_read_bool(np, "assigned-clock-parents")) | |
209 | return false; | |
210 | } | |
211 | ||
212 | if (of_property_read_bool(np, "ti,timer-dsp")) | |
213 | return false; | |
214 | ||
215 | if (of_property_read_bool(np, "ti,timer-pwm")) | |
216 | return false; | |
217 | ||
218 | return true; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Finds the first available usable always-on timer, and assigns it to either | |
223 | * clockevent or clocksource depending if the counter_32k is available on the | |
224 | * SoC or not. | |
225 | * | |
226 | * Some omap3 boards with unreliable oscillator must not use the counter_32k | |
227 | * or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliable | |
228 | * oscillator should really set counter_32k as disabled, and delete dmtimer1 | |
229 | * ti,always-on property, but let's not count on it. For these quirky cases, | |
230 | * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz | |
231 | * clock as the clocksource, and any available dmtimer as clockevent. | |
232 | * | |
233 | * For am437x, we are using am335x style dmtimer clocksource. It is unclear | |
234 | * if this quirk handling is really needed, but let's change it separately | |
235 | * based on testing as it might cause side effects. | |
236 | */ | |
237 | static void __init dmtimer_systimer_assign_alwon(void) | |
238 | { | |
239 | struct device_node *np; | |
240 | u32 pa = 0; | |
241 | bool quirk_unreliable_oscillator = false; | |
242 | ||
243 | /* Quirk unreliable 32 KiHz oscillator with incomplete dts */ | |
8840f546 | 244 | if (of_machine_is_compatible("ti,omap3-beagle-ab4")) { |
52762fbd TL |
245 | quirk_unreliable_oscillator = true; |
246 | counter_32k = -ENODEV; | |
247 | } | |
248 | ||
249 | /* Quirk am437x using am335x style dmtimer clocksource */ | |
250 | if (of_machine_is_compatible("ti,am43")) | |
251 | counter_32k = -ENODEV; | |
252 | ||
253 | for_each_matching_node(np, dmtimer_match_table) { | |
254 | if (!dmtimer_is_preferred(np)) | |
255 | continue; | |
256 | ||
257 | if (of_property_read_bool(np, "ti,timer-alwon")) { | |
258 | const __be32 *addr; | |
259 | ||
260 | addr = of_get_address(np, 0, NULL, NULL); | |
261 | pa = of_translate_address(np, addr); | |
262 | if (pa) { | |
263 | /* Quirky omap3 boards must use dmtimer12 */ | |
264 | if (quirk_unreliable_oscillator && | |
265 | pa == 0x48318000) | |
266 | continue; | |
267 | ||
268 | of_node_put(np); | |
269 | break; | |
270 | } | |
271 | } | |
272 | } | |
273 | ||
274 | /* Usually no need for dmtimer clocksource if we have counter32 */ | |
275 | if (counter_32k >= 0) { | |
276 | clockevent = pa; | |
277 | clocksource = 0; | |
278 | } else { | |
279 | clocksource = pa; | |
280 | clockevent = DMTIMER_INST_DONT_CARE; | |
281 | } | |
282 | } | |
283 | ||
284 | /* Finds the first usable dmtimer, used for the don't care case */ | |
285 | static u32 __init dmtimer_systimer_find_first_available(void) | |
286 | { | |
287 | struct device_node *np; | |
288 | const __be32 *addr; | |
289 | u32 pa = 0; | |
290 | ||
291 | for_each_matching_node(np, dmtimer_match_table) { | |
292 | if (!dmtimer_is_preferred(np)) | |
293 | continue; | |
294 | ||
295 | addr = of_get_address(np, 0, NULL, NULL); | |
296 | pa = of_translate_address(np, addr); | |
297 | if (pa) { | |
298 | if (pa == clocksource || pa == clockevent) { | |
299 | pa = 0; | |
300 | continue; | |
301 | } | |
302 | ||
303 | of_node_put(np); | |
304 | break; | |
305 | } | |
306 | } | |
307 | ||
308 | return pa; | |
309 | } | |
310 | ||
311 | /* Selects the best clocksource and clockevent to use */ | |
312 | static void __init dmtimer_systimer_select_best(void) | |
313 | { | |
314 | dmtimer_systimer_check_counter32k(); | |
315 | dmtimer_systimer_assign_alwon(); | |
316 | ||
317 | if (clockevent == DMTIMER_INST_DONT_CARE) | |
318 | clockevent = dmtimer_systimer_find_first_available(); | |
319 | ||
320 | pr_debug("%s: counter_32k: %i clocksource: %08x clockevent: %08x\n", | |
321 | __func__, counter_32k, clocksource, clockevent); | |
322 | } | |
323 | ||
324 | /* Interface clocks are only available on some SoCs variants */ | |
6cfcd556 TL |
325 | static int __init dmtimer_systimer_init_clock(struct dmtimer_systimer *t, |
326 | struct device_node *np, | |
52762fbd TL |
327 | const char *name, |
328 | unsigned long *rate) | |
329 | { | |
330 | struct clk *clock; | |
331 | unsigned long r; | |
6cfcd556 | 332 | bool is_ick = false; |
52762fbd TL |
333 | int error; |
334 | ||
6cfcd556 TL |
335 | is_ick = !strncmp(name, "ick", 3); |
336 | ||
52762fbd | 337 | clock = of_clk_get_by_name(np, name); |
6cfcd556 | 338 | if ((PTR_ERR(clock) == -EINVAL) && is_ick) |
52762fbd TL |
339 | return 0; |
340 | else if (IS_ERR(clock)) | |
341 | return PTR_ERR(clock); | |
342 | ||
343 | error = clk_prepare_enable(clock); | |
344 | if (error) | |
345 | return error; | |
346 | ||
347 | r = clk_get_rate(clock); | |
180d35a7 YY |
348 | if (!r) { |
349 | clk_disable_unprepare(clock); | |
52762fbd | 350 | return -ENODEV; |
180d35a7 | 351 | } |
52762fbd | 352 | |
6cfcd556 TL |
353 | if (is_ick) |
354 | t->ick = clock; | |
355 | else | |
356 | t->fck = clock; | |
357 | ||
52762fbd TL |
358 | *rate = r; |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
52762fbd TL |
363 | static int __init dmtimer_systimer_setup(struct device_node *np, |
364 | struct dmtimer_systimer *t) | |
365 | { | |
366 | unsigned long rate; | |
367 | u8 regbase; | |
368 | int error; | |
369 | ||
370 | if (!of_device_is_compatible(np->parent, "ti,sysc")) | |
371 | return -EINVAL; | |
372 | ||
373 | t->base = of_iomap(np, 0); | |
374 | if (!t->base) | |
375 | return -ENXIO; | |
376 | ||
377 | /* | |
378 | * Enable optional assigned-clock-parents configured at the timer | |
379 | * node level. For regular device drivers, this is done automatically | |
380 | * by bus related code such as platform_drv_probe(). | |
381 | */ | |
382 | error = of_clk_set_defaults(np, false); | |
383 | if (error < 0) | |
384 | pr_err("%s: clock source init failed: %i\n", __func__, error); | |
385 | ||
386 | /* For ti-sysc, we have timer clocks at the parent module level */ | |
6cfcd556 | 387 | error = dmtimer_systimer_init_clock(t, np->parent, "fck", &rate); |
52762fbd TL |
388 | if (error) |
389 | goto err_unmap; | |
390 | ||
391 | t->rate = rate; | |
392 | ||
6cfcd556 | 393 | error = dmtimer_systimer_init_clock(t, np->parent, "ick", &rate); |
52762fbd TL |
394 | if (error) |
395 | goto err_unmap; | |
396 | ||
397 | if (dmtimer_systimer_revision1(t)) { | |
398 | t->irq_stat = OMAP_TIMER_V1_STAT_OFFSET; | |
399 | t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET; | |
400 | t->pend = _OMAP_TIMER_WRITE_PEND_OFFSET; | |
401 | regbase = 0; | |
402 | } else { | |
403 | t->irq_stat = OMAP_TIMER_V2_IRQSTATUS; | |
404 | t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET; | |
405 | regbase = OMAP_TIMER_V2_FUNC_OFFSET; | |
406 | t->pend = regbase + _OMAP_TIMER_WRITE_PEND_OFFSET; | |
407 | } | |
408 | ||
409 | t->sysc = OMAP_TIMER_OCP_CFG_OFFSET; | |
410 | t->load = regbase + _OMAP_TIMER_LOAD_OFFSET; | |
411 | t->counter = regbase + _OMAP_TIMER_COUNTER_OFFSET; | |
412 | t->ctrl = regbase + _OMAP_TIMER_CTRL_OFFSET; | |
413 | t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET; | |
414 | t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET; | |
415 | ||
52762fbd | 416 | dmtimer_systimer_reset(t); |
16480515 | 417 | dmtimer_systimer_enable(t); |
52762fbd TL |
418 | pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base), |
419 | readl_relaxed(t->base + t->sysc)); | |
420 | ||
421 | return 0; | |
422 | ||
423 | err_unmap: | |
424 | iounmap(t->base); | |
425 | ||
426 | return error; | |
427 | } | |
428 | ||
429 | /* Clockevent */ | |
430 | static struct dmtimer_clockevent * | |
431 | to_dmtimer_clockevent(struct clock_event_device *clockevent) | |
432 | { | |
433 | return container_of(clockevent, struct dmtimer_clockevent, dev); | |
434 | } | |
435 | ||
436 | static irqreturn_t dmtimer_clockevent_interrupt(int irq, void *data) | |
437 | { | |
438 | struct dmtimer_clockevent *clkevt = data; | |
439 | struct dmtimer_systimer *t = &clkevt->t; | |
440 | ||
441 | writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat); | |
442 | clkevt->dev.event_handler(&clkevt->dev); | |
443 | ||
444 | return IRQ_HANDLED; | |
445 | } | |
446 | ||
447 | static int dmtimer_set_next_event(unsigned long cycles, | |
448 | struct clock_event_device *evt) | |
449 | { | |
450 | struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); | |
451 | struct dmtimer_systimer *t = &clkevt->t; | |
452 | void __iomem *pend = t->base + t->pend; | |
453 | ||
52762fbd TL |
454 | while (readl_relaxed(pend) & WP_TCRR) |
455 | cpu_relax(); | |
21270992 | 456 | writel_relaxed(0xffffffff - cycles, t->base + t->counter); |
52762fbd | 457 | |
52762fbd TL |
458 | while (readl_relaxed(pend) & WP_TCLR) |
459 | cpu_relax(); | |
21270992 | 460 | writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); |
52762fbd TL |
461 | |
462 | return 0; | |
463 | } | |
464 | ||
465 | static int dmtimer_clockevent_shutdown(struct clock_event_device *evt) | |
466 | { | |
467 | struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); | |
468 | struct dmtimer_systimer *t = &clkevt->t; | |
469 | void __iomem *ctrl = t->base + t->ctrl; | |
470 | u32 l; | |
471 | ||
472 | l = readl_relaxed(ctrl); | |
473 | if (l & OMAP_TIMER_CTRL_ST) { | |
474 | l &= ~BIT(0); | |
475 | writel_relaxed(l, ctrl); | |
476 | /* Flush posted write */ | |
477 | l = readl_relaxed(ctrl); | |
478 | /* Wait for functional clock period x 3.5 */ | |
479 | udelay(3500000 / t->rate + 1); | |
480 | } | |
481 | writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static int dmtimer_set_periodic(struct clock_event_device *evt) | |
487 | { | |
488 | struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); | |
489 | struct dmtimer_systimer *t = &clkevt->t; | |
490 | void __iomem *pend = t->base + t->pend; | |
491 | ||
492 | dmtimer_clockevent_shutdown(evt); | |
493 | ||
494 | /* Looks like we need to first set the load value separately */ | |
52762fbd TL |
495 | while (readl_relaxed(pend) & WP_TLDR) |
496 | cpu_relax(); | |
21270992 | 497 | writel_relaxed(clkevt->period, t->base + t->load); |
52762fbd | 498 | |
52762fbd TL |
499 | while (readl_relaxed(pend) & WP_TCRR) |
500 | cpu_relax(); | |
21270992 | 501 | writel_relaxed(clkevt->period, t->base + t->counter); |
52762fbd | 502 | |
52762fbd TL |
503 | while (readl_relaxed(pend) & WP_TCLR) |
504 | cpu_relax(); | |
21270992 TL |
505 | writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
506 | t->base + t->ctrl); | |
52762fbd TL |
507 | |
508 | return 0; | |
509 | } | |
510 | ||
511 | static void omap_clockevent_idle(struct clock_event_device *evt) | |
512 | { | |
513 | struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); | |
514 | struct dmtimer_systimer *t = &clkevt->t; | |
515 | ||
516 | dmtimer_systimer_disable(t); | |
6cfcd556 | 517 | clk_disable(t->fck); |
52762fbd TL |
518 | } |
519 | ||
520 | static void omap_clockevent_unidle(struct clock_event_device *evt) | |
521 | { | |
522 | struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); | |
523 | struct dmtimer_systimer *t = &clkevt->t; | |
6cfcd556 TL |
524 | int error; |
525 | ||
526 | error = clk_enable(t->fck); | |
527 | if (error) | |
528 | pr_err("could not enable timer fck on resume: %i\n", error); | |
52762fbd TL |
529 | |
530 | dmtimer_systimer_enable(t); | |
531 | writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena); | |
532 | writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup); | |
533 | } | |
534 | ||
3efe7a87 TL |
535 | static int __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt, |
536 | struct device_node *np, | |
537 | unsigned int features, | |
538 | const struct cpumask *cpumask, | |
539 | const char *name, | |
540 | int rating) | |
52762fbd | 541 | { |
52762fbd TL |
542 | struct clock_event_device *dev; |
543 | struct dmtimer_systimer *t; | |
544 | int error; | |
52762fbd | 545 | |
52762fbd TL |
546 | t = &clkevt->t; |
547 | dev = &clkevt->dev; | |
548 | ||
549 | /* | |
550 | * We mostly use cpuidle_coupled with ARM local timers for runtime, | |
551 | * so there's probably no use for CLOCK_EVT_FEAT_DYNIRQ here. | |
552 | */ | |
3efe7a87 TL |
553 | dev->features = features; |
554 | dev->rating = rating; | |
52762fbd TL |
555 | dev->set_next_event = dmtimer_set_next_event; |
556 | dev->set_state_shutdown = dmtimer_clockevent_shutdown; | |
557 | dev->set_state_periodic = dmtimer_set_periodic; | |
558 | dev->set_state_oneshot = dmtimer_clockevent_shutdown; | |
ac4daf73 | 559 | dev->set_state_oneshot_stopped = dmtimer_clockevent_shutdown; |
52762fbd | 560 | dev->tick_resume = dmtimer_clockevent_shutdown; |
3efe7a87 | 561 | dev->cpumask = cpumask; |
52762fbd TL |
562 | |
563 | dev->irq = irq_of_parse_and_map(np, 0); | |
3efe7a87 TL |
564 | if (!dev->irq) |
565 | return -ENXIO; | |
52762fbd TL |
566 | |
567 | error = dmtimer_systimer_setup(np, &clkevt->t); | |
568 | if (error) | |
3efe7a87 | 569 | return error; |
52762fbd TL |
570 | |
571 | clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(t->rate, HZ); | |
572 | ||
573 | /* | |
574 | * For clock-event timers we never read the timer counter and | |
575 | * so we are not impacted by errata i103 and i767. Therefore, | |
576 | * we can safely ignore this errata for clock-event timers. | |
577 | */ | |
578 | writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl); | |
579 | ||
580 | error = request_irq(dev->irq, dmtimer_clockevent_interrupt, | |
3efe7a87 | 581 | IRQF_TIMER, name, clkevt); |
52762fbd TL |
582 | if (error) |
583 | goto err_out_unmap; | |
584 | ||
585 | writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena); | |
586 | writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup); | |
587 | ||
3efe7a87 TL |
588 | pr_info("TI gptimer %s: %s%lu Hz at %pOF\n", |
589 | name, of_find_property(np, "ti,timer-alwon", NULL) ? | |
52762fbd TL |
590 | "always-on " : "", t->rate, np->parent); |
591 | ||
3efe7a87 TL |
592 | return 0; |
593 | ||
594 | err_out_unmap: | |
595 | iounmap(t->base); | |
596 | ||
597 | return error; | |
598 | } | |
599 | ||
600 | static int __init dmtimer_clockevent_init(struct device_node *np) | |
601 | { | |
602 | struct dmtimer_clockevent *clkevt; | |
603 | int error; | |
604 | ||
605 | clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL); | |
606 | if (!clkevt) | |
607 | return -ENOMEM; | |
608 | ||
609 | error = dmtimer_clkevt_init_common(clkevt, np, | |
610 | CLOCK_EVT_FEAT_PERIODIC | | |
611 | CLOCK_EVT_FEAT_ONESHOT, | |
612 | cpu_possible_mask, "clockevent", | |
613 | 300); | |
614 | if (error) | |
615 | goto err_out_free; | |
616 | ||
617 | clockevents_config_and_register(&clkevt->dev, clkevt->t.rate, | |
4bf07f65 | 618 | 3, /* Timer internal resync latency */ |
52762fbd TL |
619 | 0xffffffff); |
620 | ||
6cfcd556 TL |
621 | if (of_machine_is_compatible("ti,am33xx") || |
622 | of_machine_is_compatible("ti,am43")) { | |
3efe7a87 TL |
623 | clkevt->dev.suspend = omap_clockevent_idle; |
624 | clkevt->dev.resume = omap_clockevent_unidle; | |
52762fbd TL |
625 | } |
626 | ||
627 | return 0; | |
628 | ||
52762fbd TL |
629 | err_out_free: |
630 | kfree(clkevt); | |
631 | ||
632 | return error; | |
633 | } | |
634 | ||
25de4ce5 TL |
635 | /* Dmtimer as percpu timer. See dra7 ARM architected timer wrap erratum i940 */ |
636 | static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer); | |
637 | ||
638 | static int __init dmtimer_percpu_timer_init(struct device_node *np, int cpu) | |
639 | { | |
640 | struct dmtimer_clockevent *clkevt; | |
641 | int error; | |
642 | ||
643 | if (!cpu_possible(cpu)) | |
644 | return -EINVAL; | |
645 | ||
646 | if (!of_property_read_bool(np->parent, "ti,no-reset-on-init") || | |
647 | !of_property_read_bool(np->parent, "ti,no-idle")) | |
648 | pr_warn("Incomplete dtb for percpu dmtimer %pOF\n", np->parent); | |
649 | ||
650 | clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu); | |
651 | ||
652 | error = dmtimer_clkevt_init_common(clkevt, np, CLOCK_EVT_FEAT_ONESHOT, | |
653 | cpumask_of(cpu), "percpu-dmtimer", | |
654 | 500); | |
655 | if (error) | |
656 | return error; | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | /* See TRM for timer internal resynch latency */ | |
662 | static int omap_dmtimer_starting_cpu(unsigned int cpu) | |
663 | { | |
664 | struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu); | |
665 | struct clock_event_device *dev = &clkevt->dev; | |
666 | struct dmtimer_systimer *t = &clkevt->t; | |
667 | ||
668 | clockevents_config_and_register(dev, t->rate, 3, ULONG_MAX); | |
669 | irq_force_affinity(dev->irq, cpumask_of(cpu)); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | static int __init dmtimer_percpu_timer_startup(void) | |
675 | { | |
676 | struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, 0); | |
677 | struct dmtimer_systimer *t = &clkevt->t; | |
678 | ||
679 | if (t->sysc) { | |
680 | cpuhp_setup_state(CPUHP_AP_TI_GP_TIMER_STARTING, | |
681 | "clockevents/omap/gptimer:starting", | |
682 | omap_dmtimer_starting_cpu, NULL); | |
683 | } | |
684 | ||
685 | return 0; | |
686 | } | |
687 | subsys_initcall(dmtimer_percpu_timer_startup); | |
688 | ||
689 | static int __init dmtimer_percpu_quirk_init(struct device_node *np, u32 pa) | |
690 | { | |
691 | struct device_node *arm_timer; | |
692 | ||
693 | arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer"); | |
694 | if (of_device_is_available(arm_timer)) { | |
695 | pr_warn_once("ARM architected timer wrap issue i940 detected\n"); | |
696 | return 0; | |
697 | } | |
698 | ||
bceaae3b | 699 | if (pa == 0x4882c000) /* dra7 dmtimer15 */ |
25de4ce5 | 700 | return dmtimer_percpu_timer_init(np, 0); |
bceaae3b | 701 | else if (pa == 0x4882e000) /* dra7 dmtimer16 */ |
25de4ce5 TL |
702 | return dmtimer_percpu_timer_init(np, 1); |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
52762fbd TL |
707 | /* Clocksource */ |
708 | static struct dmtimer_clocksource * | |
709 | to_dmtimer_clocksource(struct clocksource *cs) | |
710 | { | |
711 | return container_of(cs, struct dmtimer_clocksource, dev); | |
712 | } | |
713 | ||
714 | static u64 dmtimer_clocksource_read_cycles(struct clocksource *cs) | |
715 | { | |
716 | struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); | |
717 | struct dmtimer_systimer *t = &clksrc->t; | |
718 | ||
719 | return (u64)readl_relaxed(t->base + t->counter); | |
720 | } | |
721 | ||
722 | static void __iomem *dmtimer_sched_clock_counter; | |
723 | ||
724 | static u64 notrace dmtimer_read_sched_clock(void) | |
725 | { | |
726 | return readl_relaxed(dmtimer_sched_clock_counter); | |
727 | } | |
728 | ||
729 | static void dmtimer_clocksource_suspend(struct clocksource *cs) | |
730 | { | |
731 | struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); | |
732 | struct dmtimer_systimer *t = &clksrc->t; | |
733 | ||
734 | clksrc->loadval = readl_relaxed(t->base + t->counter); | |
735 | dmtimer_systimer_disable(t); | |
6cfcd556 | 736 | clk_disable(t->fck); |
52762fbd TL |
737 | } |
738 | ||
739 | static void dmtimer_clocksource_resume(struct clocksource *cs) | |
740 | { | |
741 | struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); | |
742 | struct dmtimer_systimer *t = &clksrc->t; | |
6cfcd556 TL |
743 | int error; |
744 | ||
745 | error = clk_enable(t->fck); | |
746 | if (error) | |
747 | pr_err("could not enable timer fck on resume: %i\n", error); | |
52762fbd TL |
748 | |
749 | dmtimer_systimer_enable(t); | |
750 | writel_relaxed(clksrc->loadval, t->base + t->counter); | |
751 | writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, | |
752 | t->base + t->ctrl); | |
753 | } | |
754 | ||
755 | static int __init dmtimer_clocksource_init(struct device_node *np) | |
756 | { | |
757 | struct dmtimer_clocksource *clksrc; | |
758 | struct dmtimer_systimer *t; | |
759 | struct clocksource *dev; | |
760 | int error; | |
52762fbd TL |
761 | |
762 | clksrc = kzalloc(sizeof(*clksrc), GFP_KERNEL); | |
763 | if (!clksrc) | |
764 | return -ENOMEM; | |
765 | ||
766 | dev = &clksrc->dev; | |
767 | t = &clksrc->t; | |
768 | ||
769 | error = dmtimer_systimer_setup(np, t); | |
770 | if (error) | |
771 | goto err_out_free; | |
772 | ||
773 | dev->name = "dmtimer"; | |
774 | dev->rating = 300; | |
775 | dev->read = dmtimer_clocksource_read_cycles; | |
776 | dev->mask = CLOCKSOURCE_MASK(32); | |
777 | dev->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
778 | ||
6cfcd556 TL |
779 | /* Unlike for clockevent, legacy code sets suspend only for am4 */ |
780 | if (of_machine_is_compatible("ti,am43")) { | |
52762fbd TL |
781 | dev->suspend = dmtimer_clocksource_suspend; |
782 | dev->resume = dmtimer_clocksource_resume; | |
783 | } | |
784 | ||
785 | writel_relaxed(0, t->base + t->counter); | |
786 | writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, | |
787 | t->base + t->ctrl); | |
788 | ||
52762fbd TL |
789 | pr_info("TI gptimer clocksource: %s%pOF\n", |
790 | of_find_property(np, "ti,timer-alwon", NULL) ? | |
791 | "always-on " : "", np->parent); | |
792 | ||
793 | if (!dmtimer_sched_clock_counter) { | |
794 | dmtimer_sched_clock_counter = t->base + t->counter; | |
795 | sched_clock_register(dmtimer_read_sched_clock, 32, t->rate); | |
796 | } | |
797 | ||
798 | if (clocksource_register_hz(dev, t->rate)) | |
799 | pr_err("Could not register clocksource %pOF\n", np); | |
800 | ||
801 | return 0; | |
802 | ||
803 | err_out_free: | |
804 | kfree(clksrc); | |
805 | ||
806 | return -ENODEV; | |
807 | } | |
808 | ||
809 | /* | |
810 | * To detect between a clocksource and clockevent, we assume the device tree | |
811 | * has no interrupts configured for a clocksource timer. | |
812 | */ | |
813 | static int __init dmtimer_systimer_init(struct device_node *np) | |
814 | { | |
815 | const __be32 *addr; | |
816 | u32 pa; | |
817 | ||
818 | /* One time init for the preferred timer configuration */ | |
819 | if (!clocksource && !clockevent) | |
820 | dmtimer_systimer_select_best(); | |
821 | ||
822 | if (!clocksource && !clockevent) { | |
ac593e62 | 823 | pr_err("%s: unable to detect system timers, update dtb?\n", |
52762fbd TL |
824 | __func__); |
825 | ||
826 | return -EINVAL; | |
827 | } | |
828 | ||
829 | addr = of_get_address(np, 0, NULL, NULL); | |
830 | pa = of_translate_address(np, addr); | |
831 | if (!pa) | |
832 | return -EINVAL; | |
833 | ||
834 | if (counter_32k <= 0 && clocksource == pa) | |
835 | return dmtimer_clocksource_init(np); | |
836 | ||
837 | if (clockevent == pa) | |
838 | return dmtimer_clockevent_init(np); | |
839 | ||
25de4ce5 TL |
840 | if (of_machine_is_compatible("ti,dra7")) |
841 | return dmtimer_percpu_quirk_init(np, pa); | |
842 | ||
52762fbd TL |
843 | return 0; |
844 | } | |
845 | ||
846 | TIMER_OF_DECLARE(systimer_omap2, "ti,omap2420-timer", dmtimer_systimer_init); | |
847 | TIMER_OF_DECLARE(systimer_omap3, "ti,omap3430-timer", dmtimer_systimer_init); | |
848 | TIMER_OF_DECLARE(systimer_omap4, "ti,omap4430-timer", dmtimer_systimer_init); | |
849 | TIMER_OF_DECLARE(systimer_omap5, "ti,omap5430-timer", dmtimer_systimer_init); | |
850 | TIMER_OF_DECLARE(systimer_am33x, "ti,am335x-timer", dmtimer_systimer_init); | |
851 | TIMER_OF_DECLARE(systimer_am3ms, "ti,am335x-timer-1ms", dmtimer_systimer_init); | |
852 | TIMER_OF_DECLARE(systimer_dm814, "ti,dm814-timer", dmtimer_systimer_init); | |
853 | TIMER_OF_DECLARE(systimer_dm816, "ti,dm816-timer", dmtimer_systimer_init); |