[linux-2.6-block.git] / drivers / clocksource / timer-tegra20.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/cpumask.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/percpu.h>
#include <linux/sched_clock.h>
#include <linux/time.h>

#include "timer-of.h"

#define RTC_SECONDS            0x08
#define RTC_SHADOW_SECONDS     0x0c
#define RTC_MILLISECONDS       0x10

#define TIMERUS_CNTR_1US 0x10
#define TIMERUS_USEC_CFG 0x14
#define TIMERUS_CNTR_FREEZE 0x4c

#define TIMER_PTV		0x0
#define TIMER_PTV_EN		BIT(31)
#define TIMER_PTV_PER		BIT(30)
#define TIMER_PCR		0x4
#define TIMER_PCR_INTR_CLR	BIT(30)

#define TIMER1_BASE		0x00
#define TIMER2_BASE		0x08
#define TIMER3_BASE		0x50
#define TIMER4_BASE		0x58
#define TIMER10_BASE		0x90

#define TIMER1_IRQ_IDX		0
#define TIMER10_IRQ_IDX		10

static u32 usec_config;
static void __iomem *timer_reg_base;

static int tegra_timer_set_next_event(unsigned long cycles,
					 struct clock_event_device *evt)
{
	void __iomem *reg_base = timer_of_base(to_timer_of(evt));

	writel(TIMER_PTV_EN |
	       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
	       reg_base + TIMER_PTV);

	return 0;
}

static int tegra_timer_shutdown(struct clock_event_device *evt)
{
	void __iomem *reg_base = timer_of_base(to_timer_of(evt));

	writel(0, reg_base + TIMER_PTV);

	return 0;
}

static int tegra_timer_set_periodic(struct clock_event_device *evt)
{
	void __iomem *reg_base = timer_of_base(to_timer_of(evt));

	writel(TIMER_PTV_EN | TIMER_PTV_PER |
	       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
	       reg_base + TIMER_PTV);

	return 0;
}

static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
	void __iomem *reg_base = timer_of_base(to_timer_of(evt));

	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void tegra_timer_suspend(struct clock_event_device *evt)
{
	void __iomem *reg_base = timer_of_base(to_timer_of(evt));

	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
}

static void tegra_timer_resume(struct clock_event_device *evt)
{
	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
}

static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,

	.clkevt = {
		.name = "tegra_timer",
		.rating = 460,
		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
		.set_next_event = tegra_timer_set_next_event,
		.set_state_shutdown = tegra_timer_shutdown,
		.set_state_periodic = tegra_timer_set_periodic,
		.set_state_oneshot = tegra_timer_shutdown,
		.tick_resume = tegra_timer_shutdown,
		.suspend = tegra_timer_suspend,
		.resume = tegra_timer_resume,
	},
};

static int tegra_timer_setup(unsigned int cpu)
{
	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);

	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
	enable_irq(to->clkevt.irq);

	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
					1, /* min */
					0x1fffffff); /* 29 bits */

	return 0;
}

static int tegra_timer_stop(unsigned int cpu)
{
	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);

	to->clkevt.set_state_shutdown(&to->clkevt);
	disable_irq_nosync(to->clkevt.irq);

	return 0;
}

static u64 notrace tegra_read_sched_clock(void)
{
	return readl(timer_reg_base + TIMERUS_CNTR_1US);
}

#ifdef CONFIG_ARM
static unsigned long tegra_delay_timer_read_counter_long(void)
{
	return readl(timer_reg_base + TIMERUS_CNTR_1US);
}

static struct delay_timer tegra_delay_timer = {
	.read_current_timer = tegra_delay_timer_read_counter_long,
	.freq = 1000000,
};
#endif

static struct timer_of suspend_rtc_to = {
	.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
};

/*
 * tegra_rtc_read - Reads the Tegra RTC registers
 * Care must be taken that this funciton is not called while the
 * tegra_rtc driver could be executing to avoid race conditions
 * on the RTC shadow register
 */
static u64 tegra_rtc_read_ms(struct clocksource *cs)
{
	u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS);
	u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS);
	return (u64)s * MSEC_PER_SEC + ms;
}

static struct clocksource suspend_rtc_clocksource = {
	.name	= "tegra_suspend_timer",
	.rating	= 200,
	.read	= tegra_rtc_read_ms,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
};

static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)
{
	if (tegra20) {
		switch (cpu) {
		case 0:
			return TIMER1_BASE;
		case 1:
			return TIMER2_BASE;
		case 2:
			return TIMER3_BASE;
		default:
			return TIMER4_BASE;
		}
	}

	return TIMER10_BASE + cpu * 8;
}

static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
{
	if (tegra20)
		return TIMER1_IRQ_IDX + cpu;

	return TIMER10_IRQ_IDX + cpu;
}

static int __init tegra_init_timer(struct device_node *np, bool tegra20)
{
	struct timer_of *to;
	int cpu, ret;

	to = this_cpu_ptr(&tegra_to);
	ret = timer_of_init(np, to);
	if (ret < 0)
		goto out;

	timer_reg_base = timer_of_base(to);

	/*
	 * Configure microsecond timers to have 1MHz clock
	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
	 * Uses n+1 scheme
	 */
	switch (timer_of_rate(to)) {
	case 12000000:
		usec_config = 0x000b; /* (11+1)/(0+1) */
		break;
	case 12800000:
		usec_config = 0x043f; /* (63+1)/(4+1) */
		break;
	case 13000000:
		usec_config = 0x000c; /* (12+1)/(0+1) */
		break;
	case 16800000:
		usec_config = 0x0453; /* (83+1)/(4+1) */
		break;
	case 19200000:
		usec_config = 0x045f; /* (95+1)/(4+1) */
		break;
	case 26000000:
		usec_config = 0x0019; /* (25+1)/(0+1) */
		break;
	case 38400000:
		usec_config = 0x04bf; /* (191+1)/(4+1) */
		break;
	case 48000000:
		usec_config = 0x002f; /* (47+1)/(0+1) */
		break;
	default:
		ret = -EINVAL;
		goto out;
	}

	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);

	for_each_possible_cpu(cpu) {
		struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
		unsigned int base = tegra_base_for_cpu(cpu, tegra20);
		unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);

		/*
		 * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
		 * parent clock.
		 */
		if (tegra20)
			cpu_to->of_clk.rate = 1000000;

		cpu_to = per_cpu_ptr(&tegra_to, cpu);
		cpu_to->of_base.base = timer_reg_base + base;
		cpu_to->clkevt.cpumask = cpumask_of(cpu);
		cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx);
		if (!cpu_to->clkevt.irq) {
			pr_err("%s: can't map IRQ for CPU%d\n",
			       __func__, cpu);
			ret = -EINVAL;
			goto out;
		}

		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
				  IRQF_TIMER | IRQF_NOBALANCING,
				  cpu_to->clkevt.name, &cpu_to->clkevt);
		if (ret) {
			pr_err("%s: cannot setup irq %d for CPU%d\n",
				__func__, cpu_to->clkevt.irq, cpu);
			ret = -EINVAL;
			goto out_irq;
		}
	}

	sched_clock_register(tegra_read_sched_clock, 32, 1000000);

	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
				    "timer_us", 1000000,
				    300, 32, clocksource_mmio_readl_up);
	if (ret)
		pr_err("failed to register clocksource: %d\n", ret);

#ifdef CONFIG_ARM
	register_current_timer_delay(&tegra_delay_timer);
#endif

	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
			  "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
			  tegra_timer_stop);

	return ret;
out_irq:
	for_each_possible_cpu(cpu) {
		struct timer_of *cpu_to;

		cpu_to = per_cpu_ptr(&tegra_to, cpu);
		if (cpu_to->clkevt.irq) {
			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
			irq_dispose_mapping(cpu_to->clkevt.irq);
		}
	}
out:
	timer_of_cleanup(to);
	return ret;
}

static int __init tegra210_init_timer(struct device_node *np)
{
	return tegra_init_timer(np, false);
}
TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);

static int __init tegra20_init_timer(struct device_node *np)
{
	return tegra_init_timer(np, true);
}
TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);

static int __init tegra20_init_rtc(struct device_node *np)
{
	int ret;

	ret = timer_of_init(np, &suspend_rtc_to);
	if (ret)
		return ret;

	clocksource_register_hz(&suspend_rtc_clocksource, 1000);

	return 0;
}
TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
2d5cd9a3	2	/*
2d5cd9a3 CC	3	* Copyright (C) 2010 Google, Inc.
	4	*
	5	* Author:
	6	* Colin Cross <ccross@google.com>
2d5cd9a3 CC	7	*/
2d5cd9a3 CC	8
b4822dc7 JL	9	#include <linux/clk.h>
	10	#include <linux/clockchips.h>
	11	#include <linux/cpu.h>
	12	#include <linux/cpumask.h>
	13	#include <linux/delay.h>
62248ae8	14	#include <linux/err.h>
2d5cd9a3	15	#include <linux/interrupt.h>
3a04931e	16	#include <linux/of_address.h>
56415480	17	#include <linux/of_irq.h>
b4822dc7	18	#include <linux/percpu.h>
38ff87f7	19	#include <linux/sched_clock.h>
b4822dc7 JL	20	#include <linux/time.h>
	21
	22	#include "timer-of.h"
2d5cd9a3	23
09361785 CC	24	#define RTC_SECONDS 0x08
	25	#define RTC_SHADOW_SECONDS 0x0c
	26	#define RTC_MILLISECONDS 0x10
	27
2d5cd9a3 CC	28	#define TIMERUS_CNTR_1US 0x10
	29	#define TIMERUS_USEC_CFG 0x14
	30	#define TIMERUS_CNTR_FREEZE 0x4c
	31
b4822dc7 JL	32	#define TIMER_PTV 0x0
	33	#define TIMER_PTV_EN BIT(31)
	34	#define TIMER_PTV_PER BIT(30)
	35	#define TIMER_PCR 0x4
	36	#define TIMER_PCR_INTR_CLR BIT(30)
	37
af8d9129 DO	38	#define TIMER1_BASE 0x00
	39	#define TIMER2_BASE 0x08
	40	#define TIMER3_BASE 0x50
	41	#define TIMER4_BASE 0x58
	42	#define TIMER10_BASE 0x90
	43
f6d50ec5	44	#define TIMER1_IRQ_IDX 0
b4822dc7	45	#define TIMER10_IRQ_IDX 10
b4822dc7 JL	46
b4822dc7 JL	47	static u32 usec_config;
3a04931e	48	static void __iomem *timer_reg_base;
2d5cd9a3 CC	49
	50	static int tegra_timer_set_next_event(unsigned long cycles,
	51	struct clock_event_device *evt)
	52	{
b4822dc7	53	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
2d5cd9a3	54
b4822dc7 JL	55	writel(TIMER_PTV_EN \|
	56	((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
	57	reg_base + TIMER_PTV);
2d5cd9a3 CC	58
	59	return 0;
	60	}
	61
b4822dc7	62	static int tegra_timer_shutdown(struct clock_event_device *evt)
2d5cd9a3	63	{
b4822dc7 JL	64	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
	65
	66	writel(0, reg_base + TIMER_PTV);
	67
	68	return 0;
4134d29b	69	}
2d5cd9a3	70
b4822dc7	71	static int tegra_timer_set_periodic(struct clock_event_device *evt)
4134d29b	72	{
b4822dc7 JL	73	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
	74
	75	writel(TIMER_PTV_EN \| TIMER_PTV_PER \|
	76	((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
	77	reg_base + TIMER_PTV);
	78
4134d29b VK	79	return 0;
	80	}
	81
b4822dc7 JL	82	static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
	83	{
	84	struct clock_event_device evt = (struct clock_event_device )dev_id;
	85	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
	86
	87	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
	88	evt->event_handler(evt);
	89
	90	return IRQ_HANDLED;
	91	}
	92
	93	static void tegra_timer_suspend(struct clock_event_device *evt)
	94	{
	95	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
	96
	97	writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
	98	}
	99
	100	static void tegra_timer_resume(struct clock_event_device *evt)
	101	{
	102	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
	103	}
	104
b4822dc7 JL	105	static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
	106	.flags = TIMER_OF_CLOCK \| TIMER_OF_BASE,
	107
	108	.clkevt = {
	109	.name = "tegra_timer",
	110	.rating = 460,
	111	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
	112	.set_next_event = tegra_timer_set_next_event,
	113	.set_state_shutdown = tegra_timer_shutdown,
	114	.set_state_periodic = tegra_timer_set_periodic,
	115	.set_state_oneshot = tegra_timer_shutdown,
	116	.tick_resume = tegra_timer_shutdown,
	117	.suspend = tegra_timer_suspend,
	118	.resume = tegra_timer_resume,
	119	},
	120	};
	121
	122	static int tegra_timer_setup(unsigned int cpu)
4134d29b	123	{
b4822dc7 JL	124	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
	125
	126	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
	127	enable_irq(to->clkevt.irq);
	128
	129	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
	130	1, /* min */
	131	0x1fffffff); /* 29 bits */
4134d29b	132
4134d29b	133	return 0;
2d5cd9a3 CC	134	}
2d5cd9a3 CC	135
b4822dc7 JL	136	static int tegra_timer_stop(unsigned int cpu)
	137	{
	138	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
	139
	140	to->clkevt.set_state_shutdown(&to->clkevt);
	141	disable_irq_nosync(to->clkevt.irq);
	142
	143	return 0;
	144	}
2d5cd9a3	145
35702999	146	static u64 notrace tegra_read_sched_clock(void)
e3f4c0ab	147	{
b4822dc7 JL	148	return readl(timer_reg_base + TIMERUS_CNTR_1US);
	149	}
	150
af8d9129	151	#ifdef CONFIG_ARM
b4822dc7 JL	152	static unsigned long tegra_delay_timer_read_counter_long(void)
	153	{
	154	return readl(timer_reg_base + TIMERUS_CNTR_1US);
2d5cd9a3 CC	155	}
2d5cd9a3 CC	156
af8d9129 DO	157	static struct delay_timer tegra_delay_timer = {
	158	.read_current_timer = tegra_delay_timer_read_counter_long,
	159	.freq = 1000000,
	160	};
	161	#endif
	162
95170f07 JL	163	static struct timer_of suspend_rtc_to = {
	164	.flags = TIMER_OF_BASE \| TIMER_OF_CLOCK,
	165	};
	166
09361785 CC	167	/*
	168	* tegra_rtc_read - Reads the Tegra RTC registers
	169	* Care must be taken that this funciton is not called while the
	170	* tegra_rtc driver could be executing to avoid race conditions
	171	* on the RTC shadow register
	172	*/
95170f07	173	static u64 tegra_rtc_read_ms(struct clocksource *cs)
09361785	174	{
95170f07 JL	175	u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS);
95170f07 JL	176	u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS);
09361785 CC	177	return (u64)s * MSEC_PER_SEC + ms;
	178	}
	179
95170f07 JL	180	static struct clocksource suspend_rtc_clocksource = {
	181	.name = "tegra_suspend_timer",
	182	.rating = 200,
	183	.read = tegra_rtc_read_ms,
	184	.mask = CLOCKSOURCE_MASK(32),
	185	.flags = CLOCK_SOURCE_IS_CONTINUOUS \| CLOCK_SOURCE_SUSPEND_NONSTOP,
	186	};
a0c2998f	187
af8d9129 DO	188	static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)
	189	{
	190	if (tegra20) {
	191	switch (cpu) {
	192	case 0:
	193	return TIMER1_BASE;
	194	case 1:
	195	return TIMER2_BASE;
	196	case 2:
	197	return TIMER3_BASE;
	198	default:
	199	return TIMER4_BASE;
	200	}
	201	}
	202
	203	return TIMER10_BASE + cpu * 8;
	204	}
	205
	206	static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
	207	{
	208	if (tegra20)
	209	return TIMER1_IRQ_IDX + cpu;
	210
	211	return TIMER10_IRQ_IDX + cpu;
	212	}
	213
	214	static int __init tegra_init_timer(struct device_node *np, bool tegra20)
2d5cd9a3	215	{
f6d50ec5 DO	216	struct timer_of *to;
f6d50ec5 DO	217	int cpu, ret;
3a04931e	218
f6d50ec5	219	to = this_cpu_ptr(&tegra_to);
b4822dc7 JL	220	ret = timer_of_init(np, to);
	221	if (ret < 0)
	222	goto out;
56415480	223
b4822dc7	224	timer_reg_base = timer_of_base(to);
62248ae8	225
b4822dc7 JL	226	/*
	227	* Configure microsecond timers to have 1MHz clock
	228	* Config register is 0xqqww, where qq is "dividend", ww is "divisor"
	229	* Uses n+1 scheme
	230	*/
	231	switch (timer_of_rate(to)) {
2d5cd9a3	232	case 12000000:
b4822dc7 JL	233	usec_config = 0x000b; /* (11+1)/(0+1) */
	234	break;
	235	case 12800000:
	236	usec_config = 0x043f; /* (63+1)/(4+1) */
2d5cd9a3 CC	237	break;
2d5cd9a3 CC	238	case 13000000:
b4822dc7 JL	239	usec_config = 0x000c; /* (12+1)/(0+1) */
	240	break;
	241	case 16800000:
	242	usec_config = 0x0453; /* (83+1)/(4+1) */
2d5cd9a3 CC	243	break;
2d5cd9a3 CC	244	case 19200000:
b4822dc7	245	usec_config = 0x045f; /* (95+1)/(4+1) */
2d5cd9a3 CC	246	break;
2d5cd9a3 CC	247	case 26000000:
b4822dc7 JL	248	usec_config = 0x0019; /* (25+1)/(0+1) */
	249	break;
	250	case 38400000:
	251	usec_config = 0x04bf; /* (191+1)/(4+1) */
	252	break;
	253	case 48000000:
	254	usec_config = 0x002f; /* (47+1)/(0+1) */
2d5cd9a3 CC	255	break;
2d5cd9a3 CC	256	default:
b4822dc7 JL	257	ret = -EINVAL;
	258	goto out;
	259	}
	260
f6d50ec5	261	writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
b4822dc7 JL	262
b4822dc7 JL	263	for_each_possible_cpu(cpu) {
f6d50ec5	264	struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
af8d9129 DO	265	unsigned int base = tegra_base_for_cpu(cpu, tegra20);
af8d9129 DO	266	unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
f6d50ec5 DO	267
	268	/*
	269	* TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
	270	* parent clock.
	271	*/
	272	if (tegra20)
	273	cpu_to->of_clk.rate = 1000000;
b4822dc7	274
af8d9129 DO	275	cpu_to = per_cpu_ptr(&tegra_to, cpu);
af8d9129 DO	276	cpu_to->of_base.base = timer_reg_base + base;
b4822dc7	277	cpu_to->clkevt.cpumask = cpumask_of(cpu);
af8d9129	278	cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx);
b4822dc7 JL	279	if (!cpu_to->clkevt.irq) {
	280	pr_err("%s: can't map IRQ for CPU%d\n",
	281	__func__, cpu);
	282	ret = -EINVAL;
	283	goto out;
	284	}
	285
	286	irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
	287	ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
	288	IRQF_TIMER \| IRQF_NOBALANCING,
	289	cpu_to->clkevt.name, &cpu_to->clkevt);
	290	if (ret) {
	291	pr_err("%s: cannot setup irq %d for CPU%d\n",
	292	__func__, cpu_to->clkevt.irq, cpu);
	293	ret = -EINVAL;
	294	goto out_irq;
	295	}
	296	}
	297
af8d9129 DO	298	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
	299
	300	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
	301	"timer_us", 1000000,
	302	300, 32, clocksource_mmio_readl_up);
	303	if (ret)
	304	pr_err("failed to register clocksource: %d\n", ret);
	305
	306	#ifdef CONFIG_ARM
	307	register_current_timer_delay(&tegra_delay_timer);
	308	#endif
	309
b4822dc7 JL	310	cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
	311	"AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
	312	tegra_timer_stop);
	313
	314	return ret;
	315	out_irq:
	316	for_each_possible_cpu(cpu) {
	317	struct timer_of *cpu_to;
	318
	319	cpu_to = per_cpu_ptr(&tegra_to, cpu);
	320	if (cpu_to->clkevt.irq) {
	321	free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
	322	irq_dispose_mapping(cpu_to->clkevt.irq);
	323	}
2d5cd9a3	324	}
b4822dc7 JL	325	out:
	326	timer_of_cleanup(to);
	327	return ret;
	328	}
f6d50ec5	329
f6d50ec5 DO	330	static int __init tegra210_init_timer(struct device_node *np)
	331	{
	332	return tegra_init_timer(np, false);
	333	}
	334	TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
af8d9129	335
f6d50ec5	336	static int __init tegra20_init_timer(struct device_node *np)
b4822dc7	337	{
af8d9129	338	return tegra_init_timer(np, true);
1d16cfb3	339	}
af8d9129	340	TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
1d16cfb3	341
53978bba	342	static int __init tegra20_init_rtc(struct device_node *np)
1d16cfb3	343	{
95170f07	344	int ret;
1d16cfb3	345
95170f07 JL	346	ret = timer_of_init(np, &suspend_rtc_to);
	347	if (ret)
	348	return ret;
1d16cfb3	349
95170f07	350	clocksource_register_hz(&suspend_rtc_clocksource, 1000);
1d16cfb3	351
95170f07	352	return 0;
2d5cd9a3	353	}
17273395	354	TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);