team: avoid complex list operations in team_nl_cmd_options_set()
[linux-2.6-block.git] / drivers / clocksource / timer-tegra20.c
CommitLineData
2d5cd9a3 1/*
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2 * Copyright (C) 2010 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/init.h>
62248ae8 19#include <linux/err.h>
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20#include <linux/time.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/clockchips.h>
24#include <linux/clocksource.h>
25#include <linux/clk.h>
26#include <linux/io.h>
3a04931e 27#include <linux/of_address.h>
56415480 28#include <linux/of_irq.h>
38ff87f7 29#include <linux/sched_clock.h>
0ff36b4f 30#include <linux/delay.h>
2d5cd9a3 31
2d5cd9a3 32#include <asm/mach/time.h>
2d5cd9a3 33
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34#define RTC_SECONDS 0x08
35#define RTC_SHADOW_SECONDS 0x0c
36#define RTC_MILLISECONDS 0x10
37
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38#define TIMERUS_CNTR_1US 0x10
39#define TIMERUS_USEC_CFG 0x14
40#define TIMERUS_CNTR_FREEZE 0x4c
41
42#define TIMER1_BASE 0x0
43#define TIMER2_BASE 0x8
44#define TIMER3_BASE 0x50
45#define TIMER4_BASE 0x58
46
47#define TIMER_PTV 0x0
48#define TIMER_PCR 0x4
49
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50static void __iomem *timer_reg_base;
51static void __iomem *rtc_base;
09361785 52
a0c2998f 53static struct timespec64 persistent_ts;
09361785 54static u64 persistent_ms, last_persistent_ms;
2d5cd9a3 55
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56static struct delay_timer tegra_delay_timer;
57
2d5cd9a3 58#define timer_writel(value, reg) \
59196bce 59 writel_relaxed(value, timer_reg_base + (reg))
2d5cd9a3 60#define timer_readl(reg) \
59196bce 61 readl_relaxed(timer_reg_base + (reg))
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62
63static int tegra_timer_set_next_event(unsigned long cycles,
64 struct clock_event_device *evt)
65{
66 u32 reg;
67
68 reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
69 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
70
71 return 0;
72}
73
4134d29b 74static inline void timer_shutdown(struct clock_event_device *evt)
2d5cd9a3 75{
2d5cd9a3 76 timer_writel(0, TIMER3_BASE + TIMER_PTV);
4134d29b 77}
2d5cd9a3 78
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79static int tegra_timer_shutdown(struct clock_event_device *evt)
80{
81 timer_shutdown(evt);
82 return 0;
83}
84
85static int tegra_timer_set_periodic(struct clock_event_device *evt)
86{
87 u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
88
89 timer_shutdown(evt);
90 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
91 return 0;
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92}
93
2d5cd9a3 94static struct clock_event_device tegra_clockevent = {
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95 .name = "timer0",
96 .rating = 300,
97 .features = CLOCK_EVT_FEAT_ONESHOT |
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98 CLOCK_EVT_FEAT_PERIODIC |
99 CLOCK_EVT_FEAT_DYNIRQ,
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100 .set_next_event = tegra_timer_set_next_event,
101 .set_state_shutdown = tegra_timer_shutdown,
102 .set_state_periodic = tegra_timer_set_periodic,
103 .set_state_oneshot = tegra_timer_shutdown,
104 .tick_resume = tegra_timer_shutdown,
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105};
106
35702999 107static u64 notrace tegra_read_sched_clock(void)
e3f4c0ab 108{
2f0778af 109 return timer_readl(TIMERUS_CNTR_1US);
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110}
111
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112/*
113 * tegra_rtc_read - Reads the Tegra RTC registers
114 * Care must be taken that this funciton is not called while the
115 * tegra_rtc driver could be executing to avoid race conditions
116 * on the RTC shadow register
117 */
b28fba2a 118static u64 tegra_rtc_read_ms(void)
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119{
120 u32 ms = readl(rtc_base + RTC_MILLISECONDS);
121 u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
122 return (u64)s * MSEC_PER_SEC + ms;
123}
124
125/*
a0c2998f 126 * tegra_read_persistent_clock64 - Return time from a persistent clock.
09361785
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127 *
128 * Reads the time from a source which isn't disabled during PM, the
129 * 32k sync timer. Convert the cycles elapsed since last read into
a0c2998f 130 * nsecs and adds to a monotonically increasing timespec64.
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131 * Care must be taken that this funciton is not called while the
132 * tegra_rtc driver could be executing to avoid race conditions
133 * on the RTC shadow register
134 */
a0c2998f 135static void tegra_read_persistent_clock64(struct timespec64 *ts)
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136{
137 u64 delta;
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138
139 last_persistent_ms = persistent_ms;
140 persistent_ms = tegra_rtc_read_ms();
141 delta = persistent_ms - last_persistent_ms;
142
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143 timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
144 *ts = persistent_ts;
145}
146
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147static unsigned long tegra_delay_timer_read_counter_long(void)
148{
149 return readl(timer_reg_base + TIMERUS_CNTR_1US);
150}
151
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152static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
153{
154 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
155 timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
156 evt->event_handler(evt);
157 return IRQ_HANDLED;
158}
159
160static struct irqaction tegra_timer_irq = {
161 .name = "timer0",
39304fad 162 .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
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163 .handler = tegra_timer_interrupt,
164 .dev_id = &tegra_clockevent,
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165};
166
53978bba 167static int __init tegra20_init_timer(struct device_node *np)
2d5cd9a3 168{
62248ae8 169 struct clk *clk;
8e4fab2c 170 unsigned long rate;
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171 int ret;
172
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173 timer_reg_base = of_iomap(np, 0);
174 if (!timer_reg_base) {
37340866 175 pr_err("Can't map timer registers\n");
53978bba 176 return -ENXIO;
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177 }
178
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179 tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
180 if (tegra_timer_irq.irq <= 0) {
181 pr_err("Failed to map timer IRQ\n");
53978bba 182 return -EINVAL;
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183 }
184
6f88fb8a 185 clk = of_clk_get(np, 0);
8e4fab2c 186 if (IS_ERR(clk)) {
58664f90 187 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
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188 rate = 12000000;
189 } else {
6a5278d0 190 clk_prepare_enable(clk);
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191 rate = clk_get_rate(clk);
192 }
62248ae8 193
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194 switch (rate) {
195 case 12000000:
196 timer_writel(0x000b, TIMERUS_USEC_CFG);
197 break;
198 case 13000000:
199 timer_writel(0x000c, TIMERUS_USEC_CFG);
200 break;
201 case 19200000:
202 timer_writel(0x045f, TIMERUS_USEC_CFG);
203 break;
204 case 26000000:
205 timer_writel(0x0019, TIMERUS_USEC_CFG);
206 break;
207 default:
208 WARN(1, "Unknown clock rate");
209 }
210
35702999 211 sched_clock_register(tegra_read_sched_clock, 32, 1000000);
e3f4c0ab 212
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213 ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
214 "timer_us", 1000000, 300, 32,
215 clocksource_mmio_readl_up);
216 if (ret) {
58664f90 217 pr_err("Failed to register clocksource\n");
53978bba 218 return ret;
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219 }
220
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221 tegra_delay_timer.read_current_timer =
222 tegra_delay_timer_read_counter_long;
223 tegra_delay_timer.freq = 1000000;
224 register_current_timer_delay(&tegra_delay_timer);
225
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226 ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
227 if (ret) {
58664f90 228 pr_err("Failed to register timer IRQ: %d\n", ret);
53978bba 229 return ret;
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230 }
231
f8f5fe86 232 tegra_clockevent.cpumask = cpu_possible_mask;
2d5cd9a3 233 tegra_clockevent.irq = tegra_timer_irq.irq;
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234 clockevents_config_and_register(&tegra_clockevent, 1000000,
235 0x1, 0x1fffffff);
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236
237 return 0;
1d16cfb3 238}
17273395 239TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
1d16cfb3 240
53978bba 241static int __init tegra20_init_rtc(struct device_node *np)
1d16cfb3
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242{
243 struct clk *clk;
244
245 rtc_base = of_iomap(np, 0);
246 if (!rtc_base) {
ac9ce6d1 247 pr_err("Can't map RTC registers\n");
53978bba 248 return -ENXIO;
1d16cfb3
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249 }
250
251 /*
252 * rtc registers are used by read_persistent_clock, keep the rtc clock
253 * enabled
254 */
8024206d 255 clk = of_clk_get(np, 0);
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256 if (IS_ERR(clk))
257 pr_warn("Unable to get rtc-tegra clock\n");
258 else
259 clk_prepare_enable(clk);
260
227e3958 261 return register_persistent_clock(tegra_read_persistent_clock64);
2d5cd9a3 262}
17273395 263TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);