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9c92ab61 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2d5cd9a3 | 2 | /* |
2d5cd9a3 CC |
3 | * Copyright (C) 2010 Google, Inc. |
4 | * | |
5 | * Author: | |
6 | * Colin Cross <ccross@google.com> | |
2d5cd9a3 CC |
7 | */ |
8 | ||
49a678b8 DO |
9 | #define pr_fmt(fmt) "tegra-timer: " fmt |
10 | ||
b4822dc7 JL |
11 | #include <linux/clk.h> |
12 | #include <linux/clockchips.h> | |
13 | #include <linux/cpu.h> | |
14 | #include <linux/cpumask.h> | |
15 | #include <linux/delay.h> | |
62248ae8 | 16 | #include <linux/err.h> |
2d5cd9a3 | 17 | #include <linux/interrupt.h> |
3a04931e | 18 | #include <linux/of_address.h> |
56415480 | 19 | #include <linux/of_irq.h> |
b4822dc7 | 20 | #include <linux/percpu.h> |
38ff87f7 | 21 | #include <linux/sched_clock.h> |
b4822dc7 JL |
22 | #include <linux/time.h> |
23 | ||
24 | #include "timer-of.h" | |
2d5cd9a3 | 25 | |
49a678b8 DO |
26 | #define RTC_SECONDS 0x08 |
27 | #define RTC_SHADOW_SECONDS 0x0c | |
28 | #define RTC_MILLISECONDS 0x10 | |
09361785 | 29 | |
49a678b8 DO |
30 | #define TIMERUS_CNTR_1US 0x10 |
31 | #define TIMERUS_USEC_CFG 0x14 | |
32 | #define TIMERUS_CNTR_FREEZE 0x4c | |
2d5cd9a3 | 33 | |
b4822dc7 JL |
34 | #define TIMER_PTV 0x0 |
35 | #define TIMER_PTV_EN BIT(31) | |
36 | #define TIMER_PTV_PER BIT(30) | |
37 | #define TIMER_PCR 0x4 | |
38 | #define TIMER_PCR_INTR_CLR BIT(30) | |
39 | ||
af8d9129 DO |
40 | #define TIMER1_BASE 0x00 |
41 | #define TIMER2_BASE 0x08 | |
42 | #define TIMER3_BASE 0x50 | |
43 | #define TIMER4_BASE 0x58 | |
44 | #define TIMER10_BASE 0x90 | |
45 | ||
f6d50ec5 | 46 | #define TIMER1_IRQ_IDX 0 |
b4822dc7 | 47 | #define TIMER10_IRQ_IDX 10 |
b4822dc7 | 48 | |
2e08a4bb DO |
49 | #define TIMER_1MHz 1000000 |
50 | ||
b4822dc7 | 51 | static u32 usec_config; |
3a04931e | 52 | static void __iomem *timer_reg_base; |
2d5cd9a3 CC |
53 | |
54 | static int tegra_timer_set_next_event(unsigned long cycles, | |
49a678b8 | 55 | struct clock_event_device *evt) |
2d5cd9a3 | 56 | { |
b4822dc7 | 57 | void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
2d5cd9a3 | 58 | |
0ef6b01d DO |
59 | /* |
60 | * Tegra's timer uses n+1 scheme for the counter, i.e. timer will | |
61 | * fire after one tick if 0 is loaded. | |
62 | * | |
63 | * The minimum and maximum numbers of oneshot ticks are defined | |
64 | * by clockevents_config_and_register(1, 0x1fffffff + 1) invocation | |
65 | * below in the code. Hence the cycles (ticks) can't be outside of | |
66 | * a range supportable by hardware. | |
67 | */ | |
68 | writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV); | |
2d5cd9a3 CC |
69 | |
70 | return 0; | |
71 | } | |
72 | ||
b4822dc7 | 73 | static int tegra_timer_shutdown(struct clock_event_device *evt) |
2d5cd9a3 | 74 | { |
b4822dc7 JL |
75 | void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
76 | ||
6b349c36 | 77 | writel_relaxed(0, reg_base + TIMER_PTV); |
b4822dc7 JL |
78 | |
79 | return 0; | |
4134d29b | 80 | } |
2d5cd9a3 | 81 | |
b4822dc7 | 82 | static int tegra_timer_set_periodic(struct clock_event_device *evt) |
4134d29b | 83 | { |
b4822dc7 | 84 | void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
09b2507f | 85 | unsigned long period = timer_of_period(to_timer_of(evt)); |
b4822dc7 | 86 | |
09b2507f | 87 | writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), |
6b349c36 | 88 | reg_base + TIMER_PTV); |
b4822dc7 | 89 | |
4134d29b VK |
90 | return 0; |
91 | } | |
92 | ||
b4822dc7 JL |
93 | static irqreturn_t tegra_timer_isr(int irq, void *dev_id) |
94 | { | |
7c708fda | 95 | struct clock_event_device *evt = dev_id; |
b4822dc7 JL |
96 | void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
97 | ||
6b349c36 | 98 | writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); |
b4822dc7 JL |
99 | evt->event_handler(evt); |
100 | ||
101 | return IRQ_HANDLED; | |
102 | } | |
103 | ||
104 | static void tegra_timer_suspend(struct clock_event_device *evt) | |
105 | { | |
106 | void __iomem *reg_base = timer_of_base(to_timer_of(evt)); | |
107 | ||
6b349c36 | 108 | writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); |
b4822dc7 JL |
109 | } |
110 | ||
111 | static void tegra_timer_resume(struct clock_event_device *evt) | |
112 | { | |
6b349c36 | 113 | writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); |
b4822dc7 JL |
114 | } |
115 | ||
b4822dc7 JL |
116 | static DEFINE_PER_CPU(struct timer_of, tegra_to) = { |
117 | .flags = TIMER_OF_CLOCK | TIMER_OF_BASE, | |
118 | ||
119 | .clkevt = { | |
120 | .name = "tegra_timer", | |
b4822dc7 JL |
121 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, |
122 | .set_next_event = tegra_timer_set_next_event, | |
123 | .set_state_shutdown = tegra_timer_shutdown, | |
124 | .set_state_periodic = tegra_timer_set_periodic, | |
125 | .set_state_oneshot = tegra_timer_shutdown, | |
126 | .tick_resume = tegra_timer_shutdown, | |
127 | .suspend = tegra_timer_suspend, | |
128 | .resume = tegra_timer_resume, | |
129 | }, | |
130 | }; | |
131 | ||
132 | static int tegra_timer_setup(unsigned int cpu) | |
4134d29b | 133 | { |
b4822dc7 JL |
134 | struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); |
135 | ||
6b349c36 DO |
136 | writel_relaxed(0, timer_of_base(to) + TIMER_PTV); |
137 | writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); | |
77d57d1d | 138 | |
b4822dc7 JL |
139 | irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); |
140 | enable_irq(to->clkevt.irq); | |
141 | ||
6fde3894 DO |
142 | /* |
143 | * Tegra's timer uses n+1 scheme for the counter, i.e. timer will | |
144 | * fire after one tick if 0 is loaded and thus minimum number of | |
145 | * ticks is 1. In result both of the clocksource's tick limits are | |
146 | * higher than a minimum and maximum that hardware register can | |
147 | * take by 1, this is then taken into account by set_next_event | |
148 | * callback. | |
149 | */ | |
b4822dc7 JL |
150 | clockevents_config_and_register(&to->clkevt, timer_of_rate(to), |
151 | 1, /* min */ | |
6fde3894 | 152 | 0x1fffffff + 1); /* max 29 bits + 1 */ |
4134d29b | 153 | |
4134d29b | 154 | return 0; |
2d5cd9a3 CC |
155 | } |
156 | ||
b4822dc7 JL |
157 | static int tegra_timer_stop(unsigned int cpu) |
158 | { | |
159 | struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); | |
160 | ||
161 | to->clkevt.set_state_shutdown(&to->clkevt); | |
162 | disable_irq_nosync(to->clkevt.irq); | |
163 | ||
164 | return 0; | |
165 | } | |
2d5cd9a3 | 166 | |
35702999 | 167 | static u64 notrace tegra_read_sched_clock(void) |
e3f4c0ab | 168 | { |
6b349c36 | 169 | return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); |
b4822dc7 JL |
170 | } |
171 | ||
af8d9129 | 172 | #ifdef CONFIG_ARM |
b4822dc7 JL |
173 | static unsigned long tegra_delay_timer_read_counter_long(void) |
174 | { | |
6b349c36 | 175 | return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); |
2d5cd9a3 CC |
176 | } |
177 | ||
af8d9129 DO |
178 | static struct delay_timer tegra_delay_timer = { |
179 | .read_current_timer = tegra_delay_timer_read_counter_long, | |
2e08a4bb | 180 | .freq = TIMER_1MHz, |
af8d9129 DO |
181 | }; |
182 | #endif | |
183 | ||
95170f07 JL |
184 | static struct timer_of suspend_rtc_to = { |
185 | .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, | |
186 | }; | |
187 | ||
09361785 CC |
188 | /* |
189 | * tegra_rtc_read - Reads the Tegra RTC registers | |
49a678b8 | 190 | * Care must be taken that this function is not called while the |
09361785 CC |
191 | * tegra_rtc driver could be executing to avoid race conditions |
192 | * on the RTC shadow register | |
193 | */ | |
95170f07 | 194 | static u64 tegra_rtc_read_ms(struct clocksource *cs) |
09361785 | 195 | { |
6b349c36 | 196 | void __iomem *reg_base = timer_of_base(&suspend_rtc_to); |
49a678b8 | 197 | |
6b349c36 DO |
198 | u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); |
199 | u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); | |
49a678b8 | 200 | |
09361785 CC |
201 | return (u64)s * MSEC_PER_SEC + ms; |
202 | } | |
203 | ||
95170f07 JL |
204 | static struct clocksource suspend_rtc_clocksource = { |
205 | .name = "tegra_suspend_timer", | |
206 | .rating = 200, | |
207 | .read = tegra_rtc_read_ms, | |
208 | .mask = CLOCKSOURCE_MASK(32), | |
209 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, | |
210 | }; | |
a0c2998f | 211 | |
af8d9129 DO |
212 | static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) |
213 | { | |
214 | if (tegra20) { | |
215 | switch (cpu) { | |
216 | case 0: | |
217 | return TIMER1_BASE; | |
218 | case 1: | |
219 | return TIMER2_BASE; | |
220 | case 2: | |
221 | return TIMER3_BASE; | |
222 | default: | |
223 | return TIMER4_BASE; | |
224 | } | |
225 | } | |
226 | ||
227 | return TIMER10_BASE + cpu * 8; | |
228 | } | |
229 | ||
230 | static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) | |
231 | { | |
232 | if (tegra20) | |
233 | return TIMER1_IRQ_IDX + cpu; | |
234 | ||
235 | return TIMER10_IRQ_IDX + cpu; | |
236 | } | |
237 | ||
99311d0e DO |
238 | static inline unsigned long tegra_rate_for_timer(struct timer_of *to, |
239 | bool tegra20) | |
240 | { | |
241 | /* | |
242 | * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the | |
243 | * parent clock. | |
244 | */ | |
245 | if (tegra20) | |
2e08a4bb | 246 | return TIMER_1MHz; |
99311d0e DO |
247 | |
248 | return timer_of_rate(to); | |
249 | } | |
250 | ||
87bd4c26 DO |
251 | static int __init tegra_init_timer(struct device_node *np, bool tegra20, |
252 | int rating) | |
2d5cd9a3 | 253 | { |
f6d50ec5 DO |
254 | struct timer_of *to; |
255 | int cpu, ret; | |
3a04931e | 256 | |
f6d50ec5 | 257 | to = this_cpu_ptr(&tegra_to); |
b4822dc7 | 258 | ret = timer_of_init(np, to); |
49a678b8 | 259 | if (ret) |
b4822dc7 | 260 | goto out; |
56415480 | 261 | |
b4822dc7 | 262 | timer_reg_base = timer_of_base(to); |
62248ae8 | 263 | |
b4822dc7 JL |
264 | /* |
265 | * Configure microsecond timers to have 1MHz clock | |
266 | * Config register is 0xqqww, where qq is "dividend", ww is "divisor" | |
267 | * Uses n+1 scheme | |
268 | */ | |
269 | switch (timer_of_rate(to)) { | |
2d5cd9a3 | 270 | case 12000000: |
b4822dc7 JL |
271 | usec_config = 0x000b; /* (11+1)/(0+1) */ |
272 | break; | |
273 | case 12800000: | |
274 | usec_config = 0x043f; /* (63+1)/(4+1) */ | |
2d5cd9a3 CC |
275 | break; |
276 | case 13000000: | |
b4822dc7 JL |
277 | usec_config = 0x000c; /* (12+1)/(0+1) */ |
278 | break; | |
279 | case 16800000: | |
280 | usec_config = 0x0453; /* (83+1)/(4+1) */ | |
2d5cd9a3 CC |
281 | break; |
282 | case 19200000: | |
b4822dc7 | 283 | usec_config = 0x045f; /* (95+1)/(4+1) */ |
2d5cd9a3 CC |
284 | break; |
285 | case 26000000: | |
b4822dc7 JL |
286 | usec_config = 0x0019; /* (25+1)/(0+1) */ |
287 | break; | |
288 | case 38400000: | |
289 | usec_config = 0x04bf; /* (191+1)/(4+1) */ | |
290 | break; | |
291 | case 48000000: | |
292 | usec_config = 0x002f; /* (47+1)/(0+1) */ | |
2d5cd9a3 CC |
293 | break; |
294 | default: | |
b4822dc7 JL |
295 | ret = -EINVAL; |
296 | goto out; | |
297 | } | |
298 | ||
6b349c36 | 299 | writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); |
b4822dc7 JL |
300 | |
301 | for_each_possible_cpu(cpu) { | |
f6d50ec5 | 302 | struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); |
99311d0e DO |
303 | unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING; |
304 | unsigned long rate = tegra_rate_for_timer(to, tegra20); | |
af8d9129 DO |
305 | unsigned int base = tegra_base_for_cpu(cpu, tegra20); |
306 | unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); | |
99311d0e | 307 | unsigned int irq = irq_of_parse_and_map(np, idx); |
f6d50ec5 | 308 | |
99311d0e | 309 | if (!irq) { |
49a678b8 | 310 | pr_err("failed to map irq for cpu%d\n", cpu); |
b4822dc7 | 311 | ret = -EINVAL; |
7a391670 | 312 | goto out_irq; |
b4822dc7 JL |
313 | } |
314 | ||
99311d0e DO |
315 | cpu_to->clkevt.irq = irq; |
316 | cpu_to->clkevt.rating = rating; | |
317 | cpu_to->clkevt.cpumask = cpumask_of(cpu); | |
318 | cpu_to->of_base.base = timer_reg_base + base; | |
09b2507f | 319 | cpu_to->of_clk.period = rate / HZ; |
99311d0e DO |
320 | cpu_to->of_clk.rate = rate; |
321 | ||
b4822dc7 | 322 | irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); |
99311d0e DO |
323 | |
324 | ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags, | |
b4822dc7 JL |
325 | cpu_to->clkevt.name, &cpu_to->clkevt); |
326 | if (ret) { | |
49a678b8 DO |
327 | pr_err("failed to set up irq for cpu%d: %d\n", |
328 | cpu, ret); | |
7a391670 DO |
329 | irq_dispose_mapping(cpu_to->clkevt.irq); |
330 | cpu_to->clkevt.irq = 0; | |
b4822dc7 JL |
331 | goto out_irq; |
332 | } | |
333 | } | |
334 | ||
2e08a4bb | 335 | sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz); |
af8d9129 DO |
336 | |
337 | ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, | |
2e08a4bb DO |
338 | "timer_us", TIMER_1MHz, 300, 32, |
339 | clocksource_mmio_readl_up); | |
af8d9129 DO |
340 | if (ret) |
341 | pr_err("failed to register clocksource: %d\n", ret); | |
342 | ||
343 | #ifdef CONFIG_ARM | |
344 | register_current_timer_delay(&tegra_delay_timer); | |
345 | #endif | |
346 | ||
49a678b8 DO |
347 | ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, |
348 | "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, | |
349 | tegra_timer_stop); | |
350 | if (ret) | |
351 | pr_err("failed to set up cpu hp state: %d\n", ret); | |
b4822dc7 JL |
352 | |
353 | return ret; | |
49a678b8 | 354 | |
b4822dc7 JL |
355 | out_irq: |
356 | for_each_possible_cpu(cpu) { | |
357 | struct timer_of *cpu_to; | |
358 | ||
359 | cpu_to = per_cpu_ptr(&tegra_to, cpu); | |
360 | if (cpu_to->clkevt.irq) { | |
361 | free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt); | |
362 | irq_dispose_mapping(cpu_to->clkevt.irq); | |
363 | } | |
2d5cd9a3 | 364 | } |
fc9babc2 DO |
365 | |
366 | to->of_base.base = timer_reg_base; | |
b4822dc7 JL |
367 | out: |
368 | timer_of_cleanup(to); | |
49a678b8 | 369 | |
b4822dc7 JL |
370 | return ret; |
371 | } | |
f6d50ec5 | 372 | |
f6d50ec5 DO |
373 | static int __init tegra210_init_timer(struct device_node *np) |
374 | { | |
87bd4c26 DO |
375 | /* |
376 | * Arch-timer can't survive across power cycle of CPU core and | |
377 | * after CPUPORESET signal due to a system design shortcoming, | |
378 | * hence tegra-timer is more preferable on Tegra210. | |
379 | */ | |
380 | return tegra_init_timer(np, false, 460); | |
f6d50ec5 DO |
381 | } |
382 | TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); | |
af8d9129 | 383 | |
f6d50ec5 | 384 | static int __init tegra20_init_timer(struct device_node *np) |
b4822dc7 | 385 | { |
87bd4c26 DO |
386 | int rating; |
387 | ||
388 | /* | |
389 | * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer, | |
390 | * that timer runs off the CPU clock and hence is subjected to | |
391 | * a jitter caused by DVFS clock rate changes. Tegra-timer is | |
392 | * more preferable for older Tegra's, while later SoC generations | |
393 | * have arch-timer as a main per-CPU timer and it is not affected | |
394 | * by DVFS changes. | |
395 | */ | |
396 | if (of_machine_is_compatible("nvidia,tegra20") || | |
397 | of_machine_is_compatible("nvidia,tegra30")) | |
398 | rating = 460; | |
399 | else | |
400 | rating = 330; | |
401 | ||
402 | return tegra_init_timer(np, true, rating); | |
1d16cfb3 | 403 | } |
af8d9129 | 404 | TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); |
1d16cfb3 | 405 | |
53978bba | 406 | static int __init tegra20_init_rtc(struct device_node *np) |
1d16cfb3 | 407 | { |
95170f07 | 408 | int ret; |
1d16cfb3 | 409 | |
95170f07 JL |
410 | ret = timer_of_init(np, &suspend_rtc_to); |
411 | if (ret) | |
412 | return ret; | |
1d16cfb3 | 413 | |
49a678b8 | 414 | return clocksource_register_hz(&suspend_rtc_clocksource, 1000); |
2d5cd9a3 | 415 | } |
17273395 | 416 | TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); |