[linux-2.6-block.git] / drivers / clocksource / timer-sun4i.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Allwinner A1X SoCs timer handling.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * Based on code from
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Benn Huang <benn@allwinnertech.com>
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include "timer-of.h"

#define TIMER_IRQ_EN_REG	0x00
#define TIMER_IRQ_EN(val)		BIT(val)
#define TIMER_IRQ_ST_REG	0x04
#define TIMER_IRQ_CLEAR(val)		BIT(val)
#define TIMER_CTL_REG(val)	(0x10 * val + 0x10)
#define TIMER_CTL_ENABLE		BIT(0)
#define TIMER_CTL_RELOAD		BIT(1)
#define TIMER_CTL_CLK_SRC(val)		(((val) & 0x3) << 2)
#define TIMER_CTL_CLK_SRC_OSC24M		(1)
#define TIMER_CTL_CLK_PRES(val)		(((val) & 0x7) << 4)
#define TIMER_CTL_ONESHOT		BIT(7)
#define TIMER_INTVAL_REG(val)	(0x10 * (val) + 0x14)
#define TIMER_CNTVAL_REG(val)	(0x10 * (val) + 0x18)

#define TIMER_SYNC_TICKS	3

/*
 * When we disable a timer, we need to wait at least for 2 cycles of
 * the timer source clock. We will use for that the clocksource timer
 * that is already setup and runs at the same frequency than the other
 * timers, and we never will be disabled.
 */
static void sun4i_clkevt_sync(void __iomem *base)
{
	u32 old = readl(base + TIMER_CNTVAL_REG(1));

	while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
		cpu_relax();
}

static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
{
	u32 val = readl(base + TIMER_CTL_REG(timer));
	writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
	sun4i_clkevt_sync(base);
}

static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
				    unsigned long delay)
{
	writel(delay, base + TIMER_INTVAL_REG(timer));
}

static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
				    bool periodic)
{
	u32 val = readl(base + TIMER_CTL_REG(timer));

	if (periodic)
		val &= ~TIMER_CTL_ONESHOT;
	else
		val |= TIMER_CTL_ONESHOT;

	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
	       base + TIMER_CTL_REG(timer));
}

static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);

	sun4i_clkevt_time_stop(timer_of_base(to), 0);

	return 0;
}

static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);

	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	sun4i_clkevt_time_start(timer_of_base(to), 0, false);

	return 0;
}

static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);

	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
	sun4i_clkevt_time_start(timer_of_base(to), 0, true);

	return 0;
}

static int sun4i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *clkevt)
{
	struct timer_of *to = to_timer_of(clkevt);

	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
	sun4i_clkevt_time_start(timer_of_base(to), 0, false);

	return 0;
}

static void sun4i_timer_clear_interrupt(void __iomem *base)
{
	writel(TIMER_IRQ_CLEAR(0), base + TIMER_IRQ_ST_REG);
}

static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	struct timer_of *to = to_timer_of(evt);

	sun4i_timer_clear_interrupt(timer_of_base(to));
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct timer_of to = {
	.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,

	.clkevt = {
		.name = "sun4i_tick",
		.rating = 350,
		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
		.set_state_shutdown = sun4i_clkevt_shutdown,
		.set_state_periodic = sun4i_clkevt_set_periodic,
		.set_state_oneshot = sun4i_clkevt_set_oneshot,
		.tick_resume = sun4i_clkevt_shutdown,
		.set_next_event = sun4i_clkevt_next_event,
		.cpumask = cpu_possible_mask,
	},

	.of_irq = {
		.handler = sun4i_timer_interrupt,
		.flags = IRQF_TIMER | IRQF_IRQPOLL,
	},
};

static u64 notrace sun4i_timer_sched_read(void)
{
	return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
}

static int __init sun4i_timer_init(struct device_node *node)
{
	int ret;
	u32 val;

	ret = timer_of_init(node, &to);
	if (ret)
		return ret;

	writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
	       TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_of_base(&to) + TIMER_CTL_REG(1));

	/*
	 * sched_clock_register does not have priorities, and on sun6i and
	 * later there is a better sched_clock registered by arm_arch_timer.c
	 */
	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
	    of_machine_is_compatible("allwinner,sun5i-a13") ||
	    of_machine_is_compatible("allwinner,sun5i-a10s") ||
	    of_machine_is_compatible("allwinner,suniv-f1c100s"))
		sched_clock_register(sun4i_timer_sched_read, 32,
				     timer_of_rate(&to));

	ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
				    node->name, timer_of_rate(&to), 350, 32,
				    clocksource_mmio_readl_down);
	if (ret) {
		pr_err("Failed to register clocksource\n");
		return ret;
	}

	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_of_base(&to) + TIMER_CTL_REG(0));

	/* Make sure timer is stopped before playing with interrupts */
	sun4i_clkevt_time_stop(timer_of_base(&to), 0);

	/* clear timer0 interrupt */
	sun4i_timer_clear_interrupt(timer_of_base(&to));

	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
					TIMER_SYNC_TICKS, 0xffffffff);

	/* Enable timer0 interrupt */
	val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);

	return ret;
}
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
		       sun4i_timer_init);
TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
		 sun4i_timer_init);
TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
		 sun4i_timer_init);
TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
		       sun4i_timer_init);
Commit	Line	Data
60bff9f8	1	// SPDX-License-Identifier: GPL-2.0
b2ac5d75 MR	2	/*
	3	* Allwinner A1X SoCs timer handling.
	4	*
	5	* Copyright (C) 2012 Maxime Ripard
	6	*
	7	* Maxime Ripard <maxime.ripard@free-electrons.com>
	8	*
	9	* Based on code from
	10	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	11	* Benn Huang <benn@allwinnertech.com>
b2ac5d75 MR	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/clockchips.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/irqreturn.h>
137c6b3c	19	#include <linux/sched_clock.h>
b2ac5d75 MR	20	#include <linux/of.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
b2ac5d75	23
239751ed DL	24	#include "timer-of.h"
239751ed DL	25
04981731	26	#define TIMER_IRQ_EN_REG 0x00
40777645	27	#define TIMER_IRQ_EN(val) BIT(val)
b2ac5d75	28	#define TIMER_IRQ_ST_REG 0x04
4364044c	29	#define TIMER_IRQ_CLEAR(val) BIT(val)
04981731	30	#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
40777645	31	#define TIMER_CTL_ENABLE BIT(0)
9eded232	32	#define TIMER_CTL_RELOAD BIT(1)
a2c49e7b MR	33	#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
	34	#define TIMER_CTL_CLK_SRC_OSC24M (1)
	35	#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
40777645	36	#define TIMER_CTL_ONESHOT BIT(7)
bb008b9e MR	37	#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
bb008b9e MR	38	#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
b2ac5d75	39
12e1480b MR	40	#define TIMER_SYNC_TICKS 3
12e1480b MR	41
63d88f1a MR	42	/*
	43	* When we disable a timer, we need to wait at least for 2 cycles of
	44	* the timer source clock. We will use for that the clocksource timer
	45	* that is already setup and runs at the same frequency than the other
	46	* timers, and we never will be disabled.
	47	*/
239751ed	48	static void sun4i_clkevt_sync(void __iomem *base)
63d88f1a	49	{
239751ed	50	u32 old = readl(base + TIMER_CNTVAL_REG(1));
63d88f1a	51
239751ed	52	while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
63d88f1a MR	53	cpu_relax();
	54	}
	55
239751ed	56	static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
96651a07	57	{
239751ed DL	58	u32 val = readl(base + TIMER_CTL_REG(timer));
	59	writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
	60	sun4i_clkevt_sync(base);
96651a07 MR	61	}
96651a07 MR	62
239751ed DL	63	static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
239751ed DL	64	unsigned long delay)
96651a07	65	{
239751ed	66	writel(delay, base + TIMER_INTVAL_REG(timer));
96651a07 MR	67	}
96651a07 MR	68
239751ed DL	69	static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
239751ed DL	70	bool periodic)
96651a07	71	{
239751ed	72	u32 val = readl(base + TIMER_CTL_REG(timer));
96651a07 MR	73
	74	if (periodic)
	75	val &= ~TIMER_CTL_ONESHOT;
	76	else
	77	val \|= TIMER_CTL_ONESHOT;
	78
7e141834	79	writel(val \| TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD,
239751ed	80	base + TIMER_CTL_REG(timer));
96651a07 MR	81	}
96651a07 MR	82
6de6c977	83	static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
b2ac5d75	84	{
239751ed DL	85	struct timer_of *to = to_timer_of(evt);
	86
	87	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	88
6de6c977 VK	89	return 0;
	90	}
	91
	92	static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
	93	{
239751ed DL	94	struct timer_of *to = to_timer_of(evt);
	95
	96	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	97	sun4i_clkevt_time_start(timer_of_base(to), 0, false);
	98
6de6c977 VK	99	return 0;
	100	}
	101
	102	static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
	103	{
239751ed DL	104	struct timer_of *to = to_timer_of(evt);
	105
	106	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	107	sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
	108	sun4i_clkevt_time_start(timer_of_base(to), 0, true);
	109
6de6c977	110	return 0;
b2ac5d75 MR	111	}
b2ac5d75 MR	112
119fd635	113	static int sun4i_clkevt_next_event(unsigned long evt,
239751ed	114	struct clock_event_device *clkevt)
b2ac5d75	115	{
239751ed DL	116	struct timer_of *to = to_timer_of(clkevt);
	117
	118	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	119	sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
	120	sun4i_clkevt_time_start(timer_of_base(to), 0, false);
b2ac5d75 MR	121
	122	return 0;
	123	}
	124
239751ed	125	static void sun4i_timer_clear_interrupt(void __iomem *base)
b53e7d00	126	{
4364044c	127	writel(TIMER_IRQ_CLEAR(0), base + TIMER_IRQ_ST_REG);
b53e7d00	128	}
b2ac5d75	129
119fd635	130	static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
b2ac5d75	131	{
7a93d490	132	struct clock_event_device *evt = dev_id;
239751ed	133	struct timer_of *to = to_timer_of(evt);
b2ac5d75	134
239751ed	135	sun4i_timer_clear_interrupt(timer_of_base(to));
b2ac5d75 MR	136	evt->event_handler(evt);
	137
	138	return IRQ_HANDLED;
	139	}
	140
239751ed DL	141	static struct timer_of to = {
	142	.flags = TIMER_OF_IRQ \| TIMER_OF_CLOCK \| TIMER_OF_BASE,
	143
	144	.clkevt = {
	145	.name = "sun4i_tick",
	146	.rating = 350,
	147	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	148	.set_state_shutdown = sun4i_clkevt_shutdown,
	149	.set_state_periodic = sun4i_clkevt_set_periodic,
	150	.set_state_oneshot = sun4i_clkevt_set_oneshot,
	151	.tick_resume = sun4i_clkevt_shutdown,
	152	.set_next_event = sun4i_clkevt_next_event,
	153	.cpumask = cpu_possible_mask,
	154	},
	155
	156	.of_irq = {
	157	.handler = sun4i_timer_interrupt,
	158	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	159	},
b2ac5d75 MR	160	};
b2ac5d75 MR	161
662e7230	162	static u64 notrace sun4i_timer_sched_read(void)
137c6b3c	163	{
239751ed	164	return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
137c6b3c MR	165	}
137c6b3c MR	166
ce5dc743	167	static int __init sun4i_timer_init(struct device_node *node)
b2ac5d75	168	{
239751ed	169	int ret;
b2ac5d75 MR	170	u32 val;
b2ac5d75 MR	171
239751ed DL	172	ret = timer_of_init(node, &to);
239751ed DL	173	if (ret)
ce5dc743	174	return ret;
b2ac5d75	175
239751ed	176	writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
137c6b3c MR	177	writel(TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD \|
137c6b3c MR	178	TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
239751ed	179	timer_of_base(&to) + TIMER_CTL_REG(1));
137c6b3c	180
37b8b003 HG	181	/*
	182	* sched_clock_register does not have priorities, and on sun6i and
	183	* later there is a better sched_clock registered by arm_arch_timer.c
	184	*/
	185	if (of_machine_is_compatible("allwinner,sun4i-a10") \|\|
	186	of_machine_is_compatible("allwinner,sun5i-a13") \|\|
0113ab80 MK	187	of_machine_is_compatible("allwinner,sun5i-a10s") \|\|
0113ab80 MK	188	of_machine_is_compatible("allwinner,suniv-f1c100s"))
239751ed DL	189	sched_clock_register(sun4i_timer_sched_read, 32,
239751ed DL	190	timer_of_rate(&to));
37b8b003	191
239751ed DL	192	ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
	193	node->name, timer_of_rate(&to), 350, 32,
	194	clocksource_mmio_readl_down);
ce5dc743	195	if (ret) {
ac9ce6d1	196	pr_err("Failed to register clocksource\n");
ce5dc743 DL	197	return ret;
ce5dc743 DL	198	}
137c6b3c	199
7e141834	200	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
239751ed	201	timer_of_base(&to) + TIMER_CTL_REG(0));
b2ac5d75	202
6db50bb6	203	/* Make sure timer is stopped before playing with interrupts */
239751ed	204	sun4i_clkevt_time_stop(timer_of_base(&to), 0);
6db50bb6	205
b53e7d00	206	/* clear timer0 interrupt */
239751ed	207	sun4i_timer_clear_interrupt(timer_of_base(&to));
6bab4a8a	208
239751ed	209	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
6bab4a8a MR	210	TIMER_SYNC_TICKS, 0xffffffff);
6bab4a8a MR	211
b2ac5d75	212	/* Enable timer0 interrupt */
239751ed DL	213	val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
239751ed DL	214	writel(val \| TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);
ce5dc743 DL	215
ce5dc743 DL	216	return ret;
b2ac5d75	217	}
17273395	218	TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
119fd635	219	sun4i_timer_init);
bca4e084 MR	220	TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
	221	sun4i_timer_init);
	222	TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
	223	sun4i_timer_init);
0113ab80 MK	224	TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
0113ab80 MK	225	sun4i_timer_init);