[linux-2.6-block.git] / drivers / clocksource / timer-sun4i.c

/*
 * Allwinner A1X SoCs timer handling.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * Based on code from
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Benn Huang <benn@allwinnertech.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include "timer-of.h"

#define TIMER_IRQ_EN_REG	0x00
#define TIMER_IRQ_EN(val)		BIT(val)
#define TIMER_IRQ_ST_REG	0x04
#define TIMER_CTL_REG(val)	(0x10 * val + 0x10)
#define TIMER_CTL_ENABLE		BIT(0)
#define TIMER_CTL_RELOAD		BIT(1)
#define TIMER_CTL_CLK_SRC(val)		(((val) & 0x3) << 2)
#define TIMER_CTL_CLK_SRC_OSC24M		(1)
#define TIMER_CTL_CLK_PRES(val)		(((val) & 0x7) << 4)
#define TIMER_CTL_ONESHOT		BIT(7)
#define TIMER_INTVAL_REG(val)	(0x10 * (val) + 0x14)
#define TIMER_CNTVAL_REG(val)	(0x10 * (val) + 0x18)

#define TIMER_SYNC_TICKS	3

/*
 * When we disable a timer, we need to wait at least for 2 cycles of
 * the timer source clock. We will use for that the clocksource timer
 * that is already setup and runs at the same frequency than the other
 * timers, and we never will be disabled.
 */
static void sun4i_clkevt_sync(void __iomem *base)
{
	u32 old = readl(base + TIMER_CNTVAL_REG(1));

	while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
		cpu_relax();
}

static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
{
	u32 val = readl(base + TIMER_CTL_REG(timer));
	writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
	sun4i_clkevt_sync(base);
}

static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
				    unsigned long delay)
{
	writel(delay, base + TIMER_INTVAL_REG(timer));
}

static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
				    bool periodic)
{
	u32 val = readl(base + TIMER_CTL_REG(timer));

	if (periodic)
		val &= ~TIMER_CTL_ONESHOT;
	else
		val |= TIMER_CTL_ONESHOT;

	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
	       base + TIMER_CTL_REG(timer));
}

static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);

	sun4i_clkevt_time_stop(timer_of_base(to), 0);

	return 0;
}

static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);

	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	sun4i_clkevt_time_start(timer_of_base(to), 0, false);

	return 0;
}

static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);

	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
	sun4i_clkevt_time_start(timer_of_base(to), 0, true);

	return 0;
}

static int sun4i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *clkevt)
{
	struct timer_of *to = to_timer_of(clkevt);

	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
	sun4i_clkevt_time_start(timer_of_base(to), 0, false);

	return 0;
}

static void sun4i_timer_clear_interrupt(void __iomem *base)
{
	writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
}

static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
	struct timer_of *to = to_timer_of(evt);

	sun4i_timer_clear_interrupt(timer_of_base(to));
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct timer_of to = {
	.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,

	.clkevt = {
		.name = "sun4i_tick",
		.rating = 350,
		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
		.set_state_shutdown = sun4i_clkevt_shutdown,
		.set_state_periodic = sun4i_clkevt_set_periodic,
		.set_state_oneshot = sun4i_clkevt_set_oneshot,
		.tick_resume = sun4i_clkevt_shutdown,
		.set_next_event = sun4i_clkevt_next_event,
		.cpumask = cpu_possible_mask,
	},

	.of_irq = {
		.handler = sun4i_timer_interrupt,
		.flags = IRQF_TIMER | IRQF_IRQPOLL,
	},
};

static u64 notrace sun4i_timer_sched_read(void)
{
	return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
}

static int __init sun4i_timer_init(struct device_node *node)
{
	int ret;
	u32 val;

	ret = timer_of_init(node, &to);
	if (ret)
		return ret;

	writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
	       TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_of_base(&to) + TIMER_CTL_REG(1));

	/*
	 * sched_clock_register does not have priorities, and on sun6i and
	 * later there is a better sched_clock registered by arm_arch_timer.c
	 */
	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
	    of_machine_is_compatible("allwinner,sun5i-a13") ||
	    of_machine_is_compatible("allwinner,sun5i-a10s") ||
	    of_machine_is_compatible("allwinner,suniv-f1c100s"))
		sched_clock_register(sun4i_timer_sched_read, 32,
				     timer_of_rate(&to));

	ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
				    node->name, timer_of_rate(&to), 350, 32,
				    clocksource_mmio_readl_down);
	if (ret) {
		pr_err("Failed to register clocksource\n");
		return ret;
	}

	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_of_base(&to) + TIMER_CTL_REG(0));

	/* Make sure timer is stopped before playing with interrupts */
	sun4i_clkevt_time_stop(timer_of_base(&to), 0);

	/* clear timer0 interrupt */
	sun4i_timer_clear_interrupt(timer_of_base(&to));

	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
					TIMER_SYNC_TICKS, 0xffffffff);

	/* Enable timer0 interrupt */
	val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);

	return ret;
}
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
		       sun4i_timer_init);
TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
		 sun4i_timer_init);
TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
		 sun4i_timer_init);
TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
		       sun4i_timer_init);
Commit	Line	Data
b2ac5d75 MR	1	/*
	2	* Allwinner A1X SoCs timer handling.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* Based on code from
	9	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	10	* Benn Huang <benn@allwinnertech.com>
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/irqreturn.h>
137c6b3c	22	#include <linux/sched_clock.h>
b2ac5d75 MR	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
b2ac5d75	26
239751ed DL	27	#include "timer-of.h"
239751ed DL	28
04981731	29	#define TIMER_IRQ_EN_REG 0x00
40777645	30	#define TIMER_IRQ_EN(val) BIT(val)
b2ac5d75	31	#define TIMER_IRQ_ST_REG 0x04
04981731	32	#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
40777645	33	#define TIMER_CTL_ENABLE BIT(0)
9eded232	34	#define TIMER_CTL_RELOAD BIT(1)
a2c49e7b MR	35	#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
	36	#define TIMER_CTL_CLK_SRC_OSC24M (1)
	37	#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
40777645	38	#define TIMER_CTL_ONESHOT BIT(7)
bb008b9e MR	39	#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
bb008b9e MR	40	#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
b2ac5d75	41
12e1480b MR	42	#define TIMER_SYNC_TICKS 3
12e1480b MR	43
63d88f1a MR	44	/*
	45	* When we disable a timer, we need to wait at least for 2 cycles of
	46	* the timer source clock. We will use for that the clocksource timer
	47	* that is already setup and runs at the same frequency than the other
	48	* timers, and we never will be disabled.
	49	*/
239751ed	50	static void sun4i_clkevt_sync(void __iomem *base)
63d88f1a	51	{
239751ed	52	u32 old = readl(base + TIMER_CNTVAL_REG(1));
63d88f1a	53
239751ed	54	while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
63d88f1a MR	55	cpu_relax();
	56	}
	57
239751ed	58	static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
96651a07	59	{
239751ed DL	60	u32 val = readl(base + TIMER_CTL_REG(timer));
	61	writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
	62	sun4i_clkevt_sync(base);
96651a07 MR	63	}
96651a07 MR	64
239751ed DL	65	static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
239751ed DL	66	unsigned long delay)
96651a07	67	{
239751ed	68	writel(delay, base + TIMER_INTVAL_REG(timer));
96651a07 MR	69	}
96651a07 MR	70
239751ed DL	71	static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
239751ed DL	72	bool periodic)
96651a07	73	{
239751ed	74	u32 val = readl(base + TIMER_CTL_REG(timer));
96651a07 MR	75
	76	if (periodic)
	77	val &= ~TIMER_CTL_ONESHOT;
	78	else
	79	val \|= TIMER_CTL_ONESHOT;
	80
7e141834	81	writel(val \| TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD,
239751ed	82	base + TIMER_CTL_REG(timer));
96651a07 MR	83	}
96651a07 MR	84
6de6c977	85	static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
b2ac5d75	86	{
239751ed DL	87	struct timer_of *to = to_timer_of(evt);
	88
	89	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	90
6de6c977 VK	91	return 0;
	92	}
	93
	94	static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
	95	{
239751ed DL	96	struct timer_of *to = to_timer_of(evt);
	97
	98	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	99	sun4i_clkevt_time_start(timer_of_base(to), 0, false);
	100
6de6c977 VK	101	return 0;
	102	}
	103
	104	static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
	105	{
239751ed DL	106	struct timer_of *to = to_timer_of(evt);
	107
	108	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	109	sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
	110	sun4i_clkevt_time_start(timer_of_base(to), 0, true);
	111
6de6c977	112	return 0;
b2ac5d75 MR	113	}
b2ac5d75 MR	114
119fd635	115	static int sun4i_clkevt_next_event(unsigned long evt,
239751ed	116	struct clock_event_device *clkevt)
b2ac5d75	117	{
239751ed DL	118	struct timer_of *to = to_timer_of(clkevt);
	119
	120	sun4i_clkevt_time_stop(timer_of_base(to), 0);
	121	sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
	122	sun4i_clkevt_time_start(timer_of_base(to), 0, false);
b2ac5d75 MR	123
	124	return 0;
	125	}
	126
239751ed	127	static void sun4i_timer_clear_interrupt(void __iomem *base)
b53e7d00	128	{
239751ed	129	writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
b53e7d00	130	}
b2ac5d75	131
119fd635	132	static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
b2ac5d75 MR	133	{
b2ac5d75 MR	134	struct clock_event_device evt = (struct clock_event_device )dev_id;
239751ed	135	struct timer_of *to = to_timer_of(evt);
b2ac5d75	136
239751ed	137	sun4i_timer_clear_interrupt(timer_of_base(to));
b2ac5d75 MR	138	evt->event_handler(evt);
	139
	140	return IRQ_HANDLED;
	141	}
	142
239751ed DL	143	static struct timer_of to = {
	144	.flags = TIMER_OF_IRQ \| TIMER_OF_CLOCK \| TIMER_OF_BASE,
	145
	146	.clkevt = {
	147	.name = "sun4i_tick",
	148	.rating = 350,
	149	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	150	.set_state_shutdown = sun4i_clkevt_shutdown,
	151	.set_state_periodic = sun4i_clkevt_set_periodic,
	152	.set_state_oneshot = sun4i_clkevt_set_oneshot,
	153	.tick_resume = sun4i_clkevt_shutdown,
	154	.set_next_event = sun4i_clkevt_next_event,
	155	.cpumask = cpu_possible_mask,
	156	},
	157
	158	.of_irq = {
	159	.handler = sun4i_timer_interrupt,
	160	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	161	},
b2ac5d75 MR	162	};
b2ac5d75 MR	163
662e7230	164	static u64 notrace sun4i_timer_sched_read(void)
137c6b3c	165	{
239751ed	166	return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
137c6b3c MR	167	}
137c6b3c MR	168
ce5dc743	169	static int __init sun4i_timer_init(struct device_node *node)
b2ac5d75	170	{
239751ed	171	int ret;
b2ac5d75 MR	172	u32 val;
b2ac5d75 MR	173
239751ed DL	174	ret = timer_of_init(node, &to);
239751ed DL	175	if (ret)
ce5dc743	176	return ret;
b2ac5d75	177
239751ed	178	writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
137c6b3c MR	179	writel(TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD \|
137c6b3c MR	180	TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
239751ed	181	timer_of_base(&to) + TIMER_CTL_REG(1));
137c6b3c	182
37b8b003 HG	183	/*
	184	* sched_clock_register does not have priorities, and on sun6i and
	185	* later there is a better sched_clock registered by arm_arch_timer.c
	186	*/
	187	if (of_machine_is_compatible("allwinner,sun4i-a10") \|\|
	188	of_machine_is_compatible("allwinner,sun5i-a13") \|\|
0113ab80 MK	189	of_machine_is_compatible("allwinner,sun5i-a10s") \|\|
0113ab80 MK	190	of_machine_is_compatible("allwinner,suniv-f1c100s"))
239751ed DL	191	sched_clock_register(sun4i_timer_sched_read, 32,
239751ed DL	192	timer_of_rate(&to));
37b8b003	193
239751ed DL	194	ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
	195	node->name, timer_of_rate(&to), 350, 32,
	196	clocksource_mmio_readl_down);
ce5dc743	197	if (ret) {
ac9ce6d1	198	pr_err("Failed to register clocksource\n");
ce5dc743 DL	199	return ret;
ce5dc743 DL	200	}
137c6b3c	201
7e141834	202	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
239751ed	203	timer_of_base(&to) + TIMER_CTL_REG(0));
b2ac5d75	204
6db50bb6	205	/* Make sure timer is stopped before playing with interrupts */
239751ed	206	sun4i_clkevt_time_stop(timer_of_base(&to), 0);
6db50bb6	207
b53e7d00	208	/* clear timer0 interrupt */
239751ed	209	sun4i_timer_clear_interrupt(timer_of_base(&to));
6bab4a8a	210
239751ed	211	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
6bab4a8a MR	212	TIMER_SYNC_TICKS, 0xffffffff);
6bab4a8a MR	213
b2ac5d75	214	/* Enable timer0 interrupt */
239751ed DL	215	val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
239751ed DL	216	writel(val \| TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);
ce5dc743 DL	217
ce5dc743 DL	218	return ret;
b2ac5d75	219	}
17273395	220	TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
119fd635	221	sun4i_timer_init);
bca4e084 MR	222	TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
	223	sun4i_timer_init);
	224	TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
	225	sun4i_timer_init);
0113ab80 MK	226	TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
0113ab80 MK	227	sun4i_timer_init);