[linux-block.git] / drivers / clocksource / timer-sp804.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  linux/drivers/clocksource/timer-sp.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 */
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_clk.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <clocksource/timer-sp804.h>

#include "timer-sp.h"

static long __init sp804_get_clock_rate(struct clk *clk)
{
	long rate;
	int err;

	err = clk_prepare(clk);
	if (err) {
		pr_err("sp804: clock failed to prepare: %d\n", err);
		clk_put(clk);
		return err;
	}

	err = clk_enable(clk);
	if (err) {
		pr_err("sp804: clock failed to enable: %d\n", err);
		clk_unprepare(clk);
		clk_put(clk);
		return err;
	}

	rate = clk_get_rate(clk);
	if (rate < 0) {
		pr_err("sp804: clock failed to get rate: %ld\n", rate);
		clk_disable(clk);
		clk_unprepare(clk);
		clk_put(clk);
	}

	return rate;
}

static void __iomem *sched_clock_base;

static u64 notrace sp804_read(void)
{
	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
}

void __init sp804_timer_disable(void __iomem *base)
{
	writel(0, base + TIMER_CTRL);
}

int  __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
						     const char *name,
						     struct clk *clk,
						     int use_sched_clock)
{
	long rate;

	if (!clk) {
		clk = clk_get_sys("sp804", name);
		if (IS_ERR(clk)) {
			pr_err("sp804: clock not found: %d\n",
			       (int)PTR_ERR(clk));
			return PTR_ERR(clk);
		}
	}

	rate = sp804_get_clock_rate(clk);
	if (rate < 0)
		return -EINVAL;

	/* setup timer 0 as free-running clocksource */
	writel(0, base + TIMER_CTRL);
	writel(0xffffffff, base + TIMER_LOAD);
	writel(0xffffffff, base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, name,
		rate, 200, 32, clocksource_mmio_readl_down);

	if (use_sched_clock) {
		sched_clock_base = base;
		sched_clock_register(sp804_read, 32, rate);
	}

	return 0;
}


static void __iomem *clkevt_base;
static unsigned long clkevt_reload;

/*
 * IRQ handler for the timer
 */
static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static inline void timer_shutdown(struct clock_event_device *evt)
{
	writel(0, clkevt_base + TIMER_CTRL);
}

static int sp804_shutdown(struct clock_event_device *evt)
{
	timer_shutdown(evt);
	return 0;
}

static int sp804_set_periodic(struct clock_event_device *evt)
{
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
			     TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;

	timer_shutdown(evt);
	writel(clkevt_reload, clkevt_base + TIMER_LOAD);
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int sp804_set_next_event(unsigned long next,
	struct clock_event_device *evt)
{
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
			     TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;

	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device sp804_clockevent = {
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_DYNIRQ,
	.set_state_shutdown	= sp804_shutdown,
	.set_state_periodic	= sp804_set_periodic,
	.set_state_oneshot	= sp804_shutdown,
	.tick_resume		= sp804_shutdown,
	.set_next_event		= sp804_set_next_event,
	.rating			= 300,
};

static struct irqaction sp804_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= sp804_timer_interrupt,
	.dev_id		= &sp804_clockevent,
};

int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
{
	struct clock_event_device *evt = &sp804_clockevent;
	long rate;

	if (!clk)
		clk = clk_get_sys("sp804", name);
	if (IS_ERR(clk)) {
		pr_err("sp804: %s clock not found: %d\n", name,
			(int)PTR_ERR(clk));
		return PTR_ERR(clk);
	}

	rate = sp804_get_clock_rate(clk);
	if (rate < 0)
		return -EINVAL;

	clkevt_base = base;
	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
	evt->name = name;
	evt->irq = irq;
	evt->cpumask = cpu_possible_mask;

	writel(0, base + TIMER_CTRL);

	setup_irq(irq, &sp804_timer_irq);
	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);

	return 0;
}

static int __init sp804_of_init(struct device_node *np)
{
	static bool initialized = false;
	void __iomem *base;
	int irq, ret = -EINVAL;
	u32 irq_num = 0;
	struct clk *clk1, *clk2;
	const char *name = of_get_property(np, "compatible", NULL);

	base = of_iomap(np, 0);
	if (!base)
		return -ENXIO;

	/* Ensure timers are disabled */
	writel(0, base + TIMER_CTRL);
	writel(0, base + TIMER_2_BASE + TIMER_CTRL);

	if (initialized || !of_device_is_available(np)) {
		ret = -EINVAL;
		goto err;
	}

	clk1 = of_clk_get(np, 0);
	if (IS_ERR(clk1))
		clk1 = NULL;

	/* Get the 2nd clock if the timer has 3 timer clocks */
	if (of_clk_get_parent_count(np) == 3) {
		clk2 = of_clk_get(np, 1);
		if (IS_ERR(clk2)) {
			pr_err("sp804: %pOFn clock not found: %d\n", np,
				(int)PTR_ERR(clk2));
			clk2 = NULL;
		}
	} else
		clk2 = clk1;

	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0)
		goto err;

	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
	if (irq_num == 2) {

		ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
		if (ret)
			goto err;

		ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
		if (ret)
			goto err;
	} else {

		ret = __sp804_clockevents_init(base, irq, clk1 , name);
		if (ret)
			goto err;

		ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
							      name, clk2, 1);
		if (ret)
			goto err;
	}
	initialized = true;

	return 0;
err:
	iounmap(base);
	return ret;
}
TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);

static int __init integrator_cp_of_init(struct device_node *np)
{
	static int init_count = 0;
	void __iomem *base;
	int irq, ret = -EINVAL;
	const char *name = of_get_property(np, "compatible", NULL);
	struct clk *clk;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to iomap\n");
		return -ENXIO;
	}

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get clock\n");
		return PTR_ERR(clk);
	}

	/* Ensure timer is disabled */
	writel(0, base + TIMER_CTRL);

	if (init_count == 2 || !of_device_is_available(np))
		goto err;

	if (!init_count) {
		ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
		if (ret)
			goto err;
	} else {
		irq = irq_of_parse_and_map(np, 0);
		if (irq <= 0)
			goto err;

		ret = __sp804_clockevents_init(base, irq, clk, name);
		if (ret)
			goto err;
	}

	init_count++;
	return 0;
err:
	iounmap(base);
	return ret;
}
TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
e3887714	2	/*
0b7402dc	3	* linux/drivers/clocksource/timer-sp.c
e3887714 RK	4	*
	5	* Copyright (C) 1999 - 2003 ARM Limited
	6	* Copyright (C) 2000 Deep Blue Solutions Ltd
e3887714	7	*/
7ff550de	8	#include <linux/clk.h>
e3887714 RK	9	#include <linux/clocksource.h>
e3887714 RK	10	#include <linux/clockchips.h>
7ff550de	11	#include <linux/err.h>
e3887714 RK	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14	#include <linux/io.h>
7a0eca71 RH	15	#include <linux/of.h>
7a0eca71 RH	16	#include <linux/of_address.h>
b799cac7	17	#include <linux/of_clk.h>
7a0eca71	18	#include <linux/of_irq.h>
38ff87f7	19	#include <linux/sched_clock.h>
e3887714	20
0b7402dc SH	21	#include <clocksource/timer-sp804.h>
	22
	23	#include "timer-sp.h"
e3887714	24
7a0eca71	25	static long __init sp804_get_clock_rate(struct clk *clk)
7ff550de	26	{
7ff550de RK	27	long rate;
	28	int err;
	29
6f5ad963 RK	30	err = clk_prepare(clk);
6f5ad963 RK	31	if (err) {
7a0eca71	32	pr_err("sp804: clock failed to prepare: %d\n", err);
6f5ad963 RK	33	clk_put(clk);
	34	return err;
	35	}
	36
7ff550de RK	37	err = clk_enable(clk);
7ff550de RK	38	if (err) {
7a0eca71	39	pr_err("sp804: clock failed to enable: %d\n", err);
6f5ad963	40	clk_unprepare(clk);
7ff550de RK	41	clk_put(clk);
	42	return err;
	43	}
	44
	45	rate = clk_get_rate(clk);
	46	if (rate < 0) {
7a0eca71	47	pr_err("sp804: clock failed to get rate: %ld\n", rate);
7ff550de	48	clk_disable(clk);
6f5ad963	49	clk_unprepare(clk);
7ff550de RK	50	clk_put(clk);
	51	}
	52
	53	return rate;
	54	}
	55
a7bf6162 RH	56	static void __iomem *sched_clock_base;
a7bf6162 RH	57
9b12f3a8	58	static u64 notrace sp804_read(void)
a7bf6162 RH	59	{
	60	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
	61	}
	62
1e5f0519 SH	63	void __init sp804_timer_disable(void __iomem *base)
	64	{
	65	writel(0, base + TIMER_CTRL);
	66	}
	67
2ef2538b	68	int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
a7bf6162	69	const char *name,
7a0eca71	70	struct clk *clk,
a7bf6162	71	int use_sched_clock)
e3887714	72	{
7a0eca71 RH	73	long rate;
	74
	75	if (!clk) {
	76	clk = clk_get_sys("sp804", name);
	77	if (IS_ERR(clk)) {
	78	pr_err("sp804: clock not found: %d\n",
	79	(int)PTR_ERR(clk));
2ef2538b	80	return PTR_ERR(clk);
7a0eca71 RH	81	}
	82	}
	83
	84	rate = sp804_get_clock_rate(clk);
7ff550de	85	if (rate < 0)
2ef2538b	86	return -EINVAL;
7ff550de	87
e3887714	88	/* setup timer 0 as free-running clocksource */
bfe45e0b RK	89	writel(0, base + TIMER_CTRL);
	90	writel(0xffffffff, base + TIMER_LOAD);
	91	writel(0xffffffff, base + TIMER_VALUE);
e3887714	92	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
bfe45e0b	93	base + TIMER_CTRL);
e3887714	94
fb593cf3	95	clocksource_mmio_init(base + TIMER_VALUE, name,
7ff550de	96	rate, 200, 32, clocksource_mmio_readl_down);
a7bf6162 RH	97
	98	if (use_sched_clock) {
	99	sched_clock_base = base;
9b12f3a8	100	sched_clock_register(sp804_read, 32, rate);
a7bf6162	101	}
2ef2538b DL	102
2ef2538b DL	103	return 0;
e3887714 RK	104	}
	105
	106
	107	static void __iomem *clkevt_base;
23828a7a	108	static unsigned long clkevt_reload;
e3887714 RK	109
	110	/*
	111	* IRQ handler for the timer
	112	*/
	113	static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
	114	{
	115	struct clock_event_device *evt = dev_id;
	116
	117	/* clear the interrupt */
	118	writel(1, clkevt_base + TIMER_INTCLR);
	119
	120	evt->event_handler(evt);
	121
	122	return IRQ_HANDLED;
	123	}
	124
daea7283	125	static inline void timer_shutdown(struct clock_event_device *evt)
e3887714	126	{
daea7283 VK	127	writel(0, clkevt_base + TIMER_CTRL);
daea7283 VK	128	}
e3887714	129
daea7283 VK	130	static int sp804_shutdown(struct clock_event_device *evt)
	131	{
	132	timer_shutdown(evt);
	133	return 0;
	134	}
e3887714	135
daea7283 VK	136	static int sp804_set_periodic(struct clock_event_device *evt)
	137	{
	138	unsigned long ctrl = TIMER_CTRL_32BIT \| TIMER_CTRL_IE \|
	139	TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
e3887714	140
daea7283 VK	141	timer_shutdown(evt);
daea7283 VK	142	writel(clkevt_reload, clkevt_base + TIMER_LOAD);
e3887714	143	writel(ctrl, clkevt_base + TIMER_CTRL);
daea7283	144	return 0;
e3887714 RK	145	}
	146
	147	static int sp804_set_next_event(unsigned long next,
	148	struct clock_event_device *evt)
	149	{
daea7283 VK	150	unsigned long ctrl = TIMER_CTRL_32BIT \| TIMER_CTRL_IE \|
daea7283 VK	151	TIMER_CTRL_ONESHOT \| TIMER_CTRL_ENABLE;
e3887714 RK	152
e3887714 RK	153	writel(next, clkevt_base + TIMER_LOAD);
daea7283	154	writel(ctrl, clkevt_base + TIMER_CTRL);
e3887714 RK	155
	156	return 0;
	157	}
	158
	159	static struct clock_event_device sp804_clockevent = {
daea7283 VK	160	.features = CLOCK_EVT_FEAT_PERIODIC \|
	161	CLOCK_EVT_FEAT_ONESHOT \|
	162	CLOCK_EVT_FEAT_DYNIRQ,
	163	.set_state_shutdown = sp804_shutdown,
	164	.set_state_periodic = sp804_set_periodic,
	165	.set_state_oneshot = sp804_shutdown,
	166	.tick_resume = sp804_shutdown,
	167	.set_next_event = sp804_set_next_event,
	168	.rating = 300,
e3887714 RK	169	};
	170
	171	static struct irqaction sp804_timer_irq = {
	172	.name = "timer",
728fae6f	173	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
e3887714 RK	174	.handler = sp804_timer_interrupt,
	175	.dev_id = &sp804_clockevent,
	176	};
	177
2ef2538b	178	int __init __sp804_clockevents_init(void __iomem base, unsigned int irq, struct clk clk, const char *name)
e3887714 RK	179	{
e3887714 RK	180	struct clock_event_device *evt = &sp804_clockevent;
7a0eca71 RH	181	long rate;
	182
	183	if (!clk)
	184	clk = clk_get_sys("sp804", name);
	185	if (IS_ERR(clk)) {
	186	pr_err("sp804: %s clock not found: %d\n", name,
	187	(int)PTR_ERR(clk));
2ef2538b	188	return PTR_ERR(clk);
7a0eca71	189	}
23828a7a	190
7a0eca71	191	rate = sp804_get_clock_rate(clk);
23828a7a	192	if (rate < 0)
2ef2538b	193	return -EINVAL;
e3887714 RK	194
e3887714 RK	195	clkevt_base = base;
23828a7a	196	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
57cc4f7d RK	197	evt->name = name;
57cc4f7d RK	198	evt->irq = irq;
ea3aacf5	199	evt->cpumask = cpu_possible_mask;
e3887714	200
7a0eca71 RH	201	writel(0, base + TIMER_CTRL);
7a0eca71 RH	202
57cc4f7d	203	setup_irq(irq, &sp804_timer_irq);
7c324d83	204	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
2ef2538b DL	205
2ef2538b DL	206	return 0;
e3887714	207	}
7a0eca71	208
2ef2538b	209	static int __init sp804_of_init(struct device_node *np)
7a0eca71 RH	210	{
	211	static bool initialized = false;
	212	void __iomem *base;
2ef2538b	213	int irq, ret = -EINVAL;
7a0eca71 RH	214	u32 irq_num = 0;
	215	struct clk clk1, clk2;
	216	const char *name = of_get_property(np, "compatible", NULL);
	217
	218	base = of_iomap(np, 0);
2ef2538b DL	219	if (!base)
2ef2538b DL	220	return -ENXIO;
7a0eca71 RH	221
	222	/* Ensure timers are disabled */
	223	writel(0, base + TIMER_CTRL);
	224	writel(0, base + TIMER_2_BASE + TIMER_CTRL);
	225
2ef2538b DL	226	if (initialized \|\| !of_device_is_available(np)) {
2ef2538b DL	227	ret = -EINVAL;
7a0eca71	228	goto err;
2ef2538b	229	}
7a0eca71 RH	230
	231	clk1 = of_clk_get(np, 0);
	232	if (IS_ERR(clk1))
	233	clk1 = NULL;
	234
1bde9906	235	/* Get the 2nd clock if the timer has 3 timer clocks */
b799cac7	236	if (of_clk_get_parent_count(np) == 3) {
7a0eca71 RH	237	clk2 = of_clk_get(np, 1);
7a0eca71 RH	238	if (IS_ERR(clk2)) {
2a4849d2	239	pr_err("sp804: %pOFn clock not found: %d\n", np,
7a0eca71	240	(int)PTR_ERR(clk2));
1bde9906	241	clk2 = NULL;
7a0eca71 RH	242	}
	243	} else
	244	clk2 = clk1;
	245
	246	irq = irq_of_parse_and_map(np, 0);
	247	if (irq <= 0)
	248	goto err;
	249
	250	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
	251	if (irq_num == 2) {
2ef2538b DL	252
	253	ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
	254	if (ret)
	255	goto err;
	256
	257	ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
	258	if (ret)
	259	goto err;
7a0eca71	260	} else {
2ef2538b DL	261
	262	ret = __sp804_clockevents_init(base, irq, clk1 , name);
	263	if (ret)
	264	goto err;
	265
	266	ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
	267	name, clk2, 1);
	268	if (ret)
	269	goto err;
7a0eca71 RH	270	}
	271	initialized = true;
	272
2ef2538b	273	return 0;
7a0eca71 RH	274	err:
7a0eca71 RH	275	iounmap(base);
2ef2538b	276	return ret;
7a0eca71	277	}
17273395	278	TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
870e2928	279
2ef2538b	280	static int __init integrator_cp_of_init(struct device_node *np)
870e2928 RH	281	{
	282	static int init_count = 0;
	283	void __iomem *base;
2ef2538b	284	int irq, ret = -EINVAL;
870e2928	285	const char *name = of_get_property(np, "compatible", NULL);
9cf31380	286	struct clk *clk;
870e2928 RH	287
870e2928 RH	288	base = of_iomap(np, 0);
2ef2538b	289	if (!base) {
ac9ce6d1	290	pr_err("Failed to iomap\n");
2ef2538b DL	291	return -ENXIO;
	292	}
	293
9cf31380	294	clk = of_clk_get(np, 0);
2ef2538b	295	if (IS_ERR(clk)) {
ac9ce6d1	296	pr_err("Failed to get clock\n");
2ef2538b DL	297	return PTR_ERR(clk);
2ef2538b DL	298	}
870e2928 RH	299
	300	/* Ensure timer is disabled */
	301	writel(0, base + TIMER_CTRL);
	302
	303	if (init_count == 2 \|\| !of_device_is_available(np))
	304	goto err;
	305
2ef2538b DL	306	if (!init_count) {
	307	ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
	308	if (ret)
	309	goto err;
	310	} else {
870e2928 RH	311	irq = irq_of_parse_and_map(np, 0);
	312	if (irq <= 0)
	313	goto err;
	314
2ef2538b DL	315	ret = __sp804_clockevents_init(base, irq, clk, name);
	316	if (ret)
	317	goto err;
870e2928 RH	318	}
	319
	320	init_count++;
2ef2538b	321	return 0;
870e2928 RH	322	err:
870e2928 RH	323	iounmap(base);
2ef2538b	324	return ret;
870e2928	325	}
17273395	326	TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);