[linux-block.git] / drivers / clocksource / timer-riscv.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2012 Regents of the University of California
 * Copyright (C) 2017 SiFive
 *
 * All RISC-V systems have a timer attached to every hart.  These timers can
 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
 * setup events, or directly accessed using MMIO registers.
 */

#define pr_fmt(fmt) "riscv-timer: " fmt

#include <linux/acpi.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/sched_clock.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/limits.h>
#include <clocksource/timer-riscv.h>
#include <asm/smp.h>
#include <asm/cpufeature.h>
#include <asm/sbi.h>
#include <asm/timex.h>

static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
static bool riscv_timer_cannot_wake_cpu;

static void riscv_clock_event_stop(void)
{
	if (static_branch_likely(&riscv_sstc_available)) {
		csr_write(CSR_STIMECMP, ULONG_MAX);
		if (IS_ENABLED(CONFIG_32BIT))
			csr_write(CSR_STIMECMPH, ULONG_MAX);
	} else {
		sbi_set_timer(U64_MAX);
	}
}

static int riscv_clock_next_event(unsigned long delta,
		struct clock_event_device *ce)
{
	u64 next_tval = get_cycles64() + delta;

	if (static_branch_likely(&riscv_sstc_available)) {
#if defined(CONFIG_32BIT)
		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
		csr_write(CSR_STIMECMPH, next_tval >> 32);
#else
		csr_write(CSR_STIMECMP, next_tval);
#endif
	} else
		sbi_set_timer(next_tval);

	return 0;
}

static int riscv_clock_shutdown(struct clock_event_device *evt)
{
	riscv_clock_event_stop();
	return 0;
}

static unsigned int riscv_clock_event_irq;
static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
	.name			= "riscv_timer_clockevent",
	.features		= CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 100,
	.set_next_event		= riscv_clock_next_event,
	.set_state_shutdown	= riscv_clock_shutdown,
};

/*
 * It is guaranteed that all the timers across all the harts are synchronized
 * within one tick of each other, so while this could technically go
 * backwards when hopping between CPUs, practically it won't happen.
 */
static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
{
	return get_cycles64();
}

static u64 notrace riscv_sched_clock(void)
{
	return get_cycles64();
}

static struct clocksource riscv_clocksource = {
	.name		= "riscv_clocksource",
	.rating		= 400,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.read		= riscv_clocksource_rdtime,
#if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
	.vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
#else
	.vdso_clock_mode = VDSO_CLOCKMODE_NONE,
#endif
};

static int riscv_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);

	/* Clear timer interrupt */
	riscv_clock_event_stop();

	ce->cpumask = cpumask_of(cpu);
	ce->irq = riscv_clock_event_irq;
	if (riscv_timer_cannot_wake_cpu)
		ce->features |= CLOCK_EVT_FEAT_C3STOP;
	if (static_branch_likely(&riscv_sstc_available))
		ce->rating = 450;
	clockevents_config_and_register(ce, riscv_timebase, 100, ULONG_MAX);

	enable_percpu_irq(riscv_clock_event_irq,
			  irq_get_trigger_type(riscv_clock_event_irq));
	return 0;
}

static int riscv_timer_dying_cpu(unsigned int cpu)
{
	/*
	 * Stop the timer when the cpu is going to be offline otherwise
	 * the timer interrupt may be pending while performing power-down.
	 */
	riscv_clock_event_stop();
	disable_percpu_irq(riscv_clock_event_irq);

	return 0;
}

void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
{
	*mult = riscv_clocksource.mult;
	*shift = riscv_clocksource.shift;
}
EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);

/* called directly from the low-level interrupt handler */
static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);

	riscv_clock_event_stop();
	evdev->event_handler(evdev);

	return IRQ_HANDLED;
}

static int __init riscv_timer_init_common(void)
{
	int error;
	struct irq_domain *domain;
	struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();

	domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
	if (!domain) {
		pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
		       intc_fwnode);
		return -ENODEV;
	}

	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
	if (!riscv_clock_event_irq) {
		pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
		return -ENODEV;
	}

	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
	if (error) {
		pr_err("RISCV timer registration failed [%d]\n", error);
		return error;
	}

	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);

	error = request_percpu_irq(riscv_clock_event_irq,
				    riscv_timer_interrupt,
				    "riscv-timer", &riscv_clock_event);
	if (error) {
		pr_err("registering percpu irq failed [%d]\n", error);
		return error;
	}

	if (riscv_isa_extension_available(NULL, SSTC)) {
		pr_info("Timer interrupt in S-mode is available via sstc extension\n");
		static_branch_enable(&riscv_sstc_available);
	}

	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
			 "clockevents/riscv/timer:starting",
			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
	if (error)
		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
		       error);

	return error;
}

static int __init riscv_timer_init_dt(struct device_node *n)
{
	int cpuid, error;
	unsigned long hartid;
	struct device_node *child;

	error = riscv_of_processor_hartid(n, &hartid);
	if (error < 0) {
		pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
			n, hartid);
		return error;
	}

	cpuid = riscv_hartid_to_cpuid(hartid);
	if (cpuid < 0) {
		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
		return cpuid;
	}

	if (cpuid != smp_processor_id())
		return 0;

	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
	if (child) {
		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
					"riscv,timer-cannot-wake-cpu");
		of_node_put(child);
	}

	return riscv_timer_init_common();
}

TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);

#ifdef CONFIG_ACPI
static int __init riscv_timer_acpi_init(struct acpi_table_header *table)
{
	struct acpi_table_rhct *rhct = (struct acpi_table_rhct *)table;

	riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU;

	return riscv_timer_init_common();
}

TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init);

#endif
Commit	Line	Data
62b01943 PD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2012 Regents of the University of California
	4	* Copyright (C) 2017 SiFive
2f12dbf1	5	*
4f9bbcef CH	6	* All RISC-V systems have a timer attached to every hart. These timers can
	7	* either be read from the "time" and "timeh" CSRs, and can use the SBI to
	8	* setup events, or directly accessed using MMIO registers.
62b01943	9	*/
9f7a8ff6 AP	10
	11	#define pr_fmt(fmt) "riscv-timer: " fmt
	12
21f4f924	13	#include <linux/acpi.h>
62b01943 PD	14	#include <linux/clocksource.h>
	15	#include <linux/clockchips.h>
	16	#include <linux/cpu.h>
	17	#include <linux/delay.h>
	18	#include <linux/irq.h>
033a65de	19	#include <linux/irqdomain.h>
3a9f66cb	20	#include <linux/module.h>
92e0d143	21	#include <linux/sched_clock.h>
4f9bbcef	22	#include <linux/io-64-nonatomic-lo-hi.h>
033a65de AP	23	#include <linux/interrupt.h>
033a65de AP	24	#include <linux/of_irq.h>
5d98446f	25	#include <linux/limits.h>
3a9f66cb	26	#include <clocksource/timer-riscv.h>
f99fb607	27	#include <asm/smp.h>
e72c4333	28	#include <asm/cpufeature.h>
62b01943	29	#include <asm/sbi.h>
2bc3fc87	30	#include <asm/timex.h>
4f9bbcef	31
9f7a8ff6	32	static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
8932a953	33	static bool riscv_timer_cannot_wake_cpu;
9f7a8ff6	34
5d98446f AP	35	static void riscv_clock_event_stop(void)
	36	{
	37	if (static_branch_likely(&riscv_sstc_available)) {
	38	csr_write(CSR_STIMECMP, ULONG_MAX);
	39	if (IS_ENABLED(CONFIG_32BIT))
	40	csr_write(CSR_STIMECMPH, ULONG_MAX);
	41	} else {
	42	sbi_set_timer(U64_MAX);
	43	}
	44	}
	45
62b01943 PD	46	static int riscv_clock_next_event(unsigned long delta,
	47	struct clock_event_device *ce)
	48	{
9f7a8ff6 AP	49	u64 next_tval = get_cycles64() + delta;
9f7a8ff6 AP	50
9f7a8ff6 AP	51	if (static_branch_likely(&riscv_sstc_available)) {
	52	#if defined(CONFIG_32BIT)
	53	csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
	54	csr_write(CSR_STIMECMPH, next_tval >> 32);
	55	#else
	56	csr_write(CSR_STIMECMP, next_tval);
	57	#endif
	58	} else
	59	sbi_set_timer(next_tval);
	60
62b01943 PD	61	return 0;
	62	}
	63
6a902b11 JY	64	static int riscv_clock_shutdown(struct clock_event_device *evt)
	65	{
	66	riscv_clock_event_stop();
	67	return 0;
	68	}
	69
033a65de	70	static unsigned int riscv_clock_event_irq;
62b01943 PD	71	static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
62b01943 PD	72	.name = "riscv_timer_clockevent",
d9f15a9d	73	.features = CLOCK_EVT_FEAT_ONESHOT,
62b01943 PD	74	.rating = 100,
62b01943 PD	75	.set_next_event = riscv_clock_next_event,
6a902b11	76	.set_state_shutdown = riscv_clock_shutdown,
62b01943 PD	77	};
	78
	79	/*
	80	* It is guaranteed that all the timers across all the harts are synchronized
	81	* within one tick of each other, so while this could technically go
	82	* backwards when hopping between CPUs, practically it won't happen.
	83	*/
	84	static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
	85	{
	86	return get_cycles64();
	87	}
	88
9d05c18e	89	static u64 notrace riscv_sched_clock(void)
92e0d143 AP	90	{
	91	return get_cycles64();
	92	}
	93
713203e3	94	static struct clocksource riscv_clocksource = {
62b01943	95	.name = "riscv_clocksource",
674402b0	96	.rating = 400,
32d0be01	97	.mask = CLOCKSOURCE_MASK(64),
62b01943 PD	98	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
62b01943 PD	99	.read = riscv_clocksource_rdtime,
3aff0403 LP	100	#if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
	101	.vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
	102	#else
	103	.vdso_clock_mode = VDSO_CLOCKMODE_NONE,
	104	#endif
62b01943 PD	105	};
	106
	107	static int riscv_timer_starting_cpu(unsigned int cpu)
	108	{
	109	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
	110
8248ca30 LFT	111	/* Clear timer interrupt */
	112	riscv_clock_event_stop();
	113
62b01943	114	ce->cpumask = cpumask_of(cpu);
033a65de	115	ce->irq = riscv_clock_event_irq;
8932a953 AP	116	if (riscv_timer_cannot_wake_cpu)
8932a953 AP	117	ce->features \|= CLOCK_EVT_FEAT_C3STOP;
60c46877 AP	118	if (static_branch_likely(&riscv_sstc_available))
60c46877 AP	119	ce->rating = 450;
d38e2e7b	120	clockevents_config_and_register(ce, riscv_timebase, 100, ULONG_MAX);
62b01943	121
033a65de AP	122	enable_percpu_irq(riscv_clock_event_irq,
033a65de AP	123	irq_get_trigger_type(riscv_clock_event_irq));
62b01943 PD	124	return 0;
	125	}
	126
	127	static int riscv_timer_dying_cpu(unsigned int cpu)
	128	{
70c93b02 NH	129	/*
	130	* Stop the timer when the cpu is going to be offline otherwise
	131	* the timer interrupt may be pending while performing power-down.
	132	*/
	133	riscv_clock_event_stop();
033a65de	134	disable_percpu_irq(riscv_clock_event_irq);
70c93b02	135
62b01943 PD	136	return 0;
	137	}
	138
3a9f66cb AP	139	void riscv_cs_get_mult_shift(u32 mult, u32 shift)
	140	{
	141	*mult = riscv_clocksource.mult;
	142	*shift = riscv_clocksource.shift;
	143	}
	144	EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
	145
62b01943	146	/* called directly from the low-level interrupt handler */
033a65de	147	static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
62b01943 PD	148	{
	149	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
	150
5d98446f	151	riscv_clock_event_stop();
62b01943	152	evdev->event_handler(evdev);
033a65de AP	153
033a65de AP	154	return IRQ_HANDLED;
62b01943 PD	155	}
62b01943 PD	156
cd12d206	157	static int __init riscv_timer_init_common(void)
62b01943	158	{
cd12d206	159	int error;
033a65de	160	struct irq_domain *domain;
cd12d206	161	struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
62b01943	162
cd12d206	163	domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
033a65de	164	if (!domain) {
cd12d206 S	165	pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
cd12d206 S	166	intc_fwnode);
033a65de AP	167	return -ENODEV;
	168	}
	169
	170	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
	171	if (!riscv_clock_event_irq) {
cd12d206	172	pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
033a65de AP	173	return -ENODEV;
	174	}
	175
713203e3	176	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
26478b2f	177	if (error) {
cd12d206	178	pr_err("RISCV timer registration failed [%d]\n", error);
26478b2f AP	179	return error;
26478b2f AP	180	}
62b01943	181
32d0be01	182	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
92e0d143	183
033a65de AP	184	error = request_percpu_irq(riscv_clock_event_irq,
	185	riscv_timer_interrupt,
	186	"riscv-timer", &riscv_clock_event);
	187	if (error) {
	188	pr_err("registering percpu irq failed [%d]\n", error);
	189	return error;
	190	}
	191
225b9596 ME	192	if (riscv_isa_extension_available(NULL, SSTC)) {
	193	pr_info("Timer interrupt in S-mode is available via sstc extension\n");
	194	static_branch_enable(&riscv_sstc_available);
	195	}
	196
62b01943 PD	197	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
	198	"clockevents/riscv/timer:starting",
	199	riscv_timer_starting_cpu, riscv_timer_dying_cpu);
	200	if (error)
26478b2f AP	201	pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
26478b2f AP	202	error);
9f7a8ff6	203
62b01943 PD	204	return error;
	205	}
	206
cd12d206 S	207	static int __init riscv_timer_init_dt(struct device_node *n)
	208	{
	209	int cpuid, error;
	210	unsigned long hartid;
	211	struct device_node *child;
	212
	213	error = riscv_of_processor_hartid(n, &hartid);
	214	if (error < 0) {
	215	pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
	216	n, hartid);
	217	return error;
	218	}
	219
	220	cpuid = riscv_hartid_to_cpuid(hartid);
	221	if (cpuid < 0) {
	222	pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
	223	return cpuid;
	224	}
	225
	226	if (cpuid != smp_processor_id())
	227	return 0;
	228
	229	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
	230	if (child) {
	231	riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
	232	"riscv,timer-cannot-wake-cpu");
	233	of_node_put(child);
	234	}
	235
	236	return riscv_timer_init_common();
	237	}
	238
62b01943	239	TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
21f4f924 S	240
	241	#ifdef CONFIG_ACPI
	242	static int __init riscv_timer_acpi_init(struct acpi_table_header *table)
	243	{
d7f546c7 S	244	struct acpi_table_rhct rhct = (struct acpi_table_rhct )table;
	245
	246	riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU;
	247
21f4f924 S	248	return riscv_timer_init_common();
	249	}
	250
	251	TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init);
	252
	253	#endif