[linux-block.git] / drivers / clocksource / timer-riscv.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2012 Regents of the University of California
 * Copyright (C) 2017 SiFive
 *
 * All RISC-V systems have a timer attached to every hart.  These timers can
 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
 * setup events, or directly accessed using MMIO registers.
 */
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/sched_clock.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <asm/smp.h>
#include <asm/sbi.h>
#include <asm/timex.h>

static int riscv_clock_next_event(unsigned long delta,
		struct clock_event_device *ce)
{
	csr_set(CSR_IE, IE_TIE);
	sbi_set_timer(get_cycles64() + delta);
	return 0;
}

static unsigned int riscv_clock_event_irq;
static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
	.name			= "riscv_timer_clockevent",
	.features		= CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 100,
	.set_next_event		= riscv_clock_next_event,
};

/*
 * It is guaranteed that all the timers across all the harts are synchronized
 * within one tick of each other, so while this could technically go
 * backwards when hopping between CPUs, practically it won't happen.
 */
static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
{
	return get_cycles64();
}

static u64 notrace riscv_sched_clock(void)
{
	return get_cycles64();
}

static struct clocksource riscv_clocksource = {
	.name		= "riscv_clocksource",
	.rating		= 300,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.read		= riscv_clocksource_rdtime,
};

static int riscv_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);

	ce->cpumask = cpumask_of(cpu);
	ce->irq = riscv_clock_event_irq;
	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);

	enable_percpu_irq(riscv_clock_event_irq,
			  irq_get_trigger_type(riscv_clock_event_irq));
	return 0;
}

static int riscv_timer_dying_cpu(unsigned int cpu)
{
	disable_percpu_irq(riscv_clock_event_irq);
	return 0;
}

/* called directly from the low-level interrupt handler */
static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);

	csr_clear(CSR_IE, IE_TIE);
	evdev->event_handler(evdev);

	return IRQ_HANDLED;
}

static int __init riscv_timer_init_dt(struct device_node *n)
{
	int cpuid, hartid, error;
	struct device_node *child;
	struct irq_domain *domain;

	hartid = riscv_of_processor_hartid(n);
	if (hartid < 0) {
		pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
			n, hartid);
		return hartid;
	}

	cpuid = riscv_hartid_to_cpuid(hartid);
	if (cpuid < 0) {
		pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
		return cpuid;
	}

	if (cpuid != smp_processor_id())
		return 0;

	domain = NULL;
	child = of_get_compatible_child(n, "riscv,cpu-intc");
	if (!child) {
		pr_err("Failed to find INTC node [%pOF]\n", n);
		return -ENODEV;
	}
	domain = irq_find_host(child);
	of_node_put(child);
	if (!domain) {
		pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
		return -ENODEV;
	}

	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
	if (!riscv_clock_event_irq) {
		pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
		return -ENODEV;
	}

	pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
	       __func__, cpuid, hartid);
	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
	if (error) {
		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
		       error, cpuid);
		return error;
	}

	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);

	error = request_percpu_irq(riscv_clock_event_irq,
				    riscv_timer_interrupt,
				    "riscv-timer", &riscv_clock_event);
	if (error) {
		pr_err("registering percpu irq failed [%d]\n", error);
		return error;
	}

	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
			 "clockevents/riscv/timer:starting",
			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
	if (error)
		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
		       error);
	return error;
}

TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
Commit	Line	Data
62b01943 PD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2012 Regents of the University of California
	4	* Copyright (C) 2017 SiFive
2f12dbf1	5	*
4f9bbcef CH	6	* All RISC-V systems have a timer attached to every hart. These timers can
	7	* either be read from the "time" and "timeh" CSRs, and can use the SBI to
	8	* setup events, or directly accessed using MMIO registers.
62b01943 PD	9	*/
	10	#include <linux/clocksource.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/cpu.h>
	13	#include <linux/delay.h>
	14	#include <linux/irq.h>
033a65de	15	#include <linux/irqdomain.h>
92e0d143	16	#include <linux/sched_clock.h>
4f9bbcef	17	#include <linux/io-64-nonatomic-lo-hi.h>
033a65de AP	18	#include <linux/interrupt.h>
033a65de AP	19	#include <linux/of_irq.h>
f99fb607	20	#include <asm/smp.h>
62b01943	21	#include <asm/sbi.h>
2bc3fc87	22	#include <asm/timex.h>
4f9bbcef	23
62b01943 PD	24	static int riscv_clock_next_event(unsigned long delta,
	25	struct clock_event_device *ce)
	26	{
a4c3733d	27	csr_set(CSR_IE, IE_TIE);
2bc3fc87	28	sbi_set_timer(get_cycles64() + delta);
62b01943 PD	29	return 0;
	30	}
	31
033a65de	32	static unsigned int riscv_clock_event_irq;
62b01943 PD	33	static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
	34	.name = "riscv_timer_clockevent",
	35	.features = CLOCK_EVT_FEAT_ONESHOT,
	36	.rating = 100,
	37	.set_next_event = riscv_clock_next_event,
	38	};
	39
	40	/*
	41	* It is guaranteed that all the timers across all the harts are synchronized
	42	* within one tick of each other, so while this could technically go
	43	* backwards when hopping between CPUs, practically it won't happen.
	44	*/
	45	static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
	46	{
	47	return get_cycles64();
	48	}
	49
9d05c18e	50	static u64 notrace riscv_sched_clock(void)
92e0d143 AP	51	{
	52	return get_cycles64();
	53	}
	54
713203e3	55	static struct clocksource riscv_clocksource = {
62b01943 PD	56	.name = "riscv_clocksource",
62b01943 PD	57	.rating = 300,
32d0be01	58	.mask = CLOCKSOURCE_MASK(64),
62b01943 PD	59	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	60	.read = riscv_clocksource_rdtime,
	61	};
	62
	63	static int riscv_timer_starting_cpu(unsigned int cpu)
	64	{
	65	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
	66
	67	ce->cpumask = cpumask_of(cpu);
033a65de	68	ce->irq = riscv_clock_event_irq;
62b01943 PD	69	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
62b01943 PD	70
033a65de AP	71	enable_percpu_irq(riscv_clock_event_irq,
033a65de AP	72	irq_get_trigger_type(riscv_clock_event_irq));
62b01943 PD	73	return 0;
	74	}
	75
	76	static int riscv_timer_dying_cpu(unsigned int cpu)
	77	{
033a65de	78	disable_percpu_irq(riscv_clock_event_irq);
62b01943 PD	79	return 0;
	80	}
	81
	82	/* called directly from the low-level interrupt handler */
033a65de	83	static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
62b01943 PD	84	{
	85	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
	86
a4c3733d	87	csr_clear(CSR_IE, IE_TIE);
62b01943	88	evdev->event_handler(evdev);
033a65de AP	89
033a65de AP	90	return IRQ_HANDLED;
62b01943 PD	91	}
	92
	93	static int __init riscv_timer_init_dt(struct device_node *n)
	94	{
f99fb607	95	int cpuid, hartid, error;
033a65de AP	96	struct device_node *child;
033a65de AP	97	struct irq_domain *domain;
62b01943	98
f99fb607	99	hartid = riscv_of_processor_hartid(n);
26478b2f AP	100	if (hartid < 0) {
	101	pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
	102	n, hartid);
	103	return hartid;
	104	}
	105
f99fb607	106	cpuid = riscv_hartid_to_cpuid(hartid);
26478b2f AP	107	if (cpuid < 0) {
	108	pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
	109	return cpuid;
	110	}
f99fb607 AP	111
f99fb607 AP	112	if (cpuid != smp_processor_id())
62b01943 PD	113	return 0;
62b01943 PD	114
033a65de AP	115	domain = NULL;
	116	child = of_get_compatible_child(n, "riscv,cpu-intc");
	117	if (!child) {
	118	pr_err("Failed to find INTC node [%pOF]\n", n);
	119	return -ENODEV;
	120	}
	121	domain = irq_find_host(child);
	122	of_node_put(child);
	123	if (!domain) {
	124	pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
	125	return -ENODEV;
	126	}
	127
	128	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
	129	if (!riscv_clock_event_irq) {
	130	pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
	131	return -ENODEV;
	132	}
	133
26478b2f AP	134	pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
26478b2f AP	135	__func__, cpuid, hartid);
713203e3	136	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
26478b2f AP	137	if (error) {
	138	pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
	139	error, cpuid);
	140	return error;
	141	}
62b01943	142
32d0be01	143	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
92e0d143	144
033a65de AP	145	error = request_percpu_irq(riscv_clock_event_irq,
	146	riscv_timer_interrupt,
	147	"riscv-timer", &riscv_clock_event);
	148	if (error) {
	149	pr_err("registering percpu irq failed [%d]\n", error);
	150	return error;
	151	}
	152
62b01943 PD	153	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
	154	"clockevents/riscv/timer:starting",
	155	riscv_timer_starting_cpu, riscv_timer_dying_cpu);
	156	if (error)
26478b2f AP	157	pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
26478b2f AP	158	error);
62b01943 PD	159	return error;
	160	}
	161
	162	TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);