[linux-2.6-block.git] / drivers / clocksource / timer-qcom.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <asm/delay.h>

#define TIMER_MATCH_VAL			0x0000
#define TIMER_COUNT_VAL			0x0004
#define TIMER_ENABLE			0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)
#define TIMER_ENABLE_EN			BIT(0)
#define TIMER_CLEAR			0x000C
#define DGT_CLK_CTL			0x10
#define DGT_CLK_CTL_DIV_4		0x3
#define TIMER_STS_GPT0_CLR_PEND		BIT(10)

#define GPT_HZ 32768

static void __iomem *event_base;
static void __iomem *sts_base;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	/* Stop the timer tick */
	if (clockevent_state_oneshot(evt)) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	ctrl &= ~TIMER_ENABLE_EN;
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);

	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);

	if (sts_base)
		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
			cpu_relax();

	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

static int msm_timer_shutdown(struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	return 0;
}

static struct clock_event_device __percpu *msm_evt;

static void __iomem *source_base;

static notrace u64 msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int msm_timer_irq;
static int msm_timer_has_ppi;

static int msm_local_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
	int err;

	evt->irq = msm_timer_irq;
	evt->name = "msm_timer";
	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 200;
	evt->set_state_shutdown = msm_timer_shutdown;
	evt->set_state_oneshot = msm_timer_shutdown;
	evt->tick_resume = msm_timer_shutdown;
	evt->set_next_event = msm_timer_set_next_event;
	evt->cpumask = cpumask_of(cpu);

	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);

	if (msm_timer_has_ppi) {
		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	} else {
		err = request_irq(evt->irq, msm_timer_interrupt,
				IRQF_TIMER | IRQF_NOBALANCING |
				IRQF_TRIGGER_RISING, "gp_timer", evt);
		if (err)
			pr_err("request_irq failed\n");
	}

	return 0;
}

static int msm_local_timer_dying_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);

	evt->set_state_shutdown(evt);
	disable_percpu_irq(evt->irq);
	return 0;
}

static u64 notrace msm_sched_clock_read(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static unsigned long msm_read_current_timer(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static struct delay_timer msm_delay_timer = {
	.read_current_timer = msm_read_current_timer,
};

static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
{
	struct clocksource *cs = &msm_clocksource;
	int res = 0;

	msm_timer_irq = irq;
	msm_timer_has_ppi = percpu;

	msm_evt = alloc_percpu(struct clock_event_device);
	if (!msm_evt) {
		pr_err("memory allocation failed for clockevents\n");
		goto err;
	}

	if (percpu)
		res = request_percpu_irq(irq, msm_timer_interrupt,
					 "gp_timer", msm_evt);

	if (res) {
		pr_err("request_percpu_irq failed\n");
	} else {
		/* Install and invoke hotplug callbacks */
		res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING,
					"clockevents/qcom/timer:starting",
					msm_local_timer_starting_cpu,
					msm_local_timer_dying_cpu);
		if (res) {
			free_percpu_irq(irq, msm_evt);
			goto err;
		}
	}

err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
	msm_delay_timer.freq = dgt_hz;
	register_current_timer_delay(&msm_delay_timer);

	return res;
}

static int __init msm_dt_timer_init(struct device_node *np)
{
	u32 freq;
	int irq, ret;
	struct resource res;
	u32 percpu_offset;
	void __iomem *base;
	void __iomem *cpu0_base;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to map event base\n");
		return -ENXIO;
	}

	/* We use GPT0 for the clockevent */
	irq = irq_of_parse_and_map(np, 1);
	if (irq <= 0) {
		pr_err("Can't get irq\n");
		return -EINVAL;
	}

	/* We use CPU0's DGT for the clocksource */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	ret = of_address_to_resource(np, 0, &res);
	if (ret) {
		pr_err("Failed to parse DGT resource\n");
		return ret;
	}

	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!cpu0_base) {
		pr_err("Failed to map source base\n");
		return -EINVAL;
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
		return -EINVAL;
	}

	event_base = base + 0x4;
	sts_base = base + 0x88;
	source_base = cpu0_base + 0x24;
	freq /= 4;
	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);

	return msm_timer_init(freq, 32, irq, !!percpu_offset);
}
TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
dd15ab81	2	/*
3e4ea372 AH	3	*
3e4ea372 AH	4	* Copyright (C) 2007 Google, Inc.
3f8e8cee	5	* Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
3e4ea372 AH	6	*/
3e4ea372 AH	7
4a184075 SB	8	#include <linux/clocksource.h>
4a184075 SB	9	#include <linux/clockchips.h>
4d70c59b	10	#include <linux/cpu.h>
3e4ea372	11	#include <linux/init.h>
3e4ea372 AH	12	#include <linux/interrupt.h>
3e4ea372 AH	13	#include <linux/irq.h>
fced80c7	14	#include <linux/io.h>
6e332163 SB	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
38ff87f7	18	#include <linux/sched_clock.h>
3e4ea372	19
013be5ad SB	20	#include <asm/delay.h>
013be5ad SB	21
e25e3d1f SB	22	#define TIMER_MATCH_VAL 0x0000
	23	#define TIMER_COUNT_VAL 0x0004
	24	#define TIMER_ENABLE 0x0008
	25	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
	26	#define TIMER_ENABLE_EN BIT(0)
	27	#define TIMER_CLEAR 0x000C
	28	#define DGT_CLK_CTL 0x10
	29	#define DGT_CLK_CTL_DIV_4 0x3
	30	#define TIMER_STS_GPT0_CLR_PEND BIT(10)
3e4ea372 AH	31
3e4ea372 AH	32	#define GPT_HZ 32768
672039f0	33
2a00c106	34	static void __iomem *event_base;
e25e3d1f	35	static void __iomem *sts_base;
a850c3f6	36
3e4ea372 AH	37	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	38	{
4d70c59b	39	struct clock_event_device *evt = dev_id;
a850c3f6	40	/* Stop the timer tick */
736b2df2	41	if (clockevent_state_oneshot(evt)) {
2a00c106	42	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	43	ctrl &= ~TIMER_ENABLE_EN;
2a00c106	44	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
a850c3f6	45	}
3e4ea372 AH	46	evt->event_handler(evt);
	47	return IRQ_HANDLED;
	48	}
	49
3e4ea372 AH	50	static int msm_timer_set_next_event(unsigned long cycles,
	51	struct clock_event_device *evt)
	52	{
2a00c106	53	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
3e4ea372	54
4080d2d1 SB	55	ctrl &= ~TIMER_ENABLE_EN;
	56	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	57
	58	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
2a00c106	59	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
e25e3d1f SB	60
	61	if (sts_base)
	62	while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
	63	cpu_relax();
	64
2a00c106	65	writel_relaxed(ctrl \| TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
3e4ea372 AH	66	return 0;
	67	}
	68
736b2df2	69	static int msm_timer_shutdown(struct clock_event_device *evt)
3e4ea372	70	{
a850c3f6 SB	71	u32 ctrl;
a850c3f6 SB	72
2a00c106	73	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	74	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
2a00c106	75	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
736b2df2	76	return 0;
3e4ea372 AH	77	}
3e4ea372 AH	78
4d70c59b	79	static struct clock_event_device __percpu *msm_evt;
2a00c106 SB	80
	81	static void __iomem *source_base;
	82
a5a1d1c2	83	static notrace u64 msm_read_timer_count(struct clocksource *cs)
2081a6b5 SB	84	{
	85	return readl_relaxed(source_base + TIMER_COUNT_VAL);
	86	}
	87
2a00c106 SB	88	static struct clocksource msm_clocksource = {
	89	.name = "dg_timer",
	90	.rating = 300,
	91	.read = msm_read_timer_count,
2081a6b5	92	.mask = CLOCKSOURCE_MASK(32),
2a00c106	93	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	94	};
3e4ea372 AH	95
4d70c59b SB	96	static int msm_timer_irq;
	97	static int msm_timer_has_ppi;
	98
b0404165	99	static int msm_local_timer_starting_cpu(unsigned int cpu)
5ca709c1	100	{
b0404165	101	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
4d70c59b SB	102	int err;
	103
	104	evt->irq = msm_timer_irq;
	105	evt->name = "msm_timer";
	106	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	107	evt->rating = 200;
736b2df2 VK	108	evt->set_state_shutdown = msm_timer_shutdown;
	109	evt->set_state_oneshot = msm_timer_shutdown;
	110	evt->tick_resume = msm_timer_shutdown;
5ca709c1	111	evt->set_next_event = msm_timer_set_next_event;
4d70c59b SB	112	evt->cpumask = cpumask_of(cpu);
	113
	114	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
	115
	116	if (msm_timer_has_ppi) {
	117	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	118	} else {
	119	err = request_irq(evt->irq, msm_timer_interrupt,
	120	IRQF_TIMER \| IRQF_NOBALANCING \|
	121	IRQF_TRIGGER_RISING, "gp_timer", evt);
	122	if (err)
	123	pr_err("request_irq failed\n");
	124	}
5ca709c1	125
5ca709c1 MZ	126	return 0;
	127	}
	128
b0404165	129	static int msm_local_timer_dying_cpu(unsigned int cpu)
5ca709c1	130	{
b0404165 RC	131	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
b0404165 RC	132
736b2df2	133	evt->set_state_shutdown(evt);
5ca709c1	134	disable_percpu_irq(evt->irq);
b0404165	135	return 0;
5ca709c1 MZ	136	}
5ca709c1 MZ	137
6aa16a26	138	static u64 notrace msm_sched_clock_read(void)
f8e56c42 SB	139	{
	140	return msm_clocksource.read(&msm_clocksource);
	141	}
	142
013be5ad SB	143	static unsigned long msm_read_current_timer(void)
	144	{
	145	return msm_clocksource.read(&msm_clocksource);
	146	}
	147
	148	static struct delay_timer msm_delay_timer = {
	149	.read_current_timer = msm_read_current_timer,
	150	};
	151
ab51189c	152	static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
4312a7ef	153	bool percpu)
3e4ea372	154	{
2a00c106	155	struct clocksource *cs = &msm_clocksource;
4d70c59b SB	156	int res = 0;
	157
	158	msm_timer_irq = irq;
	159	msm_timer_has_ppi = percpu;
	160
	161	msm_evt = alloc_percpu(struct clock_event_device);
	162	if (!msm_evt) {
	163	pr_err("memory allocation failed for clockevents\n");
	164	goto err;
	165	}
3e4ea372	166
4d70c59b SB	167	if (percpu)
	168	res = request_percpu_irq(irq, msm_timer_interrupt,
	169	"gp_timer", msm_evt);
dd15ab81	170
4d70c59b SB	171	if (res) {
	172	pr_err("request_percpu_irq failed\n");
	173	} else {
b0404165 RC	174	/* Install and invoke hotplug callbacks */
b0404165 RC	175	res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING,
73c1b41e	176	"clockevents/qcom/timer:starting",
b0404165 RC	177	msm_local_timer_starting_cpu,
b0404165 RC	178	msm_local_timer_dying_cpu);
4d70c59b SB	179	if (res) {
4d70c59b SB	180	free_percpu_irq(irq, msm_evt);
dd15ab81	181	goto err;
28af690a	182	}
3e4ea372	183	}
dd15ab81	184
dd15ab81	185	err:
2a00c106	186	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
2081a6b5	187	res = clocksource_register_hz(cs, dgt_hz);
dd15ab81	188	if (res)
2a00c106	189	pr_err("clocksource_register failed\n");
6aa16a26	190	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
013be5ad SB	191	msm_delay_timer.freq = dgt_hz;
013be5ad SB	192	register_current_timer_delay(&msm_delay_timer);
ab51189c DL	193
ab51189c DL	194	return res;
3e4ea372 AH	195	}
3e4ea372 AH	196
ab51189c	197	static int __init msm_dt_timer_init(struct device_node *np)
6e332163	198	{
6e332163	199	u32 freq;
ab51189c	200	int irq, ret;
6e332163 SB	201	struct resource res;
6e332163 SB	202	u32 percpu_offset;
eebdb0c1 SB	203	void __iomem *base;
eebdb0c1 SB	204	void __iomem *cpu0_base;
6e332163	205
eebdb0c1 SB	206	base = of_iomap(np, 0);
eebdb0c1 SB	207	if (!base) {
6e332163	208	pr_err("Failed to map event base\n");
ab51189c	209	return -ENXIO;
6e332163 SB	210	}
6e332163 SB	211
eebdb0c1 SB	212	/* We use GPT0 for the clockevent */
eebdb0c1 SB	213	irq = irq_of_parse_and_map(np, 1);
6e332163 SB	214	if (irq <= 0) {
6e332163 SB	215	pr_err("Can't get irq\n");
ab51189c	216	return -EINVAL;
6e332163	217	}
6e332163	218
eebdb0c1	219	/* We use CPU0's DGT for the clocksource */
6e332163 SB	220	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	221	percpu_offset = 0;
	222
ab51189c DL	223	ret = of_address_to_resource(np, 0, &res);
ab51189c DL	224	if (ret) {
6e332163	225	pr_err("Failed to parse DGT resource\n");
ab51189c	226	return ret;
6e332163 SB	227	}
6e332163 SB	228
eebdb0c1 SB	229	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
eebdb0c1 SB	230	if (!cpu0_base) {
6e332163	231	pr_err("Failed to map source base\n");
ab51189c	232	return -EINVAL;
6e332163 SB	233	}
6e332163 SB	234
6e332163 SB	235	if (of_property_read_u32(np, "clock-frequency", &freq)) {
6e332163 SB	236	pr_err("Unknown frequency\n");
ab51189c	237	return -EINVAL;
6e332163	238	}
6e332163	239
eebdb0c1	240	event_base = base + 0x4;
e25e3d1f	241	sts_base = base + 0x88;
eebdb0c1 SB	242	source_base = cpu0_base + 0x24;
	243	freq /= 4;
	244	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
	245
ab51189c	246	return msm_timer_init(freq, 32, irq, !!percpu_offset);
6e332163	247	}
17273395 DL	248	TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
17273395 DL	249	TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);