[linux-2.6-block.git] / drivers / clocksource / timer-prima2.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * System timer for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/sched_clock.h>

#define PRIMA2_CLOCK_FREQ 1000000

#define SIRFSOC_TIMER_COUNTER_LO	0x0000
#define SIRFSOC_TIMER_COUNTER_HI	0x0004
#define SIRFSOC_TIMER_MATCH_0		0x0008
#define SIRFSOC_TIMER_MATCH_1		0x000C
#define SIRFSOC_TIMER_MATCH_2		0x0010
#define SIRFSOC_TIMER_MATCH_3		0x0014
#define SIRFSOC_TIMER_MATCH_4		0x0018
#define SIRFSOC_TIMER_MATCH_5		0x001C
#define SIRFSOC_TIMER_STATUS		0x0020
#define SIRFSOC_TIMER_INT_EN		0x0024
#define SIRFSOC_TIMER_WATCHDOG_EN	0x0028
#define SIRFSOC_TIMER_DIV		0x002C
#define SIRFSOC_TIMER_LATCH		0x0030
#define SIRFSOC_TIMER_LATCHED_LO	0x0034
#define SIRFSOC_TIMER_LATCHED_HI	0x0038

#define SIRFSOC_TIMER_WDT_INDEX		5

#define SIRFSOC_TIMER_LATCH_BIT	 BIT(0)

#define SIRFSOC_TIMER_REG_CNT 11

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
	SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
	SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
	SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
};

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

static void __iomem *sirfsoc_timer_base;

/* timer0 interrupt handler */
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;

	WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
		BIT(0)));

	/* clear timer0 interrupt */
	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

/* read 64-bit timer counter */
static u64 notrace sirfsoc_timer_read(struct clocksource *cs)
{
	u64 cycles;

	/* latch the 64-bit timer counter */
	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
	cycles = (cycles << 32) |
		readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);

	return cycles;
}

static int sirfsoc_timer_set_next_event(unsigned long delta,
	struct clock_event_device *ce)
{
	unsigned long now, next;

	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	next = now + delta;
	writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);

	return next - now > delta ? -ETIME : 0;
}

static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
{
	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);

	writel_relaxed(val & ~BIT(0),
		       sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	return 0;
}

static int sirfsoc_timer_set_oneshot(struct clock_event_device *evt)
{
	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);

	writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	return 0;
}

static void sirfsoc_clocksource_suspend(struct clocksource *cs)
{
	int i;

	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
		sirfsoc_timer_reg_val[i] =
			readl_relaxed(sirfsoc_timer_base +
				sirfsoc_timer_reg_list[i]);
}

static void sirfsoc_clocksource_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
		writel_relaxed(sirfsoc_timer_reg_val[i],
			sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
		sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
		sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
}

static struct clock_event_device sirfsoc_clockevent = {
	.name = "sirfsoc_clockevent",
	.rating = 200,
	.features = CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown = sirfsoc_timer_shutdown,
	.set_state_oneshot = sirfsoc_timer_set_oneshot,
	.set_next_event = sirfsoc_timer_set_next_event,
};

static struct clocksource sirfsoc_clocksource = {
	.name = "sirfsoc_clocksource",
	.rating = 200,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.read = sirfsoc_timer_read,
	.suspend = sirfsoc_clocksource_suspend,
	.resume = sirfsoc_clocksource_resume,
};

/* Overwrite weak default sched_clock with more precise one */
static u64 notrace sirfsoc_read_sched_clock(void)
{
	return sirfsoc_timer_read(NULL);
}

static void __init sirfsoc_clockevent_init(void)
{
	sirfsoc_clockevent.cpumask = cpumask_of(0);
	clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
					2, -2);
}

/* initialize the kernel jiffy timer source */
static int __init sirfsoc_prima2_timer_init(struct device_node *np)
{
	unsigned long rate;
	unsigned int irq;
	struct clk *clk;
	int ret;

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("Failed to enable clock\n");
		return ret;
	}

	rate = clk_get_rate(clk);

	if (rate < PRIMA2_CLOCK_FREQ || rate % PRIMA2_CLOCK_FREQ) {
		pr_err("Invalid clock rate\n");
		return -EINVAL;
	}

	sirfsoc_timer_base = of_iomap(np, 0);
	if (!sirfsoc_timer_base) {
		pr_err("unable to map timer cpu registers\n");
		return -ENXIO;
	}

	irq = irq_of_parse_and_map(np, 0);

	writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
		sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);

	ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
	if (ret) {
		pr_err("Failed to register clocksource\n");
		return ret;
	}

	sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);

	ret = request_irq(irq, sirfsoc_timer_interrupt, IRQF_TIMER,
			  "sirfsoc_timer0", &sirfsoc_clockevent);
	if (ret) {
		pr_err("Failed to setup irq\n");
		return ret;
	}

	sirfsoc_clockevent_init();

	return 0;
}
TIMER_OF_DECLARE(sirfsoc_prima2_timer,
	"sirf,prima2-tick", sirfsoc_prima2_timer_init);
Commit	Line	Data
a636cd6c	1	// SPDX-License-Identifier: GPL-2.0-or-later
02c981c0 BD	2	/*
	3	* System timer for CSR SiRFprimaII
	4	*
	5	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
02c981c0 BD	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/clockchips.h>
	11	#include <linux/clocksource.h>
	12	#include <linux/bitops.h>
	13	#include <linux/irq.h>
	14	#include <linux/clk.h>
	15	#include <linux/err.h>
	16	#include <linux/slab.h>
	17	#include <linux/of.h>
67d71344	18	#include <linux/of_irq.h>
02c981c0	19	#include <linux/of_address.h>
38ff87f7	20	#include <linux/sched_clock.h>
02c981c0	21
980c51ab UKK	22	#define PRIMA2_CLOCK_FREQ 1000000
980c51ab UKK	23
02c981c0 BD	24	#define SIRFSOC_TIMER_COUNTER_LO 0x0000
	25	#define SIRFSOC_TIMER_COUNTER_HI 0x0004
	26	#define SIRFSOC_TIMER_MATCH_0 0x0008
	27	#define SIRFSOC_TIMER_MATCH_1 0x000C
	28	#define SIRFSOC_TIMER_MATCH_2 0x0010
	29	#define SIRFSOC_TIMER_MATCH_3 0x0014
	30	#define SIRFSOC_TIMER_MATCH_4 0x0018
	31	#define SIRFSOC_TIMER_MATCH_5 0x001C
	32	#define SIRFSOC_TIMER_STATUS 0x0020
	33	#define SIRFSOC_TIMER_INT_EN 0x0024
	34	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
	35	#define SIRFSOC_TIMER_DIV 0x002C
	36	#define SIRFSOC_TIMER_LATCH 0x0030
	37	#define SIRFSOC_TIMER_LATCHED_LO 0x0034
	38	#define SIRFSOC_TIMER_LATCHED_HI 0x0038
	39
	40	#define SIRFSOC_TIMER_WDT_INDEX 5
	41
	42	#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
	43
e5598a85 BS	44	#define SIRFSOC_TIMER_REG_CNT 11
	45
	46	static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	47	SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
	48	SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
	49	SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
	50	SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
	51	};
	52
	53	static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
	54
02c981c0	55	static void __iomem *sirfsoc_timer_base;
02c981c0 BD	56
	57	/* timer0 interrupt handler */
	58	static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
	59	{
	60	struct clock_event_device *ce = dev_id;
	61
4c1ad709 BS	62	WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
4c1ad709 BS	63	BIT(0)));
02c981c0 BD	64
	65	/* clear timer0 interrupt */
	66	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
	67
	68	ce->event_handler(ce);
	69
	70	return IRQ_HANDLED;
	71	}
	72
	73	/* read 64-bit timer counter */
a5a1d1c2	74	static u64 notrace sirfsoc_timer_read(struct clocksource *cs)
02c981c0 BD	75	{
	76	u64 cycles;
	77
	78	/* latch the 64-bit timer counter */
4c1ad709 BS	79	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	80	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0	81	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
4c1ad709 BS	82	cycles = (cycles << 32) \|
4c1ad709 BS	83	readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
02c981c0 BD	84
	85	return cycles;
	86	}
	87
	88	static int sirfsoc_timer_set_next_event(unsigned long delta,
	89	struct clock_event_device *ce)
	90	{
	91	unsigned long now, next;
	92
4c1ad709 BS	93	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	94	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0 BD	95	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	96	next = now + delta;
	97	writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
4c1ad709 BS	98	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	99	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0 BD	100	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	101
	102	return next - now > delta ? -ETIME : 0;
	103	}
	104
53cba064	105	static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
02c981c0 BD	106	{
02c981c0 BD	107	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
53cba064 VK	108
	109	writel_relaxed(val & ~BIT(0),
	110	sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	111	return 0;
	112	}
	113
	114	static int sirfsoc_timer_set_oneshot(struct clock_event_device *evt)
	115	{
	116	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	117
	118	writel_relaxed(val \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	119	return 0;
02c981c0 BD	120	}
02c981c0 BD	121
e5598a85 BS	122	static void sirfsoc_clocksource_suspend(struct clocksource *cs)
	123	{
	124	int i;
	125
4c1ad709 BS	126	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	127	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
e5598a85 BS	128
e5598a85 BS	129	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
4c1ad709 BS	130	sirfsoc_timer_reg_val[i] =
	131	readl_relaxed(sirfsoc_timer_base +
	132	sirfsoc_timer_reg_list[i]);
e5598a85 BS	133	}
	134
	135	static void sirfsoc_clocksource_resume(struct clocksource *cs)
	136	{
	137	int i;
	138
debeaf6c	139	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
4c1ad709 BS	140	writel_relaxed(sirfsoc_timer_reg_val[i],
4c1ad709 BS	141	sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
e5598a85	142
4c1ad709 BS	143	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
	144	sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	145	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
	146	sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
e5598a85 BS	147	}
e5598a85 BS	148
02c981c0 BD	149	static struct clock_event_device sirfsoc_clockevent = {
	150	.name = "sirfsoc_clockevent",
	151	.rating = 200,
	152	.features = CLOCK_EVT_FEAT_ONESHOT,
53cba064 VK	153	.set_state_shutdown = sirfsoc_timer_shutdown,
53cba064 VK	154	.set_state_oneshot = sirfsoc_timer_set_oneshot,
02c981c0 BD	155	.set_next_event = sirfsoc_timer_set_next_event,
	156	};
	157
	158	static struct clocksource sirfsoc_clocksource = {
	159	.name = "sirfsoc_clocksource",
	160	.rating = 200,
	161	.mask = CLOCKSOURCE_MASK(64),
	162	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	163	.read = sirfsoc_timer_read,
e5598a85 BS	164	.suspend = sirfsoc_clocksource_suspend,
e5598a85 BS	165	.resume = sirfsoc_clocksource_resume,
02c981c0 BD	166	};
02c981c0 BD	167
02c981c0	168	/* Overwrite weak default sched_clock with more precise one */
130e6b25	169	static u64 notrace sirfsoc_read_sched_clock(void)
02c981c0	170	{
130e6b25	171	return sirfsoc_timer_read(NULL);
02c981c0 BD	172	}
	173
	174	static void __init sirfsoc_clockevent_init(void)
	175	{
02c981c0	176	sirfsoc_clockevent.cpumask = cpumask_of(0);
980c51ab	177	clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
838a2ae8	178	2, -2);
02c981c0 BD	179	}
	180
	181	/* initialize the kernel jiffy timer source */
de23484d	182	static int __init sirfsoc_prima2_timer_init(struct device_node *np)
02c981c0 BD	183	{
02c981c0 BD	184	unsigned long rate;
cc2550b4	185	unsigned int irq;
198678b0	186	struct clk *clk;
de23484d	187	int ret;
198678b0	188
c7cff54d	189	clk = of_clk_get(np, 0);
de23484d	190	if (IS_ERR(clk)) {
ac9ce6d1	191	pr_err("Failed to get clock\n");
de23484d DL	192	return PTR_ERR(clk);
de23484d DL	193	}
38941522	194
de23484d DL	195	ret = clk_prepare_enable(clk);
de23484d DL	196	if (ret) {
ac9ce6d1	197	pr_err("Failed to enable clock\n");
de23484d DL	198	return ret;
de23484d DL	199	}
38941522	200
02c981c0 BD	201	rate = clk_get_rate(clk);
02c981c0 BD	202
de23484d	203	if (rate < PRIMA2_CLOCK_FREQ \|\| rate % PRIMA2_CLOCK_FREQ) {
ac9ce6d1	204	pr_err("Invalid clock rate\n");
de23484d DL	205	return -EINVAL;
de23484d DL	206	}
02c981c0	207
275786b7	208	sirfsoc_timer_base = of_iomap(np, 0);
de23484d DL	209	if (!sirfsoc_timer_base) {
	210	pr_err("unable to map timer cpu registers\n");
	211	return -ENXIO;
	212	}
275786b7	213
cc2550b4	214	irq = irq_of_parse_and_map(np, 0);
bc8d849d	215
980c51ab	216	writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
4c1ad709	217	sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
02c981c0 BD	218	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	219	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
	220	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
	221
de23484d DL	222	ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
de23484d DL	223	if (ret) {
ac9ce6d1	224	pr_err("Failed to register clocksource\n");
de23484d DL	225	return ret;
de23484d DL	226	}
02c981c0	227
980c51ab	228	sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
bc8d849d	229
cc2550b4	230	ret = request_irq(irq, sirfsoc_timer_interrupt, IRQF_TIMER,
cc2550b4	231	"sirfsoc_timer0", &sirfsoc_clockevent);
de23484d	232	if (ret) {
ac9ce6d1	233	pr_err("Failed to setup irq\n");
de23484d DL	234	return ret;
de23484d DL	235	}
02c981c0 BD	236
02c981c0 BD	237	sirfsoc_clockevent_init();
de23484d DL	238
de23484d DL	239	return 0;
02c981c0	240	}
17273395	241	TIMER_OF_DECLARE(sirfsoc_prima2_timer,
4c1ad709	242	"sirf,prima2-tick", sirfsoc_prima2_timer_init);