[linux-2.6-block.git] / drivers / clocksource / timer-pistachio.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Pistachio clocksource based on general-purpose timers
 *
 * Copyright (C) 2015 Imagination Technologies
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/sched_clock.h>
#include <linux/time.h>

/* Top level reg */
#define CR_TIMER_CTRL_CFG		0x00
#define TIMER_ME_GLOBAL			BIT(0)
#define CR_TIMER_REV			0x10

/* Timer specific registers */
#define TIMER_CFG			0x20
#define TIMER_ME_LOCAL			BIT(0)
#define TIMER_RELOAD_VALUE		0x24
#define TIMER_CURRENT_VALUE		0x28
#define TIMER_CURRENT_OVERFLOW_VALUE	0x2C
#define TIMER_IRQ_STATUS		0x30
#define TIMER_IRQ_CLEAR			0x34
#define TIMER_IRQ_MASK			0x38

#define PERIP_TIMER_CONTROL		0x90

/* Timer specific configuration Values */
#define RELOAD_VALUE			0xffffffff

struct pistachio_clocksource {
	void __iomem *base;
	raw_spinlock_t lock;
	struct clocksource cs;
};

static struct pistachio_clocksource pcs_gpt;

#define to_pistachio_clocksource(cs)	\
	container_of(cs, struct pistachio_clocksource, cs)

static inline u32 gpt_readl(void __iomem *base, u32 offset, u32 gpt_id)
{
	return readl(base + 0x20 * gpt_id + offset);
}

static inline void gpt_writel(void __iomem *base, u32 value, u32 offset,
		u32 gpt_id)
{
	writel(value, base + 0x20 * gpt_id + offset);
}

static u64 notrace
pistachio_clocksource_read_cycles(struct clocksource *cs)
{
	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
	__maybe_unused u32 overflow;
	u32 counter;
	unsigned long flags;

	/*
	 * The counter value is only refreshed after the overflow value is read.
	 * And they must be read in strict order, hence raw spin lock added.
	 */

	raw_spin_lock_irqsave(&pcs->lock, flags);
	overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0);
	counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0);
	raw_spin_unlock_irqrestore(&pcs->lock, flags);

	return (u64)~counter;
}

static u64 notrace pistachio_read_sched_clock(void)
{
	return pistachio_clocksource_read_cycles(&pcs_gpt.cs);
}

static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx,
			int enable)
{
	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
	u32 val;

	val = gpt_readl(pcs->base, TIMER_CFG, timeridx);
	if (enable)
		val |= TIMER_ME_LOCAL;
	else
		val &= ~TIMER_ME_LOCAL;

	gpt_writel(pcs->base, val, TIMER_CFG, timeridx);
}

static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx)
{
	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);

	/* Disable GPT local before loading reload value */
	pistachio_clksrc_set_mode(cs, timeridx, false);
	gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx);
	pistachio_clksrc_set_mode(cs, timeridx, true);
}

static void pistachio_clksrc_disable(struct clocksource *cs, int timeridx)
{
	/* Disable GPT local */
	pistachio_clksrc_set_mode(cs, timeridx, false);
}

static int pistachio_clocksource_enable(struct clocksource *cs)
{
	pistachio_clksrc_enable(cs, 0);
	return 0;
}

static void pistachio_clocksource_disable(struct clocksource *cs)
{
	pistachio_clksrc_disable(cs, 0);
}

/* Desirable clock source for pistachio platform */
static struct pistachio_clocksource pcs_gpt = {
	.cs =	{
		.name		= "gptimer",
		.rating		= 300,
		.enable		= pistachio_clocksource_enable,
		.disable	= pistachio_clocksource_disable,
		.read		= pistachio_clocksource_read_cycles,
		.mask		= CLOCKSOURCE_MASK(32),
		.flags		= CLOCK_SOURCE_IS_CONTINUOUS |
				  CLOCK_SOURCE_SUSPEND_NONSTOP,
		},
};

static int __init pistachio_clksrc_of_init(struct device_node *node)
{
	struct clk *sys_clk, *fast_clk;
	struct regmap *periph_regs;
	unsigned long rate;
	int ret;

	pcs_gpt.base = of_iomap(node, 0);
	if (!pcs_gpt.base) {
		pr_err("cannot iomap\n");
		return -ENXIO;
	}

	periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
	if (IS_ERR(periph_regs)) {
		pr_err("cannot get peripheral regmap (%ld)\n",
		       PTR_ERR(periph_regs));
		return PTR_ERR(periph_regs);
	}

	/* Switch to using the fast counter clock */
	ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
				 0xf, 0x0);
	if (ret)
		return ret;

	sys_clk = of_clk_get_by_name(node, "sys");
	if (IS_ERR(sys_clk)) {
		pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
		return PTR_ERR(sys_clk);
	}

	fast_clk = of_clk_get_by_name(node, "fast");
	if (IS_ERR(fast_clk)) {
		pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
		return PTR_ERR(fast_clk);
	}

	ret = clk_prepare_enable(sys_clk);
	if (ret < 0) {
		pr_err("failed to enable clock (%d)\n", ret);
		return ret;
	}

	ret = clk_prepare_enable(fast_clk);
	if (ret < 0) {
		pr_err("failed to enable clock (%d)\n", ret);
		clk_disable_unprepare(sys_clk);
		return ret;
	}

	rate = clk_get_rate(fast_clk);

	/* Disable irq's for clocksource usage */
	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0);
	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1);
	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2);
	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3);

	/* Enable timer block */
	writel(TIMER_ME_GLOBAL, pcs_gpt.base);

	raw_spin_lock_init(&pcs_gpt.lock);
	sched_clock_register(pistachio_read_sched_clock, 32, rate);
	return clocksource_register_hz(&pcs_gpt.cs, rate);
}
TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
		       pistachio_clksrc_of_init);
Commit	Line	Data
6bd86437	1	// SPDX-License-Identifier: GPL-2.0
84583983 EG	2	/*
	3	* Pistachio clocksource based on general-purpose timers
	4	*
	5	* Copyright (C) 2015 Imagination Technologies
84583983 EG	6	*/
	7
	8	#define pr_fmt(fmt) "%s: " fmt, __func__
	9
	10	#include <linux/clk.h>
	11	#include <linux/clocksource.h>
	12	#include <linux/clockchips.h>
	13	#include <linux/delay.h>
	14	#include <linux/err.h>
	15	#include <linux/init.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/mfd/syscon.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/regmap.h>
	22	#include <linux/sched_clock.h>
	23	#include <linux/time.h>
	24
	25	/* Top level reg */
	26	#define CR_TIMER_CTRL_CFG 0x00
	27	#define TIMER_ME_GLOBAL BIT(0)
	28	#define CR_TIMER_REV 0x10
	29
	30	/* Timer specific registers */
	31	#define TIMER_CFG 0x20
	32	#define TIMER_ME_LOCAL BIT(0)
	33	#define TIMER_RELOAD_VALUE 0x24
	34	#define TIMER_CURRENT_VALUE 0x28
	35	#define TIMER_CURRENT_OVERFLOW_VALUE 0x2C
	36	#define TIMER_IRQ_STATUS 0x30
	37	#define TIMER_IRQ_CLEAR 0x34
	38	#define TIMER_IRQ_MASK 0x38
	39
	40	#define PERIP_TIMER_CONTROL 0x90
	41
	42	/* Timer specific configuration Values */
	43	#define RELOAD_VALUE 0xffffffff
	44
	45	struct pistachio_clocksource {
	46	void __iomem *base;
	47	raw_spinlock_t lock;
	48	struct clocksource cs;
	49	};
	50
	51	static struct pistachio_clocksource pcs_gpt;
	52
	53	#define to_pistachio_clocksource(cs) \
	54	container_of(cs, struct pistachio_clocksource, cs)
	55
	56	static inline u32 gpt_readl(void __iomem *base, u32 offset, u32 gpt_id)
	57	{
	58	return readl(base + 0x20 * gpt_id + offset);
	59	}
	60
	61	static inline void gpt_writel(void __iomem *base, u32 value, u32 offset,
	62	u32 gpt_id)
	63	{
	64	writel(value, base + 0x20 * gpt_id + offset);
	65	}
	66
a5a1d1c2	67	static u64 notrace
f8af0e9c	68	pistachio_clocksource_read_cycles(struct clocksource *cs)
84583983 EG	69	{
84583983 EG	70	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
0642fb4b DF	71	__maybe_unused u32 overflow;
0642fb4b DF	72	u32 counter;
84583983 EG	73	unsigned long flags;
	74
	75	/*
	76	* The counter value is only refreshed after the overflow value is read.
	77	* And they must be read in strict order, hence raw spin lock added.
	78	*/
	79
	80	raw_spin_lock_irqsave(&pcs->lock, flags);
a47d7ef4	81	overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0);
84583983 EG	82	counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0);
	83	raw_spin_unlock_irqrestore(&pcs->lock, flags);
	84
a5a1d1c2	85	return (u64)~counter;
84583983 EG	86	}
	87
	88	static u64 notrace pistachio_read_sched_clock(void)
	89	{
	90	return pistachio_clocksource_read_cycles(&pcs_gpt.cs);
	91	}
	92
	93	static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx,
	94	int enable)
	95	{
	96	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
	97	u32 val;
	98
	99	val = gpt_readl(pcs->base, TIMER_CFG, timeridx);
	100	if (enable)
	101	val \|= TIMER_ME_LOCAL;
	102	else
	103	val &= ~TIMER_ME_LOCAL;
	104
	105	gpt_writel(pcs->base, val, TIMER_CFG, timeridx);
	106	}
	107
	108	static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx)
	109	{
	110	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
	111
	112	/* Disable GPT local before loading reload value */
	113	pistachio_clksrc_set_mode(cs, timeridx, false);
	114	gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx);
	115	pistachio_clksrc_set_mode(cs, timeridx, true);
	116	}
	117
	118	static void pistachio_clksrc_disable(struct clocksource *cs, int timeridx)
	119	{
	120	/* Disable GPT local */
	121	pistachio_clksrc_set_mode(cs, timeridx, false);
	122	}
	123
	124	static int pistachio_clocksource_enable(struct clocksource *cs)
	125	{
	126	pistachio_clksrc_enable(cs, 0);
	127	return 0;
	128	}
	129
	130	static void pistachio_clocksource_disable(struct clocksource *cs)
	131	{
	132	pistachio_clksrc_disable(cs, 0);
	133	}
	134
	135	/* Desirable clock source for pistachio platform */
	136	static struct pistachio_clocksource pcs_gpt = {
	137	.cs = {
	138	.name = "gptimer",
	139	.rating = 300,
	140	.enable = pistachio_clocksource_enable,
	141	.disable = pistachio_clocksource_disable,
	142	.read = pistachio_clocksource_read_cycles,
	143	.mask = CLOCKSOURCE_MASK(32),
	144	.flags = CLOCK_SOURCE_IS_CONTINUOUS \|
	145	CLOCK_SOURCE_SUSPEND_NONSTOP,
	146	},
	147	};
	148
41505a20	149	static int __init pistachio_clksrc_of_init(struct device_node *node)
84583983 EG	150	{
	151	struct clk sys_clk, fast_clk;
	152	struct regmap *periph_regs;
	153	unsigned long rate;
	154	int ret;
	155
	156	pcs_gpt.base = of_iomap(node, 0);
	157	if (!pcs_gpt.base) {
	158	pr_err("cannot iomap\n");
41505a20	159	return -ENXIO;
84583983 EG	160	}
	161
	162	periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
	163	if (IS_ERR(periph_regs)) {
b7c8b4aa	164	pr_err("cannot get peripheral regmap (%ld)\n",
84583983	165	PTR_ERR(periph_regs));
41505a20	166	return PTR_ERR(periph_regs);
84583983 EG	167	}
	168
	169	/* Switch to using the fast counter clock */
	170	ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
	171	0xf, 0x0);
	172	if (ret)
41505a20	173	return ret;
84583983 EG	174
	175	sys_clk = of_clk_get_by_name(node, "sys");
	176	if (IS_ERR(sys_clk)) {
b7c8b4aa	177	pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
41505a20	178	return PTR_ERR(sys_clk);
84583983 EG	179	}
	180
	181	fast_clk = of_clk_get_by_name(node, "fast");
	182	if (IS_ERR(fast_clk)) {
	183	pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
41505a20	184	return PTR_ERR(fast_clk);
84583983 EG	185	}
	186
	187	ret = clk_prepare_enable(sys_clk);
	188	if (ret < 0) {
	189	pr_err("failed to enable clock (%d)\n", ret);
41505a20	190	return ret;
84583983 EG	191	}
	192
	193	ret = clk_prepare_enable(fast_clk);
	194	if (ret < 0) {
	195	pr_err("failed to enable clock (%d)\n", ret);
	196	clk_disable_unprepare(sys_clk);
41505a20	197	return ret;
84583983 EG	198	}
	199
	200	rate = clk_get_rate(fast_clk);
	201
	202	/* Disable irq's for clocksource usage */
4d0e7016 MN	203	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0);
	204	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1);
	205	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2);
	206	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3);
84583983 EG	207
	208	/* Enable timer block */
	209	writel(TIMER_ME_GLOBAL, pcs_gpt.base);
	210
	211	raw_spin_lock_init(&pcs_gpt.lock);
	212	sched_clock_register(pistachio_read_sched_clock, 32, rate);
41505a20	213	return clocksource_register_hz(&pcs_gpt.cs, rate);
84583983	214	}
17273395	215	TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
84583983	216	pistachio_clksrc_of_init);