[linux-2.6-block.git] / drivers / clocksource / timer-milbeaut.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2018 Socionext Inc.
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include "timer-of.h"

#define MLB_TMR_TMCSR_OFS	0x0
#define MLB_TMR_TMR_OFS		0x4
#define MLB_TMR_TMRLR1_OFS	0x8
#define MLB_TMR_TMRLR2_OFS	0xc
#define MLB_TMR_REGSZPCH	0x10

#define MLB_TMR_TMCSR_OUTL	BIT(5)
#define MLB_TMR_TMCSR_RELD	BIT(4)
#define MLB_TMR_TMCSR_INTE	BIT(3)
#define MLB_TMR_TMCSR_UF	BIT(2)
#define MLB_TMR_TMCSR_CNTE	BIT(1)
#define MLB_TMR_TMCSR_TRG	BIT(0)

#define MLB_TMR_TMCSR_CSL_DIV2	0
#define MLB_TMR_DIV_CNT		2

#define MLB_TMR_SRC_CH  (1)
#define MLB_TMR_EVT_CH  (0)

#define MLB_TMR_SRC_CH_OFS	(MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
#define MLB_TMR_EVT_CH_OFS	(MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)

#define MLB_TMR_SRC_TMCSR_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
#define MLB_TMR_SRC_TMR_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
#define MLB_TMR_SRC_TMRLR1_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
#define MLB_TMR_SRC_TMRLR2_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)

#define MLB_TMR_EVT_TMCSR_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
#define MLB_TMR_EVT_TMR_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
#define MLB_TMR_EVT_TMRLR1_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
#define MLB_TMR_EVT_TMRLR2_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)

#define MLB_TIMER_RATING	500

static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *clk = dev_id;
	struct timer_of *to = to_timer_of(clk);
	u32 val;

	val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
	val &= ~MLB_TMR_TMCSR_UF;
	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);

	clk->event_handler(clk);

	return IRQ_HANDLED;
}

static int mlb_set_state_periodic(struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);
	u32 val = MLB_TMR_TMCSR_CSL_DIV2;

	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);

	writel_relaxed(to->of_clk.period, timer_of_base(to) +
				MLB_TMR_EVT_TMRLR1_OFS);
	val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
		MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
	return 0;
}

static int mlb_set_state_oneshot(struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);
	u32 val = MLB_TMR_TMCSR_CSL_DIV2;

	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
	return 0;
}

static int mlb_clkevt_next_event(unsigned long event,
				   struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);

	writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
	writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
			MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
			MLB_TMR_TMCSR_TRG, timer_of_base(to) +
			MLB_TMR_EVT_TMCSR_OFS);
	return 0;
}

static int mlb_config_clock_source(struct timer_of *to)
{
	writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
	writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
		MLB_TMR_SRC_TMCSR_OFS);
	return 0;
}

static int mlb_config_clock_event(struct timer_of *to)
{
	writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
	return 0;
}

static struct timer_of to = {
	.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,

	.clkevt = {
		.name = "mlb-clkevt",
		.rating = MLB_TIMER_RATING,
		.cpumask = cpu_possible_mask,
		.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
		.set_state_oneshot = mlb_set_state_oneshot,
		.set_state_periodic = mlb_set_state_periodic,
		.set_next_event = mlb_clkevt_next_event,
	},

	.of_irq = {
		.flags = IRQF_TIMER | IRQF_IRQPOLL,
		.handler = mlb_timer_interrupt,
	},
};

static u64 notrace mlb_timer_sched_read(void)
{
	return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS);
}

static int __init mlb_timer_init(struct device_node *node)
{
	int ret;
	unsigned long rate;

	ret = timer_of_init(node, &to);
	if (ret)
		return ret;

	rate = timer_of_rate(&to) / MLB_TMR_DIV_CNT;
	mlb_config_clock_source(&to);
	clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS,
		node->name, rate, MLB_TIMER_RATING, 32,
		clocksource_mmio_readl_down);
	sched_clock_register(mlb_timer_sched_read, 32, rate);
	mlb_config_clock_event(&to);
	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 15,
		0xffffffff);
	return 0;
}
TIMER_OF_DECLARE(mlb_peritimer, "socionext,milbeaut-timer",
		mlb_timer_init);
Commit	Line	Data
b58f28f3 ST	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2018 Socionext Inc.
	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/interrupt.h>
	8	#include <linux/irq.h>
	9	#include <linux/irqreturn.h>
	10	#include <linux/sched_clock.h>
	11	#include "timer-of.h"
	12
	13	#define MLB_TMR_TMCSR_OFS 0x0
	14	#define MLB_TMR_TMR_OFS 0x4
	15	#define MLB_TMR_TMRLR1_OFS 0x8
	16	#define MLB_TMR_TMRLR2_OFS 0xc
	17	#define MLB_TMR_REGSZPCH 0x10
	18
	19	#define MLB_TMR_TMCSR_OUTL BIT(5)
	20	#define MLB_TMR_TMCSR_RELD BIT(4)
	21	#define MLB_TMR_TMCSR_INTE BIT(3)
	22	#define MLB_TMR_TMCSR_UF BIT(2)
	23	#define MLB_TMR_TMCSR_CNTE BIT(1)
	24	#define MLB_TMR_TMCSR_TRG BIT(0)
	25
	26	#define MLB_TMR_TMCSR_CSL_DIV2 0
	27	#define MLB_TMR_DIV_CNT 2
	28
	29	#define MLB_TMR_SRC_CH (1)
	30	#define MLB_TMR_EVT_CH (0)
	31
	32	#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
	33	#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
	34
	35	#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
	36	#define MLB_TMR_SRC_TMR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
	37	#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
	38	#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
	39
	40	#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
	41	#define MLB_TMR_EVT_TMR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
	42	#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
	43	#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
	44
	45	#define MLB_TIMER_RATING 500
	46
	47	static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
	48	{
	49	struct clock_event_device *clk = dev_id;
	50	struct timer_of *to = to_timer_of(clk);
	51	u32 val;
	52
	53	val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
	54	val &= ~MLB_TMR_TMCSR_UF;
	55	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
	56
	57	clk->event_handler(clk);
	58
	59	return IRQ_HANDLED;
	60	}
	61
	62	static int mlb_set_state_periodic(struct clock_event_device *clk)
	63	{
	64	struct timer_of *to = to_timer_of(clk);
65	u32 val = MLB_TMR_TMCSR_CSL_DIV2;
66
67	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
68
69	writel_relaxed(to->of_clk.period, timer_of_base(to) +
70	MLB_TMR_EVT_TMRLR1_OFS);
71	val \|= MLB_TMR_TMCSR_RELD \| MLB_TMR_TMCSR_CNTE \|
72	MLB_TMR_TMCSR_TRG \| MLB_TMR_TMCSR_INTE;
73	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
74	return 0;
75	}
76
77	static int mlb_set_state_oneshot(struct clock_event_device *clk)
78	{
79	struct timer_of *to = to_timer_of(clk);
80	u32 val = MLB_TMR_TMCSR_CSL_DIV2;
81
82	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
83	return 0;
84	}
85
86	static int mlb_clkevt_next_event(unsigned long event,
87	struct clock_event_device *clk)
88	{
89	struct timer_of *to = to_timer_of(clk);
90
91	writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
92	writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 \|
93	MLB_TMR_TMCSR_CNTE \| MLB_TMR_TMCSR_INTE \|
94	MLB_TMR_TMCSR_TRG, timer_of_base(to) +
95	MLB_TMR_EVT_TMCSR_OFS);
96	return 0;
97	}
98
99	static int mlb_config_clock_source(struct timer_of *to)
100	{
101	writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
102	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
103	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
104	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
105	writel_relaxed(BIT(4) \| BIT(1) \| BIT(0), timer_of_base(to) +
106	MLB_TMR_SRC_TMCSR_OFS);
107	return 0;
108	}
109
110	static int mlb_config_clock_event(struct timer_of *to)
111	{
112	writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
113	return 0;
114	}
115
116	static struct timer_of to = {
117	.flags = TIMER_OF_IRQ \| TIMER_OF_BASE \| TIMER_OF_CLOCK,
118
119	.clkevt = {
120	.name = "mlb-clkevt",
121	.rating = MLB_TIMER_RATING,
122	.cpumask = cpu_possible_mask,
123	.features = CLOCK_EVT_FEAT_DYNIRQ \| CLOCK_EVT_FEAT_ONESHOT,
124	.set_state_oneshot = mlb_set_state_oneshot,
125	.set_state_periodic = mlb_set_state_periodic,
126	.set_next_event = mlb_clkevt_next_event,
127	},
128
129	.of_irq = {
130	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
131	.handler = mlb_timer_interrupt,
132	},
133	};
134
135	static u64 notrace mlb_timer_sched_read(void)
136	{
137	return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS);
138	}
139
140	static int __init mlb_timer_init(struct device_node *node)
141	{
142	int ret;
143	unsigned long rate;
144
145	ret = timer_of_init(node, &to);
146	if (ret)
147	return ret;
148
149	rate = timer_of_rate(&to) / MLB_TMR_DIV_CNT;
150	mlb_config_clock_source(&to);
151	clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS,
152	node->name, rate, MLB_TIMER_RATING, 32,
153	clocksource_mmio_readl_down);
154	sched_clock_register(mlb_timer_sched_read, 32, rate);
155	mlb_config_clock_event(&to);
156	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 15,
157	0xffffffff);
158	return 0;
159	}
160	TIMER_OF_DECLARE(mlb_peritimer, "socionext,milbeaut-timer",
161	mlb_timer_init);