[linux-2.6-block.git] / drivers / clocksource / timer-microchip-pit64b.c

// SPDX-License-Identifier: GPL-2.0
/*
 * 64-bit Periodic Interval Timer driver
 *
 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
 *
 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>

#define MCHP_PIT64B_CR			0x00	/* Control Register */
#define MCHP_PIT64B_CR_START		BIT(0)
#define MCHP_PIT64B_CR_SWRST		BIT(8)

#define MCHP_PIT64B_MR			0x04	/* Mode Register */
#define MCHP_PIT64B_MR_CONT		BIT(0)
#define MCHP_PIT64B_MR_ONE_SHOT		(0)
#define MCHP_PIT64B_MR_SGCLK		BIT(3)
#define MCHP_PIT64B_MR_PRES		GENMASK(11, 8)

#define MCHP_PIT64B_LSB_PR		0x08	/* LSB Period Register */

#define MCHP_PIT64B_MSB_PR		0x0C	/* MSB Period Register */

#define MCHP_PIT64B_IER			0x10	/* Interrupt Enable Register */
#define MCHP_PIT64B_IER_PERIOD		BIT(0)

#define MCHP_PIT64B_ISR			0x1C	/* Interrupt Status Register */

#define MCHP_PIT64B_TLSBR		0x20	/* Timer LSB Register */

#define MCHP_PIT64B_TMSBR		0x24	/* Timer MSB Register */

#define MCHP_PIT64B_PRES_MAX		0x10
#define MCHP_PIT64B_LSBMASK		GENMASK_ULL(31, 0)
#define MCHP_PIT64B_PRES_TO_MODE(p)	(MCHP_PIT64B_MR_PRES & ((p) << 8))
#define MCHP_PIT64B_MODE_TO_PRES(m)	((MCHP_PIT64B_MR_PRES & (m)) >> 8)
#define MCHP_PIT64B_DEF_FREQ		5000000UL	/* 5 MHz */

#define MCHP_PIT64B_NAME		"pit64b"

/**
 * struct mchp_pit64b_timer - PIT64B timer data structure
 * @base: base address of PIT64B hardware block
 * @pclk: PIT64B's peripheral clock
 * @gclk: PIT64B's generic clock
 * @mode: precomputed value for mode register
 */
struct mchp_pit64b_timer {
	void __iomem	*base;
	struct clk	*pclk;
	struct clk	*gclk;
	u32		mode;
};

/**
 * struct mchp_pit64b_clkevt - PIT64B clockevent data structure
 * @timer: PIT64B timer
 * @clkevt: clockevent
 */
struct mchp_pit64b_clkevt {
	struct mchp_pit64b_timer	timer;
	struct clock_event_device	clkevt;
};

#define clkevt_to_mchp_pit64b_timer(x) \
	((struct mchp_pit64b_timer *)container_of(x,\
		struct mchp_pit64b_clkevt, clkevt))

/**
 * struct mchp_pit64b_clksrc - PIT64B clocksource data structure
 * @timer: PIT64B timer
 * @clksrc: clocksource
 */
struct mchp_pit64b_clksrc {
	struct mchp_pit64b_timer	timer;
	struct clocksource		clksrc;
};

#define clksrc_to_mchp_pit64b_timer(x) \
	((struct mchp_pit64b_timer *)container_of(x,\
		struct mchp_pit64b_clksrc, clksrc))

/* Base address for clocksource timer. */
static void __iomem *mchp_pit64b_cs_base;
/* Default cycles for clockevent timer. */
static u64 mchp_pit64b_ce_cycles;

static inline u64 mchp_pit64b_cnt_read(void __iomem *base)
{
	unsigned long	flags;
	u32		low, high;

	raw_local_irq_save(flags);

	/*
	 * When using a 64 bit period TLSB must be read first, followed by the
	 * read of TMSB. This sequence generates an atomic read of the 64 bit
	 * timer value whatever the lapse of time between the accesses.
	 */
	low = readl_relaxed(base + MCHP_PIT64B_TLSBR);
	high = readl_relaxed(base + MCHP_PIT64B_TMSBR);

	raw_local_irq_restore(flags);

	return (((u64)high << 32) | low);
}

static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
				     u64 cycles, u32 mode, u32 irqs)
{
	u32 low, high;

	low = cycles & MCHP_PIT64B_LSBMASK;
	high = cycles >> 32;

	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);
	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
}

static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
{
	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
		clk_disable_unprepare(timer->gclk);
	clk_disable_unprepare(timer->pclk);
}

static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
{
	clk_prepare_enable(timer->pclk);
	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
		clk_prepare_enable(timer->gclk);
}

static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
{
	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);

	mchp_pit64b_suspend(timer);
}

static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
{
	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);

	mchp_pit64b_resume(timer);
	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
}

static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
{
	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
}

static u64 notrace mchp_pit64b_sched_read_clk(void)
{
	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
}

static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	if (!clockevent_state_detached(cedev))
		mchp_pit64b_suspend(timer);

	return 0;
}

static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	if (clockevent_state_shutdown(cedev))
		mchp_pit64b_resume(timer);

	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
			  MCHP_PIT64B_IER_PERIOD);

	return 0;
}

static int mchp_pit64b_clkevt_set_oneshot(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	if (clockevent_state_shutdown(cedev))
		mchp_pit64b_resume(timer);

	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_ONE_SHOT,
			  MCHP_PIT64B_IER_PERIOD);

	return 0;
}

static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
					     struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
			  MCHP_PIT64B_IER_PERIOD);

	return 0;
}

static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
{
	struct mchp_pit64b_clkevt *irq_data = dev_id;

	/* Need to clear the interrupt. */
	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);

	irq_data->clkevt.event_handler(&irq_data->clkevt);

	return IRQ_HANDLED;
}

static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate,
					    u32 max_rate)
{
	u32 tmp;

	for (*pres = 0; *pres < MCHP_PIT64B_PRES_MAX; (*pres)++) {
		tmp = clk_rate / (*pres + 1);
		if (tmp <= max_rate)
			break;
	}

	/* Use the biggest prescaler if we didn't match one. */
	if (*pres == MCHP_PIT64B_PRES_MAX)
		*pres = MCHP_PIT64B_PRES_MAX - 1;
}

/**
 * mchp_pit64b_init_mode() - prepare PIT64B mode register value to be used at
 *			     runtime; this includes prescaler and SGCLK bit
 * @timer: pointer to pit64b timer to init
 * @max_rate: maximum rate that timer's clock could use
 *
 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
 * divided by the internal PIT64B's divider.
 *
 * This function, first tries to use GCLK by requesting the desired rate from
 * PMC and then using the internal PIT64B prescaler, if any, to reach the
 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
 * then the function falls back on using PCLK as clock source for PIT64B timer
 * choosing the highest prescaler in case it doesn't locate one to match the
 * requested frequency.
 *
 * Below is presented the PIT64B block in relation with PMC:
 *
 *                                PIT64B
 *  PMC             +------------------------------------+
 * +----+           |   +-----+                          |
 * |    |-->gclk -->|-->|     |    +---------+  +-----+  |
 * |    |           |   | MUX |--->| Divider |->|timer|  |
 * |    |-->pclk -->|-->|     |    +---------+  +-----+  |
 * +----+           |   +-----+                          |
 *                  |      ^                             |
 *                  |     sel                            |
 *                  +------------------------------------+
 *
 * Where:
 *	- gclk rate <= pclk rate/3
 *	- gclk rate could be requested from PMC
 *	- pclk rate is fixed (cannot be requested from PMC)
 */
static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
					unsigned long max_rate)
{
	unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX;
	long gclk_round = 0;
	u32 pres, best_pres = 0;

	pclk_rate = clk_get_rate(timer->pclk);
	if (!pclk_rate)
		return -EINVAL;

	timer->mode = 0;

	/* Try using GCLK. */
	gclk_round = clk_round_rate(timer->gclk, max_rate);
	if (gclk_round < 0)
		goto pclk;

	if (pclk_rate / gclk_round < 3)
		goto pclk;

	mchp_pit64b_pres_compute(&pres, gclk_round, max_rate);
	best_diff = abs(gclk_round / (pres + 1) - max_rate);
	best_pres = pres;

	if (!best_diff) {
		timer->mode |= MCHP_PIT64B_MR_SGCLK;
		clk_set_rate(timer->gclk, gclk_round);
		goto done;
	}

pclk:
	/* Check if requested rate could be obtained using PCLK. */
	mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate);
	diff = abs(pclk_rate / (pres + 1) - max_rate);

	if (best_diff > diff) {
		/* Use PCLK. */
		best_pres = pres;
	} else {
		/* Use GCLK. */
		timer->mode |= MCHP_PIT64B_MR_SGCLK;
		clk_set_rate(timer->gclk, gclk_round);
	}

done:
	timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres);

	pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",
		timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
		timer->mode & MCHP_PIT64B_MR_SGCLK ?
		gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1));

	return 0;
}

static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
					  u32 clk_rate)
{
	struct mchp_pit64b_clksrc *cs;
	int ret;

	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
	if (!cs)
		return -ENOMEM;

	mchp_pit64b_resume(timer);
	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);

	mchp_pit64b_cs_base = timer->base;

	cs->timer.base = timer->base;
	cs->timer.pclk = timer->pclk;
	cs->timer.gclk = timer->gclk;
	cs->timer.mode = timer->mode;
	cs->clksrc.name = MCHP_PIT64B_NAME;
	cs->clksrc.mask = CLOCKSOURCE_MASK(64);
	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	cs->clksrc.rating = 210;
	cs->clksrc.read = mchp_pit64b_clksrc_read;
	cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
	cs->clksrc.resume = mchp_pit64b_clksrc_resume;

	ret = clocksource_register_hz(&cs->clksrc, clk_rate);
	if (ret) {
		pr_debug("clksrc: Failed to register PIT64B clocksource!\n");

		/* Stop timer. */
		mchp_pit64b_suspend(timer);
		kfree(cs);

		return ret;
	}

	sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);

	return 0;
}

static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
					  u32 clk_rate, u32 irq)
{
	struct mchp_pit64b_clkevt *ce;
	int ret;

	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
	if (!ce)
		return -ENOMEM;

	mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);

	ce->timer.base = timer->base;
	ce->timer.pclk = timer->pclk;
	ce->timer.gclk = timer->gclk;
	ce->timer.mode = timer->mode;
	ce->clkevt.name = MCHP_PIT64B_NAME;
	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
	ce->clkevt.rating = 150;
	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;
	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;
	ce->clkevt.set_state_oneshot = mchp_pit64b_clkevt_set_oneshot;
	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;
	ce->clkevt.cpumask = cpumask_of(0);
	ce->clkevt.irq = irq;

	ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER,
			  "pit64b_tick", ce);
	if (ret) {
		pr_debug("clkevt: Failed to setup PIT64B IRQ\n");
		kfree(ce);
		return ret;
	}

	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);

	return 0;
}

static int __init mchp_pit64b_dt_init_timer(struct device_node *node,
					    bool clkevt)
{
	struct mchp_pit64b_timer timer;
	unsigned long clk_rate;
	u32 irq = 0;
	int ret;

	/* Parse DT node. */
	timer.pclk = of_clk_get_by_name(node, "pclk");
	if (IS_ERR(timer.pclk))
		return PTR_ERR(timer.pclk);

	timer.gclk = of_clk_get_by_name(node, "gclk");
	if (IS_ERR(timer.gclk))
		return PTR_ERR(timer.gclk);

	timer.base = of_iomap(node, 0);
	if (!timer.base)
		return -ENXIO;

	if (clkevt) {
		irq = irq_of_parse_and_map(node, 0);
		if (!irq) {
			ret = -ENODEV;
			goto io_unmap;
		}
	}

	/* Initialize mode (prescaler + SGCK bit). To be used at runtime. */
	ret = mchp_pit64b_init_mode(&timer, MCHP_PIT64B_DEF_FREQ);
	if (ret)
		goto irq_unmap;

	if (timer.mode & MCHP_PIT64B_MR_SGCLK)
		clk_rate = clk_get_rate(timer.gclk);
	else
		clk_rate = clk_get_rate(timer.pclk);
	clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);

	if (clkevt)
		ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
	else
		ret = mchp_pit64b_init_clksrc(&timer, clk_rate);

	if (ret)
		goto irq_unmap;

	return 0;

irq_unmap:
	irq_dispose_mapping(irq);
io_unmap:
	iounmap(timer.base);

	return ret;
}

static int __init mchp_pit64b_dt_init(struct device_node *node)
{
	static int inits;

	switch (inits++) {
	case 0:
		/* 1st request, register clockevent. */
		return mchp_pit64b_dt_init_timer(node, true);
	case 1:
		/* 2nd request, register clocksource. */
		return mchp_pit64b_dt_init_timer(node, false);
	}

	/* The rest, don't care. */
	return -EINVAL;
}

TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);
Commit	Line	Data
625022a5 CB	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* 64-bit Periodic Interval Timer driver
	4	*
	5	* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
	6	*
	7	* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
	15	#include <linux/sched_clock.h>
	16	#include <linux/slab.h>
	17
	18	#define MCHP_PIT64B_CR 0x00 /* Control Register */
	19	#define MCHP_PIT64B_CR_START BIT(0)
	20	#define MCHP_PIT64B_CR_SWRST BIT(8)
	21
	22	#define MCHP_PIT64B_MR 0x04 /* Mode Register */
	23	#define MCHP_PIT64B_MR_CONT BIT(0)
	24	#define MCHP_PIT64B_MR_ONE_SHOT (0)
	25	#define MCHP_PIT64B_MR_SGCLK BIT(3)
	26	#define MCHP_PIT64B_MR_PRES GENMASK(11, 8)
	27
	28	#define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */
	29
	30	#define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */
	31
	32	#define MCHP_PIT64B_IER 0x10 /* Interrupt Enable Register */
	33	#define MCHP_PIT64B_IER_PERIOD BIT(0)
	34
	35	#define MCHP_PIT64B_ISR 0x1C /* Interrupt Status Register */
	36
	37	#define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */
	38
	39	#define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */
	40
	41	#define MCHP_PIT64B_PRES_MAX 0x10
	42	#define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0)
	43	#define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8))
	44	#define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8)
389e3bff	45	#define MCHP_PIT64B_DEF_FREQ 5000000UL /* 5 MHz */
625022a5 CB	46
	47	#define MCHP_PIT64B_NAME "pit64b"
	48
	49	/**
	50	* struct mchp_pit64b_timer - PIT64B timer data structure
	51	* @base: base address of PIT64B hardware block
	52	* @pclk: PIT64B's peripheral clock
	53	* @gclk: PIT64B's generic clock
	54	* @mode: precomputed value for mode register
	55	*/
	56	struct mchp_pit64b_timer {
	57	void __iomem *base;
	58	struct clk *pclk;
	59	struct clk *gclk;
	60	u32 mode;
	61	};
	62
	63	/**
278150b2	64	* struct mchp_pit64b_clkevt - PIT64B clockevent data structure
625022a5 CB	65	* @timer: PIT64B timer
	66	* @clkevt: clockevent
	67	*/
	68	struct mchp_pit64b_clkevt {
	69	struct mchp_pit64b_timer timer;
	70	struct clock_event_device clkevt;
	71	};
	72
e85c1d21	73	#define clkevt_to_mchp_pit64b_timer(x) \
625022a5 CB	74	((struct mchp_pit64b_timer *)container_of(x,\
	75	struct mchp_pit64b_clkevt, clkevt))
	76
e85c1d21	77	/**
278150b2	78	* struct mchp_pit64b_clksrc - PIT64B clocksource data structure
e85c1d21 CB	79	* @timer: PIT64B timer
	80	* @clksrc: clocksource
	81	*/
	82	struct mchp_pit64b_clksrc {
	83	struct mchp_pit64b_timer timer;
	84	struct clocksource clksrc;
	85	};
	86
	87	#define clksrc_to_mchp_pit64b_timer(x) \
	88	((struct mchp_pit64b_timer *)container_of(x,\
	89	struct mchp_pit64b_clksrc, clksrc))
	90
625022a5 CB	91	/* Base address for clocksource timer. */
	92	static void __iomem *mchp_pit64b_cs_base;
	93	/* Default cycles for clockevent timer. */
	94	static u64 mchp_pit64b_ce_cycles;
	95
	96	static inline u64 mchp_pit64b_cnt_read(void __iomem *base)
	97	{
	98	unsigned long flags;
	99	u32 low, high;
	100
	101	raw_local_irq_save(flags);
	102
	103	/*
	104	* When using a 64 bit period TLSB must be read first, followed by the
	105	* read of TMSB. This sequence generates an atomic read of the 64 bit
	106	* timer value whatever the lapse of time between the accesses.
	107	*/
	108	low = readl_relaxed(base + MCHP_PIT64B_TLSBR);
	109	high = readl_relaxed(base + MCHP_PIT64B_TMSBR);
	110
	111	raw_local_irq_restore(flags);
	112
	113	return (((u64)high << 32) \| low);
	114	}
	115
	116	static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
	117	u64 cycles, u32 mode, u32 irqs)
	118	{
	119	u32 low, high;
	120
	121	low = cycles & MCHP_PIT64B_LSBMASK;
	122	high = cycles >> 32;
	123
	124	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	125	writel_relaxed(mode \| timer->mode, timer->base + MCHP_PIT64B_MR);
	126	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
	127	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
	128	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
	129	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
	130	}
	131
e85c1d21 CB	132	static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
	133	{
	134	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	135	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
	136	clk_disable_unprepare(timer->gclk);
	137	clk_disable_unprepare(timer->pclk);
	138	}
	139
	140	static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
	141	{
	142	clk_prepare_enable(timer->pclk);
	143	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
	144	clk_prepare_enable(timer->gclk);
	145	}
	146
	147	static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
	148	{
	149	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
	150
	151	mchp_pit64b_suspend(timer);
	152	}
	153
	154	static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
	155	{
	156	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
	157
	158	mchp_pit64b_resume(timer);
	159	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
	160	}
	161
625022a5 CB	162	static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
	163	{
	164	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
	165	}
	166
ff10ee97	167	static u64 notrace mchp_pit64b_sched_read_clk(void)
625022a5 CB	168	{
	169	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
	170	}
	171
	172	static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
	173	{
e85c1d21	174	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5	175
2c9c4c9e CB	176	if (!clockevent_state_detached(cedev))
2c9c4c9e CB	177	mchp_pit64b_suspend(timer);
625022a5 CB	178
	179	return 0;
	180	}
	181
	182	static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
	183	{
e85c1d21	184	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5	185
2c9c4c9e CB	186	if (clockevent_state_shutdown(cedev))
	187	mchp_pit64b_resume(timer);
	188
625022a5 CB	189	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
	190	MCHP_PIT64B_IER_PERIOD);
	191
	192	return 0;
	193	}
	194
2c9c4c9e	195	static int mchp_pit64b_clkevt_set_oneshot(struct clock_event_device *cedev)
625022a5	196	{
e85c1d21	197	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5	198
2c9c4c9e CB	199	if (clockevent_state_shutdown(cedev))
	200	mchp_pit64b_resume(timer);
	201
	202	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_ONE_SHOT,
625022a5 CB	203	MCHP_PIT64B_IER_PERIOD);
	204
	205	return 0;
	206	}
	207
2c9c4c9e CB	208	static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
2c9c4c9e CB	209	struct clock_event_device *cedev)
625022a5	210	{
e85c1d21	211	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5	212
2c9c4c9e CB	213	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
2c9c4c9e CB	214	MCHP_PIT64B_IER_PERIOD);
625022a5	215
2c9c4c9e	216	return 0;
625022a5 CB	217	}
	218
	219	static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
	220	{
	221	struct mchp_pit64b_clkevt *irq_data = dev_id;
	222
	223	/* Need to clear the interrupt. */
	224	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);
	225
	226	irq_data->clkevt.event_handler(&irq_data->clkevt);
	227
	228	return IRQ_HANDLED;
	229	}
	230
	231	static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate,
	232	u32 max_rate)
	233	{
	234	u32 tmp;
	235
	236	for (pres = 0; pres < MCHP_PIT64B_PRES_MAX; (*pres)++) {
	237	tmp = clk_rate / (*pres + 1);
	238	if (tmp <= max_rate)
	239	break;
	240	}
	241
4bf07f65	242	/* Use the biggest prescaler if we didn't match one. */
625022a5 CB	243	if (*pres == MCHP_PIT64B_PRES_MAX)
	244	*pres = MCHP_PIT64B_PRES_MAX - 1;
	245	}
	246
	247	/**
278150b2 CB	248	* mchp_pit64b_init_mode() - prepare PIT64B mode register value to be used at
	249	* runtime; this includes prescaler and SGCLK bit
	250	* @timer: pointer to pit64b timer to init
	251	* @max_rate: maximum rate that timer's clock could use
625022a5 CB	252	*
	253	* PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
	254	* be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
	255	* could be changed via clock APIs. The chosen clock (pclk or gclk) could be
	256	* divided by the internal PIT64B's divider.
	257	*
	258	* This function, first tries to use GCLK by requesting the desired rate from
	259	* PMC and then using the internal PIT64B prescaler, if any, to reach the
	260	* requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
	261	* then the function falls back on using PCLK as clock source for PIT64B timer
	262	* choosing the highest prescaler in case it doesn't locate one to match the
	263	* requested frequency.
	264	*
	265	* Below is presented the PIT64B block in relation with PMC:
	266	*
	267	* PIT64B
	268	* PMC +------------------------------------+
	269	* +----+ \| +-----+ \|
	270	* \| \|-->gclk -->\|-->\| \| +---------+ +-----+ \|
	271	* \| \| \| \| MUX \|--->\| Divider \|->\|timer\| \|
	272	* \| \|-->pclk -->\|-->\| \| +---------+ +-----+ \|
	273	* +----+ \| +-----+ \|
	274	* \| ^ \|
	275	* \| sel \|
	276	* +------------------------------------+
	277	*
	278	* Where:
	279	* - gclk rate <= pclk rate/3
	280	* - gclk rate could be requested from PMC
	281	* - pclk rate is fixed (cannot be requested from PMC)
	282	*/
	283	static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
	284	unsigned long max_rate)
	285	{
	286	unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX;
	287	long gclk_round = 0;
	288	u32 pres, best_pres = 0;
	289
	290	pclk_rate = clk_get_rate(timer->pclk);
	291	if (!pclk_rate)
	292	return -EINVAL;
	293
b9c60a74 CB	294	timer->mode = 0;
b9c60a74 CB	295
625022a5 CB	296	/* Try using GCLK. */
	297	gclk_round = clk_round_rate(timer->gclk, max_rate);
	298	if (gclk_round < 0)
	299	goto pclk;
	300
	301	if (pclk_rate / gclk_round < 3)
	302	goto pclk;
	303
	304	mchp_pit64b_pres_compute(&pres, gclk_round, max_rate);
	305	best_diff = abs(gclk_round / (pres + 1) - max_rate);
	306	best_pres = pres;
	307
	308	if (!best_diff) {
	309	timer->mode \|= MCHP_PIT64B_MR_SGCLK;
05852445	310	clk_set_rate(timer->gclk, gclk_round);
625022a5 CB	311	goto done;
	312	}
	313
	314	pclk:
	315	/* Check if requested rate could be obtained using PCLK. */
	316	mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate);
	317	diff = abs(pclk_rate / (pres + 1) - max_rate);
	318
	319	if (best_diff > diff) {
	320	/* Use PCLK. */
	321	best_pres = pres;
	322	} else {
	323	/* Use GCLK. */
	324	timer->mode \|= MCHP_PIT64B_MR_SGCLK;
	325	clk_set_rate(timer->gclk, gclk_round);
	326	}
	327
	328	done:
	329	timer->mode \|= MCHP_PIT64B_PRES_TO_MODE(best_pres);
	330
	331	pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",
	332	timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
	333	timer->mode & MCHP_PIT64B_MR_SGCLK ?
	334	gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1));
	335
	336	return 0;
	337	}
	338
	339	static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
	340	u32 clk_rate)
	341	{
e85c1d21	342	struct mchp_pit64b_clksrc *cs;
625022a5 CB	343	int ret;
625022a5 CB	344
e85c1d21 CB	345	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
	346	if (!cs)
	347	return -ENOMEM;
	348
b02180e8	349	mchp_pit64b_resume(timer);
625022a5 CB	350	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
	351
	352	mchp_pit64b_cs_base = timer->base;
	353
e85c1d21 CB	354	cs->timer.base = timer->base;
	355	cs->timer.pclk = timer->pclk;
	356	cs->timer.gclk = timer->gclk;
	357	cs->timer.mode = timer->mode;
	358	cs->clksrc.name = MCHP_PIT64B_NAME;
	359	cs->clksrc.mask = CLOCKSOURCE_MASK(64);
	360	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	361	cs->clksrc.rating = 210;
	362	cs->clksrc.read = mchp_pit64b_clksrc_read;
	363	cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
	364	cs->clksrc.resume = mchp_pit64b_clksrc_resume;
	365
	366	ret = clocksource_register_hz(&cs->clksrc, clk_rate);
625022a5 CB	367	if (ret) {
	368	pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
	369
	370	/* Stop timer. */
b02180e8	371	mchp_pit64b_suspend(timer);
e85c1d21	372	kfree(cs);
625022a5 CB	373
	374	return ret;
	375	}
	376
	377	sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);
	378
	379	return 0;
	380	}
	381
	382	static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
	383	u32 clk_rate, u32 irq)
	384	{
	385	struct mchp_pit64b_clkevt *ce;
	386	int ret;
	387
	388	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
	389	if (!ce)
	390	return -ENOMEM;
	391
	392	mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);
	393
	394	ce->timer.base = timer->base;
	395	ce->timer.pclk = timer->pclk;
	396	ce->timer.gclk = timer->gclk;
	397	ce->timer.mode = timer->mode;
	398	ce->clkevt.name = MCHP_PIT64B_NAME;
	399	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC;
	400	ce->clkevt.rating = 150;
	401	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;
	402	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;
2c9c4c9e	403	ce->clkevt.set_state_oneshot = mchp_pit64b_clkevt_set_oneshot;
625022a5	404	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;
625022a5 CB	405	ce->clkevt.cpumask = cpumask_of(0);
	406	ce->clkevt.irq = irq;
	407
	408	ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER,
	409	"pit64b_tick", ce);
	410	if (ret) {
	411	pr_debug("clkevt: Failed to setup PIT64B IRQ\n");
	412	kfree(ce);
	413	return ret;
	414	}
	415
	416	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);
	417
	418	return 0;
	419	}
	420
	421	static int __init mchp_pit64b_dt_init_timer(struct device_node *node,
	422	bool clkevt)
	423	{
b9c60a74	424	struct mchp_pit64b_timer timer;
625022a5 CB	425	unsigned long clk_rate;
	426	u32 irq = 0;
	427	int ret;
	428
	429	/* Parse DT node. */
	430	timer.pclk = of_clk_get_by_name(node, "pclk");
	431	if (IS_ERR(timer.pclk))
	432	return PTR_ERR(timer.pclk);
	433
	434	timer.gclk = of_clk_get_by_name(node, "gclk");
	435	if (IS_ERR(timer.gclk))
	436	return PTR_ERR(timer.gclk);
	437
	438	timer.base = of_iomap(node, 0);
	439	if (!timer.base)
	440	return -ENXIO;
	441
	442	if (clkevt) {
	443	irq = irq_of_parse_and_map(node, 0);
	444	if (!irq) {
	445	ret = -ENODEV;
	446	goto io_unmap;
	447	}
	448	}
	449
	450	/* Initialize mode (prescaler + SGCK bit). To be used at runtime. */
389e3bff	451	ret = mchp_pit64b_init_mode(&timer, MCHP_PIT64B_DEF_FREQ);
625022a5 CB	452	if (ret)
	453	goto irq_unmap;
	454
b02180e8	455	if (timer.mode & MCHP_PIT64B_MR_SGCLK)
625022a5	456	clk_rate = clk_get_rate(timer.gclk);
b02180e8	457	else
625022a5	458	clk_rate = clk_get_rate(timer.pclk);
625022a5 CB	459	clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);
	460
	461	if (clkevt)
	462	ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
	463	else
	464	ret = mchp_pit64b_init_clksrc(&timer, clk_rate);
	465
	466	if (ret)
b02180e8	467	goto irq_unmap;
625022a5 CB	468
	469	return 0;
	470
625022a5 CB	471	irq_unmap:
	472	irq_dispose_mapping(irq);
	473	io_unmap:
	474	iounmap(timer.base);
	475
	476	return ret;
	477	}
	478
	479	static int __init mchp_pit64b_dt_init(struct device_node *node)
	480	{
	481	static int inits;
	482
	483	switch (inits++) {
	484	case 0:
	485	/* 1st request, register clockevent. */
	486	return mchp_pit64b_dt_init_timer(node, true);
	487	case 1:
	488	/* 2nd request, register clocksource. */
	489	return mchp_pit64b_dt_init_timer(node, false);
	490	}
	491
	492	/* The rest, don't care. */
	493	return -EINVAL;
	494	}
	495
	496	TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);