[linux-2.6-block.git] / drivers / clocksource / timer-mediatek.c

/*
 * Mediatek SoCs General-Purpose Timer handling.
 *
 * Copyright (C) 2014 Matthias Brugger
 *
 * Matthias Brugger <matthias.bgg@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
#include "timer-of.h"

#define TIMER_CLK_EVT           (1)
#define TIMER_CLK_SRC           (2)

#define TIMER_SYNC_TICKS        (3)

/* gpt */
#define GPT_IRQ_EN_REG          0x00
#define GPT_IRQ_ENABLE(val)     BIT((val) - 1)
#define GPT_IRQ_ACK_REG	        0x08
#define GPT_IRQ_ACK(val)        BIT((val) - 1)

#define GPT_CTRL_REG(val)       (0x10 * (val))
#define GPT_CTRL_OP(val)        (((val) & 0x3) << 4)
#define GPT_CTRL_OP_ONESHOT     (0)
#define GPT_CTRL_OP_REPEAT      (1)
#define GPT_CTRL_OP_FREERUN     (3)
#define GPT_CTRL_CLEAR          (2)
#define GPT_CTRL_ENABLE         (1)
#define GPT_CTRL_DISABLE        (0)

#define GPT_CLK_REG(val)        (0x04 + (0x10 * (val)))
#define GPT_CLK_SRC(val)        (((val) & 0x1) << 4)
#define GPT_CLK_SRC_SYS13M      (0)
#define GPT_CLK_SRC_RTC32K      (1)
#define GPT_CLK_DIV1            (0x0)
#define GPT_CLK_DIV2            (0x1)

#define GPT_CNT_REG(val)        (0x08 + (0x10 * (val)))
#define GPT_CMP_REG(val)        (0x0C + (0x10 * (val)))

/* system timer */
#define SYST_BASE               (0x40)

#define SYST_CON                (SYST_BASE + 0x0)
#define SYST_VAL                (SYST_BASE + 0x4)

#define SYST_CON_REG(to)        (timer_of_base(to) + SYST_CON)
#define SYST_VAL_REG(to)        (timer_of_base(to) + SYST_VAL)

/*
 * SYST_CON_EN: Clock enable. Shall be set to
 *   - Start timer countdown.
 *   - Allow timeout ticks being updated.
 *   - Allow changing interrupt functions.
 *
 * SYST_CON_IRQ_EN: Set to allow interrupt.
 *
 * SYST_CON_IRQ_CLR: Set to clear interrupt.
 */
#define SYST_CON_EN              BIT(0)
#define SYST_CON_IRQ_EN          BIT(1)
#define SYST_CON_IRQ_CLR         BIT(4)

static void __iomem *gpt_sched_reg __read_mostly;

static void mtk_syst_ack_irq(struct timer_of *to)
{
	/* Clear and disable interrupt */
	writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
}

static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
{
	struct clock_event_device *clkevt = dev_id;
	struct timer_of *to = to_timer_of(clkevt);

	mtk_syst_ack_irq(to);
	clkevt->event_handler(clkevt);

	return IRQ_HANDLED;
}

static int mtk_syst_clkevt_next_event(unsigned long ticks,
				      struct clock_event_device *clkevt)
{
	struct timer_of *to = to_timer_of(clkevt);

	/* Enable clock to allow timeout tick update later */
	writel(SYST_CON_EN, SYST_CON_REG(to));

	/*
	 * Write new timeout ticks. Timer shall start countdown
	 * after timeout ticks are updated.
	 */
	writel(ticks, SYST_VAL_REG(to));

	/* Enable interrupt */
	writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));

	return 0;
}

static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
{
	/* Disable timer */
	writel(0, SYST_CON_REG(to_timer_of(clkevt)));

	return 0;
}

static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
{
	return mtk_syst_clkevt_shutdown(clkevt);
}

static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
{
	return 0;
}

static u64 notrace mtk_gpt_read_sched_clock(void)
{
	return readl_relaxed(gpt_sched_reg);
}

static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
{
	u32 val;

	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
	writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
	       GPT_CTRL_REG(timer));
}

static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
				      unsigned long delay, u8 timer)
{
	writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
}

static void mtk_gpt_clkevt_time_start(struct timer_of *to,
				      bool periodic, u8 timer)
{
	u32 val;

	/* Acknowledge interrupt */
	writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);

	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));

	/* Clear 2 bit timer operation mode field */
	val &= ~GPT_CTRL_OP(0x3);

	if (periodic)
		val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
	else
		val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);

	writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
	       timer_of_base(to) + GPT_CTRL_REG(timer));
}

static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
{
	mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);

	return 0;
}

static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);

	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
	mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
	mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);

	return 0;
}

static int mtk_gpt_clkevt_next_event(unsigned long event,
				     struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);

	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
	mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
	mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);

	return 0;
}

static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
	struct timer_of *to = to_timer_of(clkevt);

	/* Acknowledge timer0 irq */
	writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
	clkevt->event_handler(clkevt);

	return IRQ_HANDLED;
}

static void
__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
{
	writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
	       timer_of_base(to) + GPT_CTRL_REG(timer));

	writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
	       timer_of_base(to) + GPT_CLK_REG(timer));

	writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));

	writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
	       timer_of_base(to) + GPT_CTRL_REG(timer));
}

static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
{
	u32 val;

	/* Disable all interrupts */
	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);

	/* Acknowledge all spurious pending interrupts */
	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);

	val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
	writel(val | GPT_IRQ_ENABLE(timer),
	       timer_of_base(to) + GPT_IRQ_EN_REG);
}

static struct timer_of to = {
	.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,

	.clkevt = {
		.name = "mtk-clkevt",
		.rating = 300,
		.cpumask = cpu_possible_mask,
	},

	.of_irq = {
		.flags = IRQF_TIMER | IRQF_IRQPOLL,
	},
};

static int __init mtk_syst_init(struct device_node *node)
{
	int ret;

	to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
	to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
	to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
	to.clkevt.tick_resume = mtk_syst_clkevt_resume;
	to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
	to.of_irq.handler = mtk_syst_handler;

	ret = timer_of_init(node, &to);
	if (ret)
		goto err;

	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
					TIMER_SYNC_TICKS, 0xffffffff);

	return 0;
err:
	timer_of_cleanup(&to);
	return ret;
}

static int __init mtk_gpt_init(struct device_node *node)
{
	int ret;

	to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
	to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
	to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
	to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
	to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
	to.of_irq.handler = mtk_gpt_interrupt;

	ret = timer_of_init(node, &to);
	if (ret)
		goto err;

	/* Configure clock source */
	mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
	clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
			      node->name, timer_of_rate(&to), 300, 32,
			      clocksource_mmio_readl_up);
	gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
	sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));

	/* Configure clock event */
	mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
					TIMER_SYNC_TICKS, 0xffffffff);

	mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);

	return 0;
err:
	timer_of_cleanup(&to);
	return ret;
}
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
Commit	Line	Data
ecb3530d MB	1	/*
	2	* Mediatek SoCs General-Purpose Timer handling.
	3	*
	4	* Copyright (C) 2014 Matthias Brugger
	5	*
	6	* Matthias Brugger <matthias.bgg@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
9a78ec45 AK	19	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a78ec45 AK	20
ecb3530d	21	#include <linux/clockchips.h>
a0858f93	22	#include <linux/clocksource.h>
ecb3530d	23	#include <linux/interrupt.h>
ecb3530d	24	#include <linux/irqreturn.h>
f14665f6	25	#include <linux/sched_clock.h>
ecb3530d	26	#include <linux/slab.h>
a0858f93	27	#include "timer-of.h"
ecb3530d	28
56d52d3f SC	29	#define TIMER_CLK_EVT (1)
	30	#define TIMER_CLK_SRC (2)
	31
	32	#define TIMER_SYNC_TICKS (3)
	33
	34	/* gpt */
	35	#define GPT_IRQ_EN_REG 0x00
	36	#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
	37	#define GPT_IRQ_ACK_REG 0x08
	38	#define GPT_IRQ_ACK(val) BIT((val) - 1)
	39
	40	#define GPT_CTRL_REG(val) (0x10 * (val))
	41	#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
	42	#define GPT_CTRL_OP_ONESHOT (0)
	43	#define GPT_CTRL_OP_REPEAT (1)
	44	#define GPT_CTRL_OP_FREERUN (3)
	45	#define GPT_CTRL_CLEAR (2)
	46	#define GPT_CTRL_ENABLE (1)
	47	#define GPT_CTRL_DISABLE (0)
	48
	49	#define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
	50	#define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
	51	#define GPT_CLK_SRC_SYS13M (0)
	52	#define GPT_CLK_SRC_RTC32K (1)
	53	#define GPT_CLK_DIV1 (0x0)
	54	#define GPT_CLK_DIV2 (0x1)
	55
	56	#define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
	57	#define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
ecb3530d	58
e3af6776 SC	59	/* system timer */
	60	#define SYST_BASE (0x40)
	61
	62	#define SYST_CON (SYST_BASE + 0x0)
	63	#define SYST_VAL (SYST_BASE + 0x4)
	64
	65	#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
	66	#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
	67
	68	/*
	69	* SYST_CON_EN: Clock enable. Shall be set to
	70	* - Start timer countdown.
	71	* - Allow timeout ticks being updated.
	72	* - Allow changing interrupt functions.
	73	*
	74	* SYST_CON_IRQ_EN: Set to allow interrupt.
	75	*
	76	* SYST_CON_IRQ_CLR: Set to clear interrupt.
	77	*/
	78	#define SYST_CON_EN BIT(0)
	79	#define SYST_CON_IRQ_EN BIT(1)
	80	#define SYST_CON_IRQ_CLR BIT(4)
	81
f14665f6 YC	82	static void __iomem *gpt_sched_reg __read_mostly;
f14665f6 YC	83
e3af6776 SC	84	static void mtk_syst_ack_irq(struct timer_of *to)
	85	{
	86	/* Clear and disable interrupt */
	87	writel(SYST_CON_IRQ_CLR \| SYST_CON_EN, SYST_CON_REG(to));
	88	}
	89
	90	static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
	91	{
	92	struct clock_event_device *clkevt = dev_id;
	93	struct timer_of *to = to_timer_of(clkevt);
	94
	95	mtk_syst_ack_irq(to);
	96	clkevt->event_handler(clkevt);
	97
	98	return IRQ_HANDLED;
	99	}
	100
	101	static int mtk_syst_clkevt_next_event(unsigned long ticks,
	102	struct clock_event_device *clkevt)
	103	{
	104	struct timer_of *to = to_timer_of(clkevt);
	105
	106	/* Enable clock to allow timeout tick update later */
	107	writel(SYST_CON_EN, SYST_CON_REG(to));
	108
	109	/*
	110	* Write new timeout ticks. Timer shall start countdown
	111	* after timeout ticks are updated.
	112	*/
	113	writel(ticks, SYST_VAL_REG(to));
	114
	115	/* Enable interrupt */
	116	writel(SYST_CON_EN \| SYST_CON_IRQ_EN, SYST_CON_REG(to));
	117
	118	return 0;
	119	}
	120
	121	static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
	122	{
	123	/* Disable timer */
	124	writel(0, SYST_CON_REG(to_timer_of(clkevt)));
	125
	126	return 0;
	127	}
	128
	129	static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
	130	{
	131	return mtk_syst_clkevt_shutdown(clkevt);
	132	}
	133
	134	static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
	135	{
	136	return 0;
	137	}
	138
56d52d3f	139	static u64 notrace mtk_gpt_read_sched_clock(void)
f14665f6 YC	140	{
	141	return readl_relaxed(gpt_sched_reg);
	142	}
	143
a0858f93	144	static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
ecb3530d MB	145	{
	146	u32 val;
	147
a0858f93 SC	148	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
	149	writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
	150	GPT_CTRL_REG(timer));
ecb3530d MB	151	}
ecb3530d MB	152
a0858f93 SC	153	static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
a0858f93 SC	154	unsigned long delay, u8 timer)
ecb3530d	155	{
a0858f93	156	writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
ecb3530d MB	157	}
ecb3530d MB	158
a0858f93 SC	159	static void mtk_gpt_clkevt_time_start(struct timer_of *to,
a0858f93 SC	160	bool periodic, u8 timer)
ecb3530d MB	161	{
	162	u32 val;
	163
	164	/* Acknowledge interrupt */
a0858f93	165	writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
ecb3530d	166
a0858f93	167	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
ecb3530d MB	168
ecb3530d MB	169	/* Clear 2 bit timer operation mode field */
56d52d3f	170	val &= ~GPT_CTRL_OP(0x3);
ecb3530d MB	171
ecb3530d MB	172	if (periodic)
56d52d3f	173	val \|= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
ecb3530d	174	else
56d52d3f	175	val \|= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
ecb3530d	176
56d52d3f	177	writel(val \| GPT_CTRL_ENABLE \| GPT_CTRL_CLEAR,
a0858f93	178	timer_of_base(to) + GPT_CTRL_REG(timer));
ecb3530d MB	179	}
ecb3530d MB	180
56d52d3f	181	static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
a2b7e10d	182	{
a0858f93 SC	183	mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
a0858f93 SC	184
a2b7e10d VK	185	return 0;
	186	}
	187
56d52d3f	188	static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
ecb3530d	189	{
a0858f93 SC	190	struct timer_of *to = to_timer_of(clk);
	191
	192	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
	193	mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
	194	mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
ecb3530d	195
a2b7e10d	196	return 0;
ecb3530d MB	197	}
ecb3530d MB	198
56d52d3f	199	static int mtk_gpt_clkevt_next_event(unsigned long event,
a0858f93	200	struct clock_event_device *clk)
ecb3530d	201	{
a0858f93	202	struct timer_of *to = to_timer_of(clk);
ecb3530d	203
a0858f93 SC	204	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
	205	mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
	206	mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
ecb3530d MB	207
	208	return 0;
	209	}
	210
56d52d3f	211	static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
ecb3530d	212	{
a0858f93 SC	213	struct clock_event_device clkevt = (struct clock_event_device )dev_id;
a0858f93 SC	214	struct timer_of *to = to_timer_of(clkevt);
ecb3530d MB	215
ecb3530d MB	216	/* Acknowledge timer0 irq */
a0858f93 SC	217	writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
a0858f93 SC	218	clkevt->event_handler(clkevt);
ecb3530d MB	219
	220	return IRQ_HANDLED;
	221	}
	222
ecb3530d	223	static void
a0858f93	224	__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
ecb3530d	225	{
56d52d3f	226	writel(GPT_CTRL_CLEAR \| GPT_CTRL_DISABLE,
a0858f93	227	timer_of_base(to) + GPT_CTRL_REG(timer));
ecb3530d	228
56d52d3f	229	writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) \| GPT_CLK_DIV1,
a0858f93	230	timer_of_base(to) + GPT_CLK_REG(timer));
ecb3530d	231
a0858f93	232	writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
ecb3530d	233
56d52d3f	234	writel(GPT_CTRL_OP(option) \| GPT_CTRL_ENABLE,
a0858f93	235	timer_of_base(to) + GPT_CTRL_REG(timer));
ecb3530d MB	236	}
ecb3530d MB	237
a0858f93	238	static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
ecb3530d MB	239	{
	240	u32 val;
	241
fc686d00	242	/* Disable all interrupts */
a0858f93	243	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
fc686d00 DL	244
fc686d00 DL	245	/* Acknowledge all spurious pending interrupts */
a0858f93	246	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
fc686d00	247
a0858f93	248	val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
ecb3530d	249	writel(val \| GPT_IRQ_ENABLE(timer),
a0858f93	250	timer_of_base(to) + GPT_IRQ_EN_REG);
ecb3530d MB	251	}
ecb3530d MB	252
a0858f93 SC	253	static struct timer_of to = {
	254	.flags = TIMER_OF_IRQ \| TIMER_OF_BASE \| TIMER_OF_CLOCK,
	255
	256	.clkevt = {
	257	.name = "mtk-clkevt",
	258	.rating = 300,
	259	.cpumask = cpu_possible_mask,
	260	},
	261
	262	.of_irq = {
	263	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	264	},
	265	};
	266
e3af6776 SC	267	static int __init mtk_syst_init(struct device_node *node)
	268	{
	269	int ret;
	270
	271	to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ \| CLOCK_EVT_FEAT_ONESHOT;
	272	to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
	273	to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
	274	to.clkevt.tick_resume = mtk_syst_clkevt_resume;
	275	to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
	276	to.of_irq.handler = mtk_syst_handler;
	277
	278	ret = timer_of_init(node, &to);
	279	if (ret)
	280	goto err;
	281
	282	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
	283	TIMER_SYNC_TICKS, 0xffffffff);
	284
	285	return 0;
	286	err:
	287	timer_of_cleanup(&to);
	288	return ret;
	289	}
	290
56d52d3f	291	static int __init mtk_gpt_init(struct device_node *node)
ecb3530d	292	{
a0858f93 SC	293	int ret;
	294
	295	to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	296	to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
	297	to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
	298	to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
	299	to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
	300	to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
	301	to.of_irq.handler = mtk_gpt_interrupt;
	302
	303	ret = timer_of_init(node, &to);
	304	if (ret)
	305	goto err;
ecb3530d	306
ecb3530d	307	/* Configure clock source */
a0858f93 SC	308	mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
	309	clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
	310	node->name, timer_of_rate(&to), 300, 32,
	311	clocksource_mmio_readl_up);
	312	gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
	313	sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
ecb3530d MB	314
ecb3530d MB	315	/* Configure clock event */
a0858f93 SC	316	mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
	317	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
	318	TIMER_SYNC_TICKS, 0xffffffff);
d4a19eb3	319
a0858f93	320	mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
d4a19eb3	321
d64e24ce	322	return 0;
a0858f93 SC	323	err:
	324	timer_of_cleanup(&to);
	325	return ret;
ecb3530d	326	}
56d52d3f	327	TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
e3af6776	328	TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);