[linux-2.6-block.git] / drivers / clocksource / timer-mediatek.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Mediatek SoCs General-Purpose Timer handling.
 *
 * Copyright (C) 2014 Matthias Brugger
 *
 * Matthias Brugger <matthias.bgg@gmail.com>
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
#include "timer-of.h"

#define TIMER_CLK_EVT           (1)
#define TIMER_CLK_SRC           (2)

#define TIMER_SYNC_TICKS        (3)

/* gpt */
#define GPT_IRQ_EN_REG          0x00
#define GPT_IRQ_ENABLE(val)     BIT((val) - 1)
#define GPT_IRQ_ACK_REG	        0x08
#define GPT_IRQ_ACK(val)        BIT((val) - 1)

#define GPT_CTRL_REG(val)       (0x10 * (val))
#define GPT_CTRL_OP(val)        (((val) & 0x3) << 4)
#define GPT_CTRL_OP_ONESHOT     (0)
#define GPT_CTRL_OP_REPEAT      (1)
#define GPT_CTRL_OP_FREERUN     (3)
#define GPT_CTRL_CLEAR          (2)
#define GPT_CTRL_ENABLE         (1)
#define GPT_CTRL_DISABLE        (0)

#define GPT_CLK_REG(val)        (0x04 + (0x10 * (val)))
#define GPT_CLK_SRC(val)        (((val) & 0x1) << 4)
#define GPT_CLK_SRC_SYS13M      (0)
#define GPT_CLK_SRC_RTC32K      (1)
#define GPT_CLK_DIV1            (0x0)
#define GPT_CLK_DIV2            (0x1)

#define GPT_CNT_REG(val)        (0x08 + (0x10 * (val)))
#define GPT_CMP_REG(val)        (0x0C + (0x10 * (val)))

/* system timer */
#define SYST_BASE               (0x40)

#define SYST_CON                (SYST_BASE + 0x0)
#define SYST_VAL                (SYST_BASE + 0x4)

#define SYST_CON_REG(to)        (timer_of_base(to) + SYST_CON)
#define SYST_VAL_REG(to)        (timer_of_base(to) + SYST_VAL)

/*
 * SYST_CON_EN: Clock enable. Shall be set to
 *   - Start timer countdown.
 *   - Allow timeout ticks being updated.
 *   - Allow changing interrupt status,like clear irq pending.
 *
 * SYST_CON_IRQ_EN: Set to enable interrupt.
 *
 * SYST_CON_IRQ_CLR: Set to clear interrupt.
 */
#define SYST_CON_EN              BIT(0)
#define SYST_CON_IRQ_EN          BIT(1)
#define SYST_CON_IRQ_CLR         BIT(4)

static void __iomem *gpt_sched_reg __read_mostly;

static void mtk_syst_ack_irq(struct timer_of *to)
{
	/* Clear and disable interrupt */
	writel(SYST_CON_EN, SYST_CON_REG(to));
	writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
}

static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
{
	struct clock_event_device *clkevt = dev_id;
	struct timer_of *to = to_timer_of(clkevt);

	mtk_syst_ack_irq(to);
	clkevt->event_handler(clkevt);

	return IRQ_HANDLED;
}

static int mtk_syst_clkevt_next_event(unsigned long ticks,
				      struct clock_event_device *clkevt)
{
	struct timer_of *to = to_timer_of(clkevt);

	/* Enable clock to allow timeout tick update later */
	writel(SYST_CON_EN, SYST_CON_REG(to));

	/*
	 * Write new timeout ticks. Timer shall start countdown
	 * after timeout ticks are updated.
	 */
	writel(ticks, SYST_VAL_REG(to));

	/* Enable interrupt */
	writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));

	return 0;
}

static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
{
	/* Clear any irq */
	mtk_syst_ack_irq(to_timer_of(clkevt));

	/* Disable timer */
	writel(0, SYST_CON_REG(to_timer_of(clkevt)));

	return 0;
}

static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
{
	return mtk_syst_clkevt_shutdown(clkevt);
}

static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
{
	return 0;
}

static u64 notrace mtk_gpt_read_sched_clock(void)
{
	return readl_relaxed(gpt_sched_reg);
}

static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
{
	u32 val;

	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
	writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
	       GPT_CTRL_REG(timer));
}

static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
				      unsigned long delay, u8 timer)
{
	writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
}

static void mtk_gpt_clkevt_time_start(struct timer_of *to,
				      bool periodic, u8 timer)
{
	u32 val;

	/* Acknowledge interrupt */
	writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);

	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));

	/* Clear 2 bit timer operation mode field */
	val &= ~GPT_CTRL_OP(0x3);

	if (periodic)
		val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
	else
		val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);

	writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
	       timer_of_base(to) + GPT_CTRL_REG(timer));
}

static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
{
	mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);

	return 0;
}

static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);

	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
	mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
	mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);

	return 0;
}

static int mtk_gpt_clkevt_next_event(unsigned long event,
				     struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);

	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
	mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
	mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);

	return 0;
}

static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
	struct timer_of *to = to_timer_of(clkevt);

	/* Acknowledge timer0 irq */
	writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
	clkevt->event_handler(clkevt);

	return IRQ_HANDLED;
}

static void
__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
{
	writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
	       timer_of_base(to) + GPT_CTRL_REG(timer));

	writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
	       timer_of_base(to) + GPT_CLK_REG(timer));

	writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));

	writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
	       timer_of_base(to) + GPT_CTRL_REG(timer));
}

static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
{
	u32 val;

	/* Disable all interrupts */
	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);

	/* Acknowledge all spurious pending interrupts */
	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);

	val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
	writel(val | GPT_IRQ_ENABLE(timer),
	       timer_of_base(to) + GPT_IRQ_EN_REG);
}

static void mtk_gpt_resume(struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);

	mtk_gpt_enable_irq(to, TIMER_CLK_EVT);
}

static void mtk_gpt_suspend(struct clock_event_device *clk)
{
	struct timer_of *to = to_timer_of(clk);

	/* Disable all interrupts */
	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);

	/*
	 * This is called with interrupts disabled,
	 * so we need to ack any interrupt that is pending
	 * or for example ATF will prevent a suspend from completing.
	 */
	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
}

static struct timer_of to = {
	.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,

	.clkevt = {
		.name = "mtk-clkevt",
		.rating = 300,
		.cpumask = cpu_possible_mask,
	},

	.of_irq = {
		.flags = IRQF_TIMER | IRQF_IRQPOLL,
	},
};

static int __init mtk_syst_init(struct device_node *node)
{
	int ret;

	to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
	to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
	to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
	to.clkevt.tick_resume = mtk_syst_clkevt_resume;
	to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
	to.of_irq.handler = mtk_syst_handler;

	ret = timer_of_init(node, &to);
	if (ret)
		return ret;

	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
					TIMER_SYNC_TICKS, 0xffffffff);

	return 0;
}

static int __init mtk_gpt_init(struct device_node *node)
{
	int ret;

	to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
	to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
	to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
	to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
	to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
	to.clkevt.suspend = mtk_gpt_suspend;
	to.clkevt.resume = mtk_gpt_resume;
	to.of_irq.handler = mtk_gpt_interrupt;

	ret = timer_of_init(node, &to);
	if (ret)
		return ret;

	/* Configure clock source */
	mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
	clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
			      node->name, timer_of_rate(&to), 300, 32,
			      clocksource_mmio_readl_up);
	gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
	sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));

	/* Configure clock event */
	mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
					TIMER_SYNC_TICKS, 0xffffffff);

	mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);

	return 0;
}
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
ecb3530d MB	2	/*
	3	* Mediatek SoCs General-Purpose Timer handling.
	4	*
	5	* Copyright (C) 2014 Matthias Brugger
	6	*
	7	* Matthias Brugger <matthias.bgg@gmail.com>
ecb3530d MB	8	*/
ecb3530d MB	9
9a78ec45 AK	10	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a78ec45 AK	11
ecb3530d	12	#include <linux/clockchips.h>
a0858f93	13	#include <linux/clocksource.h>
ecb3530d	14	#include <linux/interrupt.h>
ecb3530d	15	#include <linux/irqreturn.h>
f14665f6	16	#include <linux/sched_clock.h>
ecb3530d	17	#include <linux/slab.h>
a0858f93	18	#include "timer-of.h"
ecb3530d	19
56d52d3f SC	20	#define TIMER_CLK_EVT (1)
	21	#define TIMER_CLK_SRC (2)
	22
	23	#define TIMER_SYNC_TICKS (3)
	24
	25	/* gpt */
	26	#define GPT_IRQ_EN_REG 0x00
	27	#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
	28	#define GPT_IRQ_ACK_REG 0x08
	29	#define GPT_IRQ_ACK(val) BIT((val) - 1)
	30
	31	#define GPT_CTRL_REG(val) (0x10 * (val))
	32	#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
	33	#define GPT_CTRL_OP_ONESHOT (0)
	34	#define GPT_CTRL_OP_REPEAT (1)
	35	#define GPT_CTRL_OP_FREERUN (3)
	36	#define GPT_CTRL_CLEAR (2)
	37	#define GPT_CTRL_ENABLE (1)
	38	#define GPT_CTRL_DISABLE (0)
	39
	40	#define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
	41	#define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
	42	#define GPT_CLK_SRC_SYS13M (0)
	43	#define GPT_CLK_SRC_RTC32K (1)
	44	#define GPT_CLK_DIV1 (0x0)
	45	#define GPT_CLK_DIV2 (0x1)
	46
	47	#define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
	48	#define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
ecb3530d	49
e3af6776 SC	50	/* system timer */
	51	#define SYST_BASE (0x40)
	52
	53	#define SYST_CON (SYST_BASE + 0x0)
	54	#define SYST_VAL (SYST_BASE + 0x4)
	55
	56	#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
	57	#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
	58
	59	/*
	60	* SYST_CON_EN: Clock enable. Shall be set to
	61	* - Start timer countdown.
	62	* - Allow timeout ticks being updated.
ce957065	63	* - Allow changing interrupt status,like clear irq pending.
e3af6776	64	*
ce957065	65	* SYST_CON_IRQ_EN: Set to enable interrupt.
e3af6776 SC	66	*
	67	* SYST_CON_IRQ_CLR: Set to clear interrupt.
	68	*/
	69	#define SYST_CON_EN BIT(0)
	70	#define SYST_CON_IRQ_EN BIT(1)
	71	#define SYST_CON_IRQ_CLR BIT(4)
	72
f14665f6 YC	73	static void __iomem *gpt_sched_reg __read_mostly;
f14665f6 YC	74
e3af6776 SC	75	static void mtk_syst_ack_irq(struct timer_of *to)
	76	{
	77	/* Clear and disable interrupt */
ce957065	78	writel(SYST_CON_EN, SYST_CON_REG(to));
e3af6776 SC	79	writel(SYST_CON_IRQ_CLR \| SYST_CON_EN, SYST_CON_REG(to));
	80	}
	81
	82	static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
	83	{
	84	struct clock_event_device *clkevt = dev_id;
	85	struct timer_of *to = to_timer_of(clkevt);
	86
	87	mtk_syst_ack_irq(to);
	88	clkevt->event_handler(clkevt);
	89
	90	return IRQ_HANDLED;
	91	}
	92
	93	static int mtk_syst_clkevt_next_event(unsigned long ticks,
	94	struct clock_event_device *clkevt)
	95	{
	96	struct timer_of *to = to_timer_of(clkevt);
	97
	98	/* Enable clock to allow timeout tick update later */
	99	writel(SYST_CON_EN, SYST_CON_REG(to));
	100
	101	/*
	102	* Write new timeout ticks. Timer shall start countdown
	103	* after timeout ticks are updated.
	104	*/
	105	writel(ticks, SYST_VAL_REG(to));
	106
	107	/* Enable interrupt */
	108	writel(SYST_CON_EN \| SYST_CON_IRQ_EN, SYST_CON_REG(to));
	109
	110	return 0;
	111	}
	112
	113	static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
	114	{
ce957065 FC	115	/* Clear any irq */
	116	mtk_syst_ack_irq(to_timer_of(clkevt));
	117
e3af6776 SC	118	/* Disable timer */
	119	writel(0, SYST_CON_REG(to_timer_of(clkevt)));
	120
	121	return 0;
	122	}
	123
	124	static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
	125	{
	126	return mtk_syst_clkevt_shutdown(clkevt);
	127	}
	128
	129	static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
	130	{
	131	return 0;
	132	}
	133
56d52d3f	134	static u64 notrace mtk_gpt_read_sched_clock(void)
f14665f6 YC	135	{
	136	return readl_relaxed(gpt_sched_reg);
	137	}
	138
a0858f93	139	static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
ecb3530d MB	140	{
	141	u32 val;
	142
a0858f93 SC	143	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
	144	writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
	145	GPT_CTRL_REG(timer));
ecb3530d MB	146	}
ecb3530d MB	147
a0858f93 SC	148	static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
a0858f93 SC	149	unsigned long delay, u8 timer)
ecb3530d	150	{
a0858f93	151	writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
ecb3530d MB	152	}
ecb3530d MB	153
a0858f93 SC	154	static void mtk_gpt_clkevt_time_start(struct timer_of *to,
a0858f93 SC	155	bool periodic, u8 timer)
ecb3530d MB	156	{
	157	u32 val;
	158
	159	/* Acknowledge interrupt */
a0858f93	160	writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
ecb3530d	161
a0858f93	162	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
ecb3530d MB	163
ecb3530d MB	164	/* Clear 2 bit timer operation mode field */
56d52d3f	165	val &= ~GPT_CTRL_OP(0x3);
ecb3530d MB	166
ecb3530d MB	167	if (periodic)
56d52d3f	168	val \|= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
ecb3530d	169	else
56d52d3f	170	val \|= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
ecb3530d	171
56d52d3f	172	writel(val \| GPT_CTRL_ENABLE \| GPT_CTRL_CLEAR,
a0858f93	173	timer_of_base(to) + GPT_CTRL_REG(timer));
ecb3530d MB	174	}
ecb3530d MB	175
56d52d3f	176	static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
a2b7e10d	177	{
a0858f93 SC	178	mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
a0858f93 SC	179
a2b7e10d VK	180	return 0;
	181	}
	182
56d52d3f	183	static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
ecb3530d	184	{
a0858f93 SC	185	struct timer_of *to = to_timer_of(clk);
	186
	187	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
	188	mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
	189	mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
ecb3530d	190
a2b7e10d	191	return 0;
ecb3530d MB	192	}
ecb3530d MB	193
56d52d3f	194	static int mtk_gpt_clkevt_next_event(unsigned long event,
a0858f93	195	struct clock_event_device *clk)
ecb3530d	196	{
a0858f93	197	struct timer_of *to = to_timer_of(clk);
ecb3530d	198
a0858f93 SC	199	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
	200	mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
	201	mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
ecb3530d MB	202
	203	return 0;
	204	}
	205
56d52d3f	206	static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
ecb3530d	207	{
a0858f93 SC	208	struct clock_event_device clkevt = (struct clock_event_device )dev_id;
a0858f93 SC	209	struct timer_of *to = to_timer_of(clkevt);
ecb3530d MB	210
ecb3530d MB	211	/* Acknowledge timer0 irq */
a0858f93 SC	212	writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
a0858f93 SC	213	clkevt->event_handler(clkevt);
ecb3530d MB	214
	215	return IRQ_HANDLED;
	216	}
	217
ecb3530d	218	static void
a0858f93	219	__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
ecb3530d	220	{
56d52d3f	221	writel(GPT_CTRL_CLEAR \| GPT_CTRL_DISABLE,
a0858f93	222	timer_of_base(to) + GPT_CTRL_REG(timer));
ecb3530d	223
56d52d3f	224	writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) \| GPT_CLK_DIV1,
a0858f93	225	timer_of_base(to) + GPT_CLK_REG(timer));
ecb3530d	226
a0858f93	227	writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
ecb3530d	228
56d52d3f	229	writel(GPT_CTRL_OP(option) \| GPT_CTRL_ENABLE,
a0858f93	230	timer_of_base(to) + GPT_CTRL_REG(timer));
ecb3530d MB	231	}
ecb3530d MB	232
a0858f93	233	static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
ecb3530d MB	234	{
	235	u32 val;
	236
fc686d00	237	/* Disable all interrupts */
a0858f93	238	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
fc686d00 DL	239
fc686d00 DL	240	/* Acknowledge all spurious pending interrupts */
a0858f93	241	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
fc686d00	242
a0858f93	243	val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
ecb3530d	244	writel(val \| GPT_IRQ_ENABLE(timer),
a0858f93	245	timer_of_base(to) + GPT_IRQ_EN_REG);
ecb3530d MB	246	}
ecb3530d MB	247
75ac5cc2 EB	248	static void mtk_gpt_resume(struct clock_event_device *clk)
	249	{
	250	struct timer_of *to = to_timer_of(clk);
	251
	252	mtk_gpt_enable_irq(to, TIMER_CLK_EVT);
	253	}
	254
	255	static void mtk_gpt_suspend(struct clock_event_device *clk)
	256	{
	257	struct timer_of *to = to_timer_of(clk);
	258
	259	/* Disable all interrupts */
	260	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
	261
	262	/*
	263	* This is called with interrupts disabled,
	264	* so we need to ack any interrupt that is pending
	265	* or for example ATF will prevent a suspend from completing.
	266	*/
	267	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
	268	}
	269
a0858f93 SC	270	static struct timer_of to = {
	271	.flags = TIMER_OF_IRQ \| TIMER_OF_BASE \| TIMER_OF_CLOCK,
	272
	273	.clkevt = {
	274	.name = "mtk-clkevt",
	275	.rating = 300,
	276	.cpumask = cpu_possible_mask,
	277	},
	278
	279	.of_irq = {
	280	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	281	},
	282	};
	283
e3af6776 SC	284	static int __init mtk_syst_init(struct device_node *node)
	285	{
	286	int ret;
	287
	288	to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ \| CLOCK_EVT_FEAT_ONESHOT;
	289	to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
	290	to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
	291	to.clkevt.tick_resume = mtk_syst_clkevt_resume;
	292	to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
	293	to.of_irq.handler = mtk_syst_handler;
	294
	295	ret = timer_of_init(node, &to);
	296	if (ret)
41d49e79	297	return ret;
e3af6776 SC	298
	299	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
	300	TIMER_SYNC_TICKS, 0xffffffff);
	301
	302	return 0;
e3af6776 SC	303	}
e3af6776 SC	304
56d52d3f	305	static int __init mtk_gpt_init(struct device_node *node)
ecb3530d	306	{
a0858f93 SC	307	int ret;
	308
	309	to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	310	to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
	311	to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
	312	to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
	313	to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
	314	to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
75ac5cc2 EB	315	to.clkevt.suspend = mtk_gpt_suspend;
75ac5cc2 EB	316	to.clkevt.resume = mtk_gpt_resume;
a0858f93 SC	317	to.of_irq.handler = mtk_gpt_interrupt;
	318
	319	ret = timer_of_init(node, &to);
	320	if (ret)
41d49e79	321	return ret;
ecb3530d	322
ecb3530d	323	/* Configure clock source */
a0858f93 SC	324	mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
	325	clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
	326	node->name, timer_of_rate(&to), 300, 32,
	327	clocksource_mmio_readl_up);
	328	gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
	329	sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
ecb3530d MB	330
ecb3530d MB	331	/* Configure clock event */
a0858f93 SC	332	mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
	333	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
	334	TIMER_SYNC_TICKS, 0xffffffff);
d4a19eb3	335
a0858f93	336	mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
d4a19eb3	337
d64e24ce	338	return 0;
ecb3530d	339	}
56d52d3f	340	TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
e3af6776	341	TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);