[linux-2.6-block.git] / drivers / clocksource / timer-marco.c

/*
 * System timer for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/sched_clock.h>
#include <asm/mach/time.h>

#define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
#define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
#define SIRFSOC_TIMER_MATCH_0				0x0018
#define SIRFSOC_TIMER_MATCH_1				0x001c
#define SIRFSOC_TIMER_COUNTER_0				0x0048
#define SIRFSOC_TIMER_COUNTER_1				0x004c
#define SIRFSOC_TIMER_INTR_STATUS			0x0060
#define SIRFSOC_TIMER_WATCHDOG_EN			0x0064
#define SIRFSOC_TIMER_64COUNTER_CTRL			0x0068
#define SIRFSOC_TIMER_64COUNTER_LO			0x006c
#define SIRFSOC_TIMER_64COUNTER_HI			0x0070
#define SIRFSOC_TIMER_64COUNTER_LOAD_LO			0x0074
#define SIRFSOC_TIMER_64COUNTER_LOAD_HI			0x0078
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO		0x007c
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI		0x0080

#define SIRFSOC_TIMER_REG_CNT 6

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	SIRFSOC_TIMER_WATCHDOG_EN,
	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	SIRFSOC_TIMER_64COUNTER_CTRL,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
};

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

static void __iomem *sirfsoc_timer_base;

/* disable count and interrupt */
static inline void sirfsoc_timer_count_disable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* enable count and interrupt */
static inline void sirfsoc_timer_count_enable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* timer interrupt handler */
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;
	int cpu = smp_processor_id();

	/* clear timer interrupt */
	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
		sirfsoc_timer_count_disable(cpu);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

/* read 64-bit timer counter */
static cycle_t sirfsoc_timer_read(struct clocksource *cs)
{
	u64 cycles;

	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);

	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);

	return cycles;
}

static int sirfsoc_timer_set_next_event(unsigned long delta,
	struct clock_event_device *ce)
{
	int cpu = smp_processor_id();

	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
		4 * cpu);
	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
		4 * cpu);

	/* enable the tick */
	sirfsoc_timer_count_enable(cpu);

	return 0;
}

static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
	struct clock_event_device *ce)
{
	switch (mode) {
	case CLOCK_EVT_MODE_ONESHOT:
		/* enable in set_next_event */
		break;
	default:
		break;
	}

	sirfsoc_timer_count_disable(smp_processor_id());
}

static void sirfsoc_clocksource_suspend(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
}

static void sirfsoc_clocksource_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);

	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
}

static struct clock_event_device __percpu *sirfsoc_clockevent;

static struct clocksource sirfsoc_clocksource = {
	.name = "sirfsoc_clocksource",
	.rating = 200,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.read = sirfsoc_timer_read,
	.suspend = sirfsoc_clocksource_suspend,
	.resume = sirfsoc_clocksource_resume,
};

static struct irqaction sirfsoc_timer_irq = {
	.name = "sirfsoc_timer0",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static struct irqaction sirfsoc_timer1_irq = {
	.name = "sirfsoc_timer1",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
{
	int cpu = smp_processor_id();
	struct irqaction *action;

	if (cpu == 0)
		action = &sirfsoc_timer_irq;
	else
		action = &sirfsoc_timer1_irq;

	ce->irq = action->irq;
	ce->name = "local_timer";
	ce->features = CLOCK_EVT_FEAT_ONESHOT;
	ce->rating = 200;
	ce->set_mode = sirfsoc_timer_set_mode;
	ce->set_next_event = sirfsoc_timer_set_next_event;
	clockevents_calc_mult_shift(ce, CLOCK_TICK_RATE, 60);
	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
	ce->min_delta_ns = clockevent_delta2ns(2, ce);
	ce->cpumask = cpumask_of(cpu);

	action->dev_id = ce;
	BUG_ON(setup_irq(ce->irq, action));
	irq_set_affinity(action->irq, cpumask_of(cpu));

	clockevents_register_device(ce);
	return 0;
}

static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
{
	int cpu = smp_processor_id();

	sirfsoc_timer_count_disable(1);

	if (cpu == 0)
		remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	else
		remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
}

static int sirfsoc_cpu_notify(struct notifier_block *self,
			      unsigned long action, void *hcpu)
{
	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
		break;
	case CPU_DYING:
		sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block sirfsoc_cpu_nb = {
	.notifier_call = sirfsoc_cpu_notify,
};

static void __init sirfsoc_clockevent_init(void)
{
	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	BUG_ON(!sirfsoc_clockevent);

	BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));

	/* Immediately configure the timer on the boot CPU */
	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
}

/* initialize the kernel jiffy timer source */
static void __init sirfsoc_marco_timer_init(void)
{
	unsigned long rate;
	u32 timer_div;
	struct clk *clk;

	/* timer's input clock is io clock */
	clk = clk_get_sys("io", NULL);

	BUG_ON(IS_ERR(clk));
	rate = clk_get_rate(clk);

	BUG_ON(rate < CLOCK_TICK_RATE);
	BUG_ON(rate % CLOCK_TICK_RATE);

	/* Initialize the timer dividers */
	timer_div = rate / CLOCK_TICK_RATE - 1;
	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);

	/* Initialize timer counters to 0 */
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);

	/* Clear all interrupts */
	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));

	sirfsoc_clockevent_init();
}

static void __init sirfsoc_of_timer_init(struct device_node *np)
{
	sirfsoc_timer_base = of_iomap(np, 0);
	if (!sirfsoc_timer_base)
		panic("unable to map timer cpu registers\n");

	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
	if (!sirfsoc_timer_irq.irq)
		panic("No irq passed for timer0 via DT\n");

	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
	if (!sirfsoc_timer1_irq.irq)
		panic("No irq passed for timer1 via DT\n");

	sirfsoc_marco_timer_init();
}
CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );
Commit	Line	Data
4898de3d BS	1	/*
	2	* System timer for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/clocksource.h>
05a65485	13	#include <linux/cpu.h>
4898de3d BS	14	#include <linux/bitops.h>
	15	#include <linux/irq.h>
	16	#include <linux/clk.h>
	17	#include <linux/slab.h>
	18	#include <linux/of.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/of_address.h>
38ff87f7	21	#include <linux/sched_clock.h>
4898de3d BS	22	#include <asm/mach/time.h>
4898de3d BS	23
4898de3d BS	24	#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
	25	#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
	26	#define SIRFSOC_TIMER_MATCH_0 0x0018
	27	#define SIRFSOC_TIMER_MATCH_1 0x001c
	28	#define SIRFSOC_TIMER_COUNTER_0 0x0048
	29	#define SIRFSOC_TIMER_COUNTER_1 0x004c
	30	#define SIRFSOC_TIMER_INTR_STATUS 0x0060
	31	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
	32	#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
	33	#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
	34	#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
	35	#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
	36	#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
	37	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
	38	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
	39
	40	#define SIRFSOC_TIMER_REG_CNT 6
	41
	42	static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	43	SIRFSOC_TIMER_WATCHDOG_EN,
	44	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	45	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	46	SIRFSOC_TIMER_64COUNTER_CTRL,
	47	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	48	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
	49	};
	50
	51	static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
	52
	53	static void __iomem *sirfsoc_timer_base;
4898de3d BS	54
	55	/* disable count and interrupt */
	56	static inline void sirfsoc_timer_count_disable(int idx)
	57	{
	58	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
	59	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	60	}
	61
	62	/* enable count and interrupt */
	63	static inline void sirfsoc_timer_count_enable(int idx)
	64	{
	65	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) \| 0x7,
	66	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	67	}
	68
	69	/* timer interrupt handler */
	70	static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
	71	{
	72	struct clock_event_device *ce = dev_id;
	73	int cpu = smp_processor_id();
	74
	75	/* clear timer interrupt */
	76	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	77
	78	if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
	79	sirfsoc_timer_count_disable(cpu);
	80
	81	ce->event_handler(ce);
	82
	83	return IRQ_HANDLED;
	84	}
	85
	86	/* read 64-bit timer counter */
	87	static cycle_t sirfsoc_timer_read(struct clocksource *cs)
	88	{
	89	u64 cycles;
	90
	91	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	92	BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	93
	94	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	95	cycles = (cycles << 32) \| readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
	96
	97	return cycles;
	98	}
	99
	100	static int sirfsoc_timer_set_next_event(unsigned long delta,
	101	struct clock_event_device *ce)
	102	{
	103	int cpu = smp_processor_id();
	104
	105	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
	106	4 * cpu);
	107	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
	108	4 * cpu);
	109
	110	/* enable the tick */
	111	sirfsoc_timer_count_enable(cpu);
	112
	113	return 0;
	114	}
	115
	116	static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
	117	struct clock_event_device *ce)
118	{
119	switch (mode) {
120	case CLOCK_EVT_MODE_ONESHOT:
121	/* enable in set_next_event */
122	break;
123	default:
124	break;
125	}
126
127	sirfsoc_timer_count_disable(smp_processor_id());
128	}
129
130	static void sirfsoc_clocksource_suspend(struct clocksource *cs)
131	{
132	int i;
133
134	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
135	sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
136	}
137
138	static void sirfsoc_clocksource_resume(struct clocksource *cs)
139	{
140	int i;
141
142	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
143	writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
144
145	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
146	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
147	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
148	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
149
150	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
151	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
152	}
153
05a65485	154	static struct clock_event_device __percpu *sirfsoc_clockevent;
4898de3d BS	155
	156	static struct clocksource sirfsoc_clocksource = {
	157	.name = "sirfsoc_clocksource",
	158	.rating = 200,
	159	.mask = CLOCKSOURCE_MASK(64),
	160	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	161	.read = sirfsoc_timer_read,
	162	.suspend = sirfsoc_clocksource_suspend,
	163	.resume = sirfsoc_clocksource_resume,
	164	};
	165
	166	static struct irqaction sirfsoc_timer_irq = {
	167	.name = "sirfsoc_timer0",
	168	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	169	.handler = sirfsoc_timer_interrupt,
4898de3d BS	170	};
4898de3d BS	171
4898de3d BS	172	static struct irqaction sirfsoc_timer1_irq = {
	173	.name = "sirfsoc_timer1",
	174	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	175	.handler = sirfsoc_timer_interrupt,
	176	};
	177
8c37bb3a	178	static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
4898de3d	179	{
05a65485 SB	180	int cpu = smp_processor_id();
	181	struct irqaction *action;
	182
	183	if (cpu == 0)
	184	action = &sirfsoc_timer_irq;
	185	else
	186	action = &sirfsoc_timer1_irq;
4898de3d	187
05a65485	188	ce->irq = action->irq;
4898de3d	189	ce->name = "local_timer";
05a65485 SB	190	ce->features = CLOCK_EVT_FEAT_ONESHOT;
05a65485 SB	191	ce->rating = 200;
4898de3d BS	192	ce->set_mode = sirfsoc_timer_set_mode;
4898de3d BS	193	ce->set_next_event = sirfsoc_timer_set_next_event;
05a65485 SB	194	clockevents_calc_mult_shift(ce, CLOCK_TICK_RATE, 60);
	195	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
	196	ce->min_delta_ns = clockevent_delta2ns(2, ce);
	197	ce->cpumask = cpumask_of(cpu);
4898de3d	198
05a65485 SB	199	action->dev_id = ce;
	200	BUG_ON(setup_irq(ce->irq, action));
	201	irq_set_affinity(action->irq, cpumask_of(cpu));
4898de3d BS	202
	203	clockevents_register_device(ce);
	204	return 0;
	205	}
	206
	207	static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
	208	{
05a65485 SB	209	int cpu = smp_processor_id();
05a65485 SB	210
4898de3d BS	211	sirfsoc_timer_count_disable(1);
4898de3d BS	212
05a65485 SB	213	if (cpu == 0)
	214	remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	215	else
	216	remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
4898de3d BS	217	}
4898de3d BS	218
47dcd356 OJ	219	static int sirfsoc_cpu_notify(struct notifier_block *self,
47dcd356 OJ	220	unsigned long action, void *hcpu)
05a65485 SB	221	{
	222	/*
	223	* Grab cpu pointer in each case to avoid spurious
	224	* preemptible warnings
	225	*/
	226	switch (action & ~CPU_TASKS_FROZEN) {
	227	case CPU_STARTING:
	228	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
	229	break;
	230	case CPU_DYING:
	231	sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
	232	break;
	233	}
	234
	235	return NOTIFY_OK;
	236	}
	237
47dcd356	238	static struct notifier_block sirfsoc_cpu_nb = {
05a65485	239	.notifier_call = sirfsoc_cpu_notify,
4898de3d	240	};
4898de3d BS	241
	242	static void __init sirfsoc_clockevent_init(void)
	243	{
05a65485 SB	244	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	245	BUG_ON(!sirfsoc_clockevent);
	246
	247	BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));
	248
	249	/* Immediately configure the timer on the boot CPU */
	250	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
4898de3d BS	251	}
	252
	253	/* initialize the kernel jiffy timer source */
275786b7	254	static void __init sirfsoc_marco_timer_init(void)
4898de3d BS	255	{
	256	unsigned long rate;
	257	u32 timer_div;
	258	struct clk *clk;
	259
4898de3d BS	260	/* timer's input clock is io clock */
	261	clk = clk_get_sys("io", NULL);
	262
	263	BUG_ON(IS_ERR(clk));
	264	rate = clk_get_rate(clk);
	265
	266	BUG_ON(rate < CLOCK_TICK_RATE);
	267	BUG_ON(rate % CLOCK_TICK_RATE);
	268
4898de3d BS	269	/* Initialize the timer dividers */
	270	timer_div = rate / CLOCK_TICK_RATE - 1;
	271	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	272	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	273	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
	274
	275	/* Initialize timer counters to 0 */
	276	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	277	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	278	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	279	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	280	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	281	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
	282
	283	/* Clear all interrupts */
	284	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	285
	286	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
	287
4898de3d BS	288	sirfsoc_clockevent_init();
	289	}
	290
275786b7	291	static void __init sirfsoc_of_timer_init(struct device_node *np)
4898de3d	292	{
4898de3d BS	293	sirfsoc_timer_base = of_iomap(np, 0);
	294	if (!sirfsoc_timer_base)
	295	panic("unable to map timer cpu registers\n");
	296
	297	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
	298	if (!sirfsoc_timer_irq.irq)
	299	panic("No irq passed for timer0 via DT\n");
	300
4898de3d BS	301	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
	302	if (!sirfsoc_timer1_irq.irq)
	303	panic("No irq passed for timer1 via DT\n");
4898de3d	304
275786b7	305	sirfsoc_marco_timer_init();
4898de3d	306	}
275786b7	307	CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );