[linux-block.git] / drivers / clocksource / timer-imx-sysctr.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2017-2019 NXP

#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/slab.h>

#include "timer-of.h"

#define CMP_OFFSET	0x10000
#define RD_OFFSET	0x20000

#define CNTCV_LO	0x8
#define CNTCV_HI	0xc
#define CMPCV_LO	(CMP_OFFSET + 0x20)
#define CMPCV_HI	(CMP_OFFSET + 0x24)
#define CMPCR		(CMP_OFFSET + 0x2c)
#define CNTCV_LO_IMX95	(RD_OFFSET + 0x8)
#define CNTCV_HI_IMX95	(RD_OFFSET + 0xc)

#define SYS_CTR_EN		0x1
#define SYS_CTR_IRQ_MASK	0x2

#define SYS_CTR_CLK_DIV		0x3

struct sysctr_private {
	u32 cmpcr;
	u32 lo_off;
	u32 hi_off;
};

static void sysctr_timer_enable(struct clock_event_device *evt, bool enable)
{
	struct timer_of *to = to_timer_of(evt);
	struct sysctr_private *priv = to->private_data;
	void __iomem *base = timer_of_base(to);

	writel(enable ? priv->cmpcr | SYS_CTR_EN : priv->cmpcr, base + CMPCR);
}

static void sysctr_irq_acknowledge(struct clock_event_device *evt)
{
	/*
	 * clear the enable bit(EN =0) will clear
	 * the status bit(ISTAT = 0), then the interrupt
	 * signal will be negated(acknowledged).
	 */
	sysctr_timer_enable(evt, false);
}

static inline u64 sysctr_read_counter(struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);
	struct sysctr_private *priv = to->private_data;
	void __iomem *base = timer_of_base(to);
	u32 cnt_hi, tmp_hi, cnt_lo;

	do {
		cnt_hi = readl_relaxed(base + priv->hi_off);
		cnt_lo = readl_relaxed(base + priv->lo_off);
		tmp_hi = readl_relaxed(base + priv->hi_off);
	} while (tmp_hi != cnt_hi);

	return  ((u64) cnt_hi << 32) | cnt_lo;
}

static int sysctr_set_next_event(unsigned long delta,
				 struct clock_event_device *evt)
{
	struct timer_of *to = to_timer_of(evt);
	void __iomem *base = timer_of_base(to);
	u32 cmp_hi, cmp_lo;
	u64 next;

	sysctr_timer_enable(evt, false);

	next = sysctr_read_counter(evt);

	next += delta;

	cmp_hi = (next >> 32) & 0x00fffff;
	cmp_lo = next & 0xffffffff;

	writel_relaxed(cmp_hi, base + CMPCV_HI);
	writel_relaxed(cmp_lo, base + CMPCV_LO);

	sysctr_timer_enable(evt, true);

	return 0;
}

static int sysctr_set_state_oneshot(struct clock_event_device *evt)
{
	return 0;
}

static int sysctr_set_state_shutdown(struct clock_event_device *evt)
{
	sysctr_timer_enable(evt, false);

	return 0;
}

static irqreturn_t sysctr_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	sysctr_irq_acknowledge(evt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct timer_of to_sysctr = {
	.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
	.clkevt = {
		.name			= "i.MX system counter timer",
		.features		= CLOCK_EVT_FEAT_ONESHOT |
						CLOCK_EVT_FEAT_DYNIRQ,
		.set_state_oneshot	= sysctr_set_state_oneshot,
		.set_next_event		= sysctr_set_next_event,
		.set_state_shutdown	= sysctr_set_state_shutdown,
		.rating			= 200,
	},
	.of_irq = {
		.handler		= sysctr_timer_interrupt,
		.flags			= IRQF_TIMER,
	},
	.of_clk = {
		.name = "per",
	},
};

static int __init __sysctr_timer_init(struct device_node *np)
{
	struct sysctr_private *priv;
	void __iomem *base;
	int ret;

	priv = kzalloc(sizeof(struct sysctr_private), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	ret = timer_of_init(np, &to_sysctr);
	if (ret) {
		kfree(priv);
		return ret;
	}

	if (!of_property_read_bool(np, "nxp,no-divider")) {
		/* system counter clock is divided by 3 internally */
		to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
	}

	to_sysctr.clkevt.cpumask = cpu_possible_mask;
	to_sysctr.private_data = priv;

	base = timer_of_base(&to_sysctr);
	priv->cmpcr = readl(base + CMPCR) & ~SYS_CTR_EN;

	return 0;
}

static int __init sysctr_timer_init(struct device_node *np)
{
	struct sysctr_private *priv;
	int ret;

	ret = __sysctr_timer_init(np);
	if (ret)
		return ret;

	priv = to_sysctr.private_data;
	priv->lo_off = CNTCV_LO;
	priv->hi_off = CNTCV_HI;

	clockevents_config_and_register(&to_sysctr.clkevt,
					timer_of_rate(&to_sysctr),
					0xff, 0x7fffffff);

	return 0;
}

static int __init sysctr_timer_imx95_init(struct device_node *np)
{
	struct sysctr_private *priv;
	int ret;

	ret = __sysctr_timer_init(np);
	if (ret)
		return ret;

	priv = to_sysctr.private_data;
	priv->lo_off = CNTCV_LO_IMX95;
	priv->hi_off = CNTCV_HI_IMX95;

	clockevents_config_and_register(&to_sysctr.clkevt,
					timer_of_rate(&to_sysctr),
					0xff, 0x7fffffff);

	return 0;
}

TIMER_OF_DECLARE(sysctr_timer, "nxp,sysctr-timer", sysctr_timer_init);
TIMER_OF_DECLARE(sysctr_timer_imx95, "nxp,imx95-sysctr-timer", sysctr_timer_imx95_init);
Commit	Line	Data
7117a44b BP	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright 2017-2019 NXP
	4
	5	#include <linux/interrupt.h>
	6	#include <linux/clockchips.h>
418062b5	7	#include <linux/slab.h>
7117a44b BP	8
	9	#include "timer-of.h"
	10
	11	#define CMP_OFFSET 0x10000
b67686e9	12	#define RD_OFFSET 0x20000
7117a44b BP	13
	14	#define CNTCV_LO 0x8
	15	#define CNTCV_HI 0xc
	16	#define CMPCV_LO (CMP_OFFSET + 0x20)
	17	#define CMPCV_HI (CMP_OFFSET + 0x24)
	18	#define CMPCR (CMP_OFFSET + 0x2c)
b67686e9 PF	19	#define CNTCV_LO_IMX95 (RD_OFFSET + 0x8)
b67686e9 PF	20	#define CNTCV_HI_IMX95 (RD_OFFSET + 0xc)
7117a44b BP	21
	22	#define SYS_CTR_EN 0x1
	23	#define SYS_CTR_IRQ_MASK 0x2
	24
4419e19d AH	25	#define SYS_CTR_CLK_DIV 0x3
4419e19d AH	26
418062b5 PF	27	struct sysctr_private {
418062b5 PF	28	u32 cmpcr;
b67686e9 PF	29	u32 lo_off;
b67686e9 PF	30	u32 hi_off;
418062b5	31	};
7117a44b	32
418062b5	33	static void sysctr_timer_enable(struct clock_event_device *evt, bool enable)
7117a44b	34	{
418062b5 PF	35	struct timer_of *to = to_timer_of(evt);
	36	struct sysctr_private *priv = to->private_data;
	37	void __iomem *base = timer_of_base(to);
	38
	39	writel(enable ? priv->cmpcr \| SYS_CTR_EN : priv->cmpcr, base + CMPCR);
7117a44b BP	40	}
7117a44b BP	41
418062b5	42	static void sysctr_irq_acknowledge(struct clock_event_device *evt)
7117a44b BP	43	{
	44	/*
	45	* clear the enable bit(EN =0) will clear
	46	* the status bit(ISTAT = 0), then the interrupt
	47	* signal will be negated(acknowledged).
	48	*/
418062b5	49	sysctr_timer_enable(evt, false);
7117a44b BP	50	}
7117a44b BP	51
418062b5	52	static inline u64 sysctr_read_counter(struct clock_event_device *evt)
7117a44b	53	{
418062b5	54	struct timer_of *to = to_timer_of(evt);
b67686e9	55	struct sysctr_private *priv = to->private_data;
418062b5	56	void __iomem *base = timer_of_base(to);
7117a44b BP	57	u32 cnt_hi, tmp_hi, cnt_lo;
	58
	59	do {
b67686e9 PF	60	cnt_hi = readl_relaxed(base + priv->hi_off);
	61	cnt_lo = readl_relaxed(base + priv->lo_off);
	62	tmp_hi = readl_relaxed(base + priv->hi_off);
7117a44b BP	63	} while (tmp_hi != cnt_hi);
	64
	65	return ((u64) cnt_hi << 32) \| cnt_lo;
	66	}
	67
	68	static int sysctr_set_next_event(unsigned long delta,
	69	struct clock_event_device *evt)
	70	{
418062b5 PF	71	struct timer_of *to = to_timer_of(evt);
418062b5 PF	72	void __iomem *base = timer_of_base(to);
7117a44b BP	73	u32 cmp_hi, cmp_lo;
	74	u64 next;
	75
418062b5	76	sysctr_timer_enable(evt, false);
7117a44b	77
418062b5	78	next = sysctr_read_counter(evt);
7117a44b BP	79
	80	next += delta;
	81
	82	cmp_hi = (next >> 32) & 0x00fffff;
	83	cmp_lo = next & 0xffffffff;
	84
418062b5 PF	85	writel_relaxed(cmp_hi, base + CMPCV_HI);
418062b5 PF	86	writel_relaxed(cmp_lo, base + CMPCV_LO);
7117a44b	87
418062b5	88	sysctr_timer_enable(evt, true);
7117a44b BP	89
	90	return 0;
	91	}
	92
	93	static int sysctr_set_state_oneshot(struct clock_event_device *evt)
	94	{
	95	return 0;
	96	}
	97
	98	static int sysctr_set_state_shutdown(struct clock_event_device *evt)
	99	{
418062b5	100	sysctr_timer_enable(evt, false);
7117a44b BP	101
	102	return 0;
	103	}
	104
	105	static irqreturn_t sysctr_timer_interrupt(int irq, void *dev_id)
	106	{
	107	struct clock_event_device *evt = dev_id;
	108
418062b5	109	sysctr_irq_acknowledge(evt);
7117a44b BP	110
	111	evt->event_handler(evt);
	112
	113	return IRQ_HANDLED;
	114	}
	115
	116	static struct timer_of to_sysctr = {
	117	.flags = TIMER_OF_IRQ \| TIMER_OF_CLOCK \| TIMER_OF_BASE,
	118	.clkevt = {
	119	.name = "i.MX system counter timer",
	120	.features = CLOCK_EVT_FEAT_ONESHOT \|
	121	CLOCK_EVT_FEAT_DYNIRQ,
	122	.set_state_oneshot = sysctr_set_state_oneshot,
	123	.set_next_event = sysctr_set_next_event,
	124	.set_state_shutdown = sysctr_set_state_shutdown,
	125	.rating = 200,
	126	},
	127	.of_irq = {
	128	.handler = sysctr_timer_interrupt,
84125554	129	.flags = IRQF_TIMER,
7117a44b BP	130	},
	131	.of_clk = {
	132	.name = "per",
	133	},
	134	};
	135
b67686e9	136	static int __init __sysctr_timer_init(struct device_node *np)
7117a44b	137	{
418062b5 PF	138	struct sysctr_private *priv;
	139	void __iomem *base;
	140	int ret;
	141
	142	priv = kzalloc(sizeof(struct sysctr_private), GFP_KERNEL);
	143	if (!priv)
	144	return -ENOMEM;
7117a44b BP	145
7117a44b BP	146	ret = timer_of_init(np, &to_sysctr);
418062b5 PF	147	if (ret) {
418062b5 PF	148	kfree(priv);
7117a44b	149	return ret;
418062b5	150	}
7117a44b	151
27b30995 PF	152	if (!of_property_read_bool(np, "nxp,no-divider")) {
	153	/* system counter clock is divided by 3 internally */
	154	to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
	155	}
4419e19d	156
418062b5 PF	157	to_sysctr.clkevt.cpumask = cpu_possible_mask;
418062b5 PF	158	to_sysctr.private_data = priv;
7117a44b	159
418062b5 PF	160	base = timer_of_base(&to_sysctr);
418062b5 PF	161	priv->cmpcr = readl(base + CMPCR) & ~SYS_CTR_EN;
7117a44b	162
b67686e9 PF	163	return 0;
	164	}
	165
	166	static int __init sysctr_timer_init(struct device_node *np)
	167	{
	168	struct sysctr_private *priv;
	169	int ret;
	170
	171	ret = __sysctr_timer_init(np);
	172	if (ret)
	173	return ret;
	174
	175	priv = to_sysctr.private_data;
	176	priv->lo_off = CNTCV_LO;
	177	priv->hi_off = CNTCV_HI;
	178
418062b5 PF	179	clockevents_config_and_register(&to_sysctr.clkevt,
	180	timer_of_rate(&to_sysctr),
	181	0xff, 0x7fffffff);
b67686e9	182
7117a44b BP	183	return 0;
7117a44b BP	184	}
b67686e9 PF	185
	186	static int __init sysctr_timer_imx95_init(struct device_node *np)
	187	{
	188	struct sysctr_private *priv;
	189	int ret;
	190
	191	ret = __sysctr_timer_init(np);
	192	if (ret)
	193	return ret;
	194
	195	priv = to_sysctr.private_data;
	196	priv->lo_off = CNTCV_LO_IMX95;
	197	priv->hi_off = CNTCV_HI_IMX95;
	198
	199	clockevents_config_and_register(&to_sysctr.clkevt,
	200	timer_of_rate(&to_sysctr),
	201	0xff, 0x7fffffff);
	202
	203	return 0;
	204	}
	205
7117a44b	206	TIMER_OF_DECLARE(sysctr_timer, "nxp,sysctr-timer", sysctr_timer_init);
b67686e9	207	TIMER_OF_DECLARE(sysctr_timer_imx95, "nxp,imx95-sysctr-timer", sysctr_timer_imx95_init);