[linux-block.git] / drivers / clocksource / timer-imx-gpt.c

// SPDX-License-Identifier: GPL-2.0+
//
//  Copyright (C) 2000-2001 Deep Blue Solutions
//  Copyright (C) 2002 Shane Nay (shane@minirl.com)
//  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
//  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <soc/imx/timer.h>

/*
 * There are 4 versions of the timer hardware on Freescale MXC hardware.
 *  - MX1/MXL
 *  - MX21, MX27.
 *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
 *  - MX6DL, MX6SX, MX6Q(rev1.1+)
 */

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5, MX6 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_CLK_PER		(2 << 6)
#define V2_TCTL_CLK_OSC_DIV8	(5 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_TCTL_24MEN		(1 << 10)
#define V2_TPRER_PRE24M		12
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define V2_TIMER_RATE_OSC_DIV8	3000000

struct imx_timer {
	enum imx_gpt_type type;
	void __iomem *base;
	int irq;
	struct clk *clk_per;
	struct clk *clk_ipg;
	const struct imx_gpt_data *gpt;
	struct clock_event_device ced;
};

struct imx_gpt_data {
	int reg_tstat;
	int reg_tcn;
	int reg_tcmp;
	void (*gpt_setup_tctl)(struct imx_timer *imxtm);
	void (*gpt_irq_enable)(struct imx_timer *imxtm);
	void (*gpt_irq_disable)(struct imx_timer *imxtm);
	void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
	int (*set_next_event)(unsigned long evt,
			      struct clock_event_device *ced);
};

static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
{
	return container_of(ced, struct imx_timer, ced);
}

static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_disable imx1_gpt_irq_disable

static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable

static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_enable imx1_gpt_irq_enable

static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
{
	writel_relaxed(1<<0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable

static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
}

static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				imxtm->base + MX1_2_TSTAT);
}

static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
}
#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge

static void __iomem *sched_clock_reg;

static u64 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
}

#if defined(CONFIG_ARM)
static struct delay_timer imx_delay_timer;

static unsigned long imx_read_current_timer(void)
{
	return readl_relaxed(sched_clock_reg);
}
#endif

static int __init mxc_clocksource_init(struct imx_timer *imxtm)
{
	unsigned int c = clk_get_rate(imxtm->clk_per);
	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;

#if defined(CONFIG_ARM)
	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	imx_delay_timer.freq = c;
	register_current_timer_delay(&imx_delay_timer);
#endif

	sched_clock_reg = reg;

	sched_clock_register(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);

	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + V2_TCMP);

	return evt < 0x7fffffff &&
		(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

static int mxc_shutdown(struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	u32 tcn;

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
	/* Set event time into far-far future */
	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

	/* Clear pending interrupt */
	imxtm->gpt->gpt_irq_acknowledge(imxtm);

#ifdef DEBUG
	printk(KERN_INFO "%s: changing mode\n", __func__);
#endif /* DEBUG */

	return 0;
}

static int mxc_set_oneshot(struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	if (!clockevent_state_oneshot(ced)) {
		u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
		/* Set event time into far-far future */
		writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

		/* Clear pending interrupt */
		imxtm->gpt->gpt_irq_acknowledge(imxtm);
	}

#ifdef DEBUG
	printk(KERN_INFO "%s: changing mode\n", __func__);
#endif /* DEBUG */

	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
	imxtm->gpt->gpt_irq_enable(imxtm);

	return 0;
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ced = dev_id;
	struct imx_timer *imxtm = to_imx_timer(ced);
	uint32_t tstat;

	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);

	imxtm->gpt->gpt_irq_acknowledge(imxtm);

	ced->event_handler(ced);

	return IRQ_HANDLED;
}

static int __init mxc_clockevent_init(struct imx_timer *imxtm)
{
	struct clock_event_device *ced = &imxtm->ced;

	ced->name = "mxc_timer1";
	ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
	ced->set_state_shutdown = mxc_shutdown;
	ced->set_state_oneshot = mxc_set_oneshot;
	ced->tick_resume = mxc_shutdown;
	ced->set_next_event = imxtm->gpt->set_next_event;
	ced->rating = 200;
	ced->cpumask = cpumask_of(0);
	ced->irq = imxtm->irq;
	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
					0xff, 0xfffffffe);

	return request_irq(imxtm->irq, mxc_timer_interrupt,
			   IRQF_TIMER | IRQF_IRQPOLL, "i.MX Timer Tick", ced);
}

static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl

static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
	else
		tctl_val |= V2_TCTL_CLK_PER;

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
		/* 24 / 8 = 3 MHz */
		writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
		tctl_val |= V2_TCTL_24MEN;
	} else {
		tctl_val |= V2_TCTL_CLK_PER;
	}

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static const struct imx_gpt_data imx1_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx1_gpt_irq_enable,
	.gpt_irq_disable = imx1_gpt_irq_disable,
	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx1_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx21_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx21_gpt_irq_enable,
	.gpt_irq_disable = imx21_gpt_irq_disable,
	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx21_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx31_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx31_gpt_irq_enable,
	.gpt_irq_disable = imx31_gpt_irq_disable,
	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx31_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static const struct imx_gpt_data imx6dl_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx6dl_gpt_irq_enable,
	.gpt_irq_disable = imx6dl_gpt_irq_disable,
	.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static int __init _mxc_timer_init(struct imx_timer *imxtm)
{
	int ret;

	switch (imxtm->type) {
	case GPT_TYPE_IMX1:
		imxtm->gpt = &imx1_gpt_data;
		break;
	case GPT_TYPE_IMX21:
		imxtm->gpt = &imx21_gpt_data;
		break;
	case GPT_TYPE_IMX31:
		imxtm->gpt = &imx31_gpt_data;
		break;
	case GPT_TYPE_IMX6DL:
		imxtm->gpt = &imx6dl_gpt_data;
		break;
	default:
		return -EINVAL;
	}

	if (IS_ERR(imxtm->clk_per)) {
		pr_err("i.MX timer: unable to get clk\n");
		return PTR_ERR(imxtm->clk_per);
	}

	if (!IS_ERR(imxtm->clk_ipg))
		clk_prepare_enable(imxtm->clk_ipg);

	clk_prepare_enable(imxtm->clk_per);

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	writel_relaxed(0, imxtm->base + MXC_TCTL);
	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */

	imxtm->gpt->gpt_setup_tctl(imxtm);

	/* init and register the timer to the framework */
	ret = mxc_clocksource_init(imxtm);
	if (ret)
		return ret;

	return mxc_clockevent_init(imxtm);
}

void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
{
	struct imx_timer *imxtm;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	BUG_ON(!imxtm);

	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");

	imxtm->base = ioremap(pbase, SZ_4K);
	BUG_ON(!imxtm->base);

	imxtm->type = type;
	imxtm->irq = irq;

	_mxc_timer_init(imxtm);
}

static int __init mxc_timer_init_dt(struct device_node *np,  enum imx_gpt_type type)
{
	struct imx_timer *imxtm;
	static int initialized;
	int ret;

	/* Support one instance only */
	if (initialized)
		return 0;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	if (!imxtm)
		return -ENOMEM;

	imxtm->base = of_iomap(np, 0);
	if (!imxtm->base)
		return -ENXIO;

	imxtm->irq = irq_of_parse_and_map(np, 0);
	if (imxtm->irq <= 0)
		return -EINVAL;

	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");

	/* Try osc_per first, and fall back to per otherwise */
	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	if (IS_ERR(imxtm->clk_per))
		imxtm->clk_per = of_clk_get_by_name(np, "per");

	imxtm->type = type;

	ret = _mxc_timer_init(imxtm);
	if (ret)
		return ret;

	initialized = 1;

	return 0;
}

static int __init imx1_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX1);
}

static int __init imx21_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX21);
}

static int __init imx31_timer_init_dt(struct device_node *np)
{
	enum imx_gpt_type type = GPT_TYPE_IMX31;

	/*
	 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	 * GPT device, while they actually have different programming model.
	 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
	 * working with the new kernel.
	 */
	if (of_machine_is_compatible("fsl,imx6dl"))
		type = GPT_TYPE_IMX6DL;

	return mxc_timer_init_dt(np, type);
}

static int __init imx6dl_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
}

TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
Commit	Line	Data
c53bb605 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2000-2001 Deep Blue Solutions
	4	// Copyright (C) 2002 Shane Nay (shane@minirl.com)
	5	// Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	6	// Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
d0f349fb JB	7
	8	#include <linux/interrupt.h>
	9	#include <linux/irq.h>
	10	#include <linux/clockchips.h>
	11	#include <linux/clk.h>
1119c84a	12	#include <linux/delay.h>
821dc4df	13	#include <linux/err.h>
38ff87f7	14	#include <linux/sched_clock.h>
6dd74782	15	#include <linux/slab.h>
876292d6 GC	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_irq.h>
0931aff7	19	#include <soc/imx/timer.h>
d0f349fb	20
0f3332c4	21	/*
65d0a16d SW	22	* There are 4 versions of the timer hardware on Freescale MXC hardware.
	23	* - MX1/MXL
	24	* - MX21, MX27.
	25	* - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
	26	* - MX6DL, MX6SX, MX6Q(rev1.1+)
0f3332c4 SH	27	*/
0f3332c4 SH	28
ec996ba9 SH	29	/* defines common for all i.MX */
ec996ba9 SH	30	#define MXC_TCTL 0x00
0f3332c4	31	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	32	#define MXC_TPRER 0x04
	33
	34	/* MX1, MX21, MX27 */
	35	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	36	#define MX1_2_TCTL_IRQEN (1 << 4)
	37	#define MX1_2_TCTL_FRR (1 << 8)
	38	#define MX1_2_TCMP 0x08
	39	#define MX1_2_TCN 0x10
	40	#define MX1_2_TSTAT 0x14
	41
	42	/* MX21, MX27 */
	43	#define MX2_TSTAT_CAPT (1 << 1)
	44	#define MX2_TSTAT_COMP (1 << 0)
	45
bad3db10	46	/* MX31, MX35, MX25, MX5, MX6 */
38a66f51 AK	47	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
38a66f51 AK	48	#define V2_TCTL_CLK_IPG (1 << 6)
1f152b48	49	#define V2_TCTL_CLK_PER (2 << 6)
bad3db10	50	#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
38a66f51	51	#define V2_TCTL_FRR (1 << 9)
bad3db10 AH	52	#define V2_TCTL_24MEN (1 << 10)
bad3db10 AH	53	#define V2_TPRER_PRE24M 12
38a66f51 AK	54	#define V2_IR 0x0c
	55	#define V2_TSTAT 0x08
	56	#define V2_TSTAT_OF1 (1 << 0)
	57	#define V2_TCN 0x24
	58	#define V2_TCMP 0x10
d0f349fb	59
bad3db10 AH	60	#define V2_TIMER_RATE_OSC_DIV8 3000000
bad3db10 AH	61
6dd74782	62	struct imx_timer {
0931aff7	63	enum imx_gpt_type type;
6dd74782 SG	64	void __iomem *base;
	65	int irq;
	66	struct clk *clk_per;
	67	struct clk *clk_ipg;
9c8694bd	68	const struct imx_gpt_data *gpt;
e510d201	69	struct clock_event_device ced;
9c8694bd SG	70	};
	71
	72	struct imx_gpt_data {
24f74ad1 SG	73	int reg_tstat;
	74	int reg_tcn;
	75	int reg_tcmp;
9c8694bd	76	void (gpt_setup_tctl)(struct imx_timer imxtm);
db2ae4b4 SG	77	void (gpt_irq_enable)(struct imx_timer imxtm);
	78	void (gpt_irq_disable)(struct imx_timer imxtm);
	79	void (gpt_irq_acknowledge)(struct imx_timer imxtm);
5ab0475b SG	80	int (*set_next_event)(unsigned long evt,
5ab0475b SG	81	struct clock_event_device *ced);
6dd74782 SG	82	};
6dd74782 SG	83
e510d201 SG	84	static inline struct imx_timer to_imx_timer(struct clock_event_device ced)
	85	{
	86	return container_of(ced, struct imx_timer, ced);
	87	}
	88
db2ae4b4	89	static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
d0f349fb	90	{
ec996ba9 SH	91	unsigned int tmp;
ec996ba9 SH	92
db2ae4b4 SG	93	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
db2ae4b4 SG	94	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
ec996ba9	95	}
db2ae4b4	96	#define imx21_gpt_irq_disable imx1_gpt_irq_disable
ec996ba9	97
db2ae4b4	98	static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
ec996ba9	99	{
db2ae4b4 SG	100	writel_relaxed(0, imxtm->base + V2_IR);
	101	}
	102	#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
	103
	104	static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
	105	{
	106	unsigned int tmp;
	107
	108	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	109	writel_relaxed(tmp \| MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
	110	}
	111	#define imx21_gpt_irq_enable imx1_gpt_irq_enable
	112
	113	static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
	114	{
	115	writel_relaxed(1<<0, imxtm->base + V2_IR);
	116	}
	117	#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
	118
	119	static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
	120	{
	121	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	122	}
ec996ba9 SH	123
db2ae4b4	124	static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
ec996ba9	125	{
db2ae4b4	126	writel_relaxed(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
89955520	127	imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	128	}
ec996ba9 SH	129
db2ae4b4 SG	130	static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
	131	{
	132	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
	133	}
	134	#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
	135
234b6ced	136	static void __iomem *sched_clock_reg;
d0f349fb	137
b93767e3	138	static u64 notrace mxc_read_sched_clock(void)
c124befc	139	{
c7770bba	140	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
c124befc JW	141	}
c124befc JW	142
df181e38	143	#if defined(CONFIG_ARM)
1119c84a SAS	144	static struct delay_timer imx_delay_timer;
	145
	146	static unsigned long imx_read_current_timer(void)
	147	{
c7770bba	148	return readl_relaxed(sched_clock_reg);
1119c84a	149	}
df181e38	150	#endif
1119c84a	151
6dd74782	152	static int __init mxc_clocksource_init(struct imx_timer *imxtm)
d0f349fb	153	{
6dd74782	154	unsigned int c = clk_get_rate(imxtm->clk_per);
24f74ad1	155	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
d0f349fb	156
df181e38	157	#if defined(CONFIG_ARM)
1119c84a SAS	158	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	159	imx_delay_timer.freq = c;
	160	register_current_timer_delay(&imx_delay_timer);
df181e38	161	#endif
1119c84a	162
234b6ced	163	sched_clock_reg = reg;
ec996ba9	164
b93767e3	165	sched_clock_register(mxc_read_sched_clock, 32, c);
234b6ced RK	166	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	167	clocksource_mmio_readl_up);
d0f349fb JB	168	}
	169
	170	/* clock event */
	171
ec996ba9	172	static int mx1_2_set_next_event(unsigned long evt,
89955520	173	struct clock_event_device *ced)
d0f349fb	174	{
89955520	175	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	176	unsigned long tcmp;
d0f349fb JB	177
89955520	178	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
d0f349fb	179
89955520	180	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
ec996ba9	181
89955520	182	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
ec996ba9 SH	183	-ETIME : 0;
	184	}
	185
38a66f51	186	static int v2_set_next_event(unsigned long evt,
89955520	187	struct clock_event_device *ced)
ec996ba9	188	{
89955520	189	struct imx_timer *imxtm = to_imx_timer(ced);
ec996ba9 SH	190	unsigned long tcmp;
ec996ba9 SH	191
89955520	192	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
ec996ba9	193
89955520	194	writel_relaxed(tcmp, imxtm->base + V2_TCMP);
ec996ba9	195
eea8e326	196	return evt < 0x7fffffff &&
89955520	197	(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
d0f349fb JB	198	-ETIME : 0;
	199	}
	200
26b91f04 VK	201	static int mxc_shutdown(struct clock_event_device *ced)
	202	{
	203	struct imx_timer *imxtm = to_imx_timer(ced);
26b91f04 VK	204	u32 tcn;
26b91f04 VK	205
26b91f04 VK	206	/* Disable interrupt in GPT module */
	207	imxtm->gpt->gpt_irq_disable(imxtm);
	208
	209	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
	210	/* Set event time into far-far future */
	211	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
	212
	213	/* Clear pending interrupt */
	214	imxtm->gpt->gpt_irq_acknowledge(imxtm);
	215
d0f349fb	216	#ifdef DEBUG
26b91f04	217	printk(KERN_INFO "%s: changing mode\n", __func__);
d0f349fb JB	218	#endif /* DEBUG */
d0f349fb JB	219
26b91f04 VK	220	return 0;
	221	}
	222
	223	static int mxc_set_oneshot(struct clock_event_device *ced)
d0f349fb	224	{
e510d201	225	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	226
d0f349fb JB	227	/* Disable interrupt in GPT module */
db2ae4b4	228	imxtm->gpt->gpt_irq_disable(imxtm);
d0f349fb	229
26b91f04	230	if (!clockevent_state_oneshot(ced)) {
24f74ad1	231	u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
d0f349fb	232	/* Set event time into far-far future */
24f74ad1	233	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
ec996ba9	234
d0f349fb	235	/* Clear pending interrupt */
db2ae4b4	236	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb JB	237	}
	238
	239	#ifdef DEBUG
26b91f04	240	printk(KERN_INFO "%s: changing mode\n", __func__);
d0f349fb JB	241	#endif /* DEBUG */
d0f349fb JB	242
d0f349fb JB	243	/*
	244	* Do not put overhead of interrupt enable/disable into
	245	* mxc_set_next_event(), the core has about 4 minutes
	246	* to call mxc_set_next_event() or shutdown clock after
	247	* mode switching
	248	*/
26b91f04	249	imxtm->gpt->gpt_irq_enable(imxtm);
26b91f04 VK	250
26b91f04 VK	251	return 0;
d0f349fb JB	252	}
	253
	254	/*
	255	* IRQ handler for the timer
	256	*/
	257	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	258	{
e510d201	259	struct clock_event_device *ced = dev_id;
24f74ad1	260	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	261	uint32_t tstat;
d0f349fb JB	262
24f74ad1	263	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
d0f349fb	264
db2ae4b4	265	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb	266
e510d201	267	ced->event_handler(ced);
d0f349fb JB	268
	269	return IRQ_HANDLED;
	270	}
	271
6dd74782	272	static int __init mxc_clockevent_init(struct imx_timer *imxtm)
d0f349fb	273	{
e510d201	274	struct clock_event_device *ced = &imxtm->ced;
e510d201	275
e510d201	276	ced->name = "mxc_timer1";
f1c08c9b	277	ced->features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_DYNIRQ;
26b91f04 VK	278	ced->set_state_shutdown = mxc_shutdown;
	279	ced->set_state_oneshot = mxc_set_oneshot;
	280	ced->tick_resume = mxc_shutdown;
e510d201 SG	281	ced->set_next_event = imxtm->gpt->set_next_event;
	282	ced->rating = 200;
	283	ced->cpumask = cpumask_of(0);
f1c08c9b	284	ced->irq = imxtm->irq;
e510d201	285	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
838a2ae8	286	0xff, 0xfffffffe);
d0f349fb	287
cc2550b4	288	return request_irq(imxtm->irq, mxc_timer_interrupt,
cc2550b4	289	IRQF_TIMER \| IRQF_IRQPOLL, "i.MX Timer Tick", ced);
d0f349fb JB	290	}
d0f349fb JB	291
9c8694bd SG	292	static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
	293	{
	294	u32 tctl_val;
	295
	296	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	297	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	298	}
	299	#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
	300
	301	static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
	302	{
	303	u32 tctl_val;
	304
	305	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	306	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
	307	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	308	else
	309	tctl_val \|= V2_TCTL_CLK_PER;
	310
	311	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	312	}
	313
	314	static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
d0f349fb	315	{
9c8694bd SG	316	u32 tctl_val;
	317
	318	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	319	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
	320	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	321	/* 24 / 8 = 3 MHz */
	322	writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
	323	tctl_val \|= V2_TCTL_24MEN;
	324	} else {
	325	tctl_val \|= V2_TCTL_CLK_PER;
	326	}
	327
	328	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	329	}
821dc4df	330
9c8694bd	331	static const struct imx_gpt_data imx1_gpt_data = {
24f74ad1 SG	332	.reg_tstat = MX1_2_TSTAT,
	333	.reg_tcn = MX1_2_TCN,
	334	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	335	.gpt_irq_enable = imx1_gpt_irq_enable,
	336	.gpt_irq_disable = imx1_gpt_irq_disable,
	337	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
9c8694bd	338	.gpt_setup_tctl = imx1_gpt_setup_tctl,
5ab0475b	339	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	340	};
	341
	342	static const struct imx_gpt_data imx21_gpt_data = {
24f74ad1 SG	343	.reg_tstat = MX1_2_TSTAT,
	344	.reg_tcn = MX1_2_TCN,
	345	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	346	.gpt_irq_enable = imx21_gpt_irq_enable,
	347	.gpt_irq_disable = imx21_gpt_irq_disable,
	348	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
9c8694bd	349	.gpt_setup_tctl = imx21_gpt_setup_tctl,
5ab0475b	350	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	351	};
	352
	353	static const struct imx_gpt_data imx31_gpt_data = {
24f74ad1 SG	354	.reg_tstat = V2_TSTAT,
	355	.reg_tcn = V2_TCN,
	356	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	357	.gpt_irq_enable = imx31_gpt_irq_enable,
	358	.gpt_irq_disable = imx31_gpt_irq_disable,
	359	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
9c8694bd	360	.gpt_setup_tctl = imx31_gpt_setup_tctl,
5ab0475b	361	.set_next_event = v2_set_next_event,
9c8694bd SG	362	};
	363
	364	static const struct imx_gpt_data imx6dl_gpt_data = {
24f74ad1 SG	365	.reg_tstat = V2_TSTAT,
	366	.reg_tcn = V2_TCN,
	367	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	368	.gpt_irq_enable = imx6dl_gpt_irq_enable,
	369	.gpt_irq_disable = imx6dl_gpt_irq_disable,
	370	.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
9c8694bd	371	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
5ab0475b	372	.set_next_event = v2_set_next_event,
9c8694bd SG	373	};
9c8694bd SG	374
c11cd416	375	static int __init _mxc_timer_init(struct imx_timer *imxtm)
9c8694bd	376	{
c11cd416 DL	377	int ret;
c11cd416 DL	378
9c8694bd SG	379	switch (imxtm->type) {
	380	case GPT_TYPE_IMX1:
	381	imxtm->gpt = &imx1_gpt_data;
	382	break;
	383	case GPT_TYPE_IMX21:
	384	imxtm->gpt = &imx21_gpt_data;
	385	break;
	386	case GPT_TYPE_IMX31:
	387	imxtm->gpt = &imx31_gpt_data;
	388	break;
	389	case GPT_TYPE_IMX6DL:
	390	imxtm->gpt = &imx6dl_gpt_data;
	391	break;
	392	default:
c11cd416	393	return -EINVAL;
9c8694bd SG	394	}
9c8694bd SG	395
6dd74782	396	if (IS_ERR(imxtm->clk_per)) {
2cfb4518	397	pr_err("i.MX timer: unable to get clk\n");
c11cd416	398	return PTR_ERR(imxtm->clk_per);
821dc4df	399	}
ec996ba9	400
6dd74782 SG	401	if (!IS_ERR(imxtm->clk_ipg))
6dd74782 SG	402	clk_prepare_enable(imxtm->clk_ipg);
2cfb4518	403
6dd74782	404	clk_prepare_enable(imxtm->clk_per);
d0f349fb JB	405
	406	/*
	407	* Initialise to a known state (all timers off, and timing reset)
	408	*/
d0f349fb	409
6dd74782 SG	410	writel_relaxed(0, imxtm->base + MXC_TCTL);
6dd74782 SG	411	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
ec996ba9	412
9c8694bd	413	imxtm->gpt->gpt_setup_tctl(imxtm);
d0f349fb JB	414
d0f349fb JB	415	/* init and register the timer to the framework */
c11cd416 DL	416	ret = mxc_clocksource_init(imxtm);
	417	if (ret)
	418	return ret;
	419
	420	return mxc_clockevent_init(imxtm);
d0f349fb	421	}
876292d6	422
0931aff7	423	void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
f4696752	424	{
6dd74782 SG	425	struct imx_timer *imxtm;
	426
	427	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	428	BUG_ON(!imxtm);
f4696752	429
6dd74782 SG	430	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
6dd74782 SG	431	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
d7f98915	432
6dd74782 SG	433	imxtm->base = ioremap(pbase, SZ_4K);
	434	BUG_ON(!imxtm->base);
	435
0931aff7	436	imxtm->type = type;
be3b0f9b	437	imxtm->irq = irq;
0931aff7	438
6dd74782	439	_mxc_timer_init(imxtm);
f4696752 AS	440	}
f4696752 AS	441
c11cd416	442	static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
876292d6	443	{
6dd74782 SG	444	struct imx_timer *imxtm;
6dd74782 SG	445	static int initialized;
c11cd416	446	int ret;
876292d6	447
6dd74782 SG	448	/* Support one instance only */
6dd74782 SG	449	if (initialized)
c11cd416	450	return 0;
fd4959d8	451
6dd74782	452	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
c11cd416 DL	453	if (!imxtm)
c11cd416 DL	454	return -ENOMEM;
876292d6	455
6dd74782	456	imxtm->base = of_iomap(np, 0);
c11cd416 DL	457	if (!imxtm->base)
	458	return -ENXIO;
	459
6dd74782	460	imxtm->irq = irq_of_parse_and_map(np, 0);
c11cd416 DL	461	if (imxtm->irq <= 0)
c11cd416 DL	462	return -EINVAL;
6dd74782 SG	463
6dd74782 SG	464	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
f4696752	465
bad3db10	466	/* Try osc_per first, and fall back to per otherwise */
6dd74782 SG	467	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	468	if (IS_ERR(imxtm->clk_per))
	469	imxtm->clk_per = of_clk_get_by_name(np, "per");
	470
bef11c88 SG	471	imxtm->type = type;
bef11c88 SG	472
c11cd416 DL	473	ret = _mxc_timer_init(imxtm);
	474	if (ret)
	475	return ret;
bad3db10	476
6dd74782	477	initialized = 1;
c11cd416 DL	478
c11cd416 DL	479	return 0;
876292d6	480	}
bef11c88	481
c11cd416	482	static int __init imx1_timer_init_dt(struct device_node *np)
bef11c88	483	{
c11cd416	484	return mxc_timer_init_dt(np, GPT_TYPE_IMX1);
bef11c88 SG	485	}
bef11c88 SG	486
c11cd416	487	static int __init imx21_timer_init_dt(struct device_node *np)
bef11c88	488	{
c11cd416	489	return mxc_timer_init_dt(np, GPT_TYPE_IMX21);
bef11c88 SG	490	}
bef11c88 SG	491
c11cd416	492	static int __init imx31_timer_init_dt(struct device_node *np)
bef11c88 SG	493	{
	494	enum imx_gpt_type type = GPT_TYPE_IMX31;
	495
	496	/*
	497	* We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	498	* GPT device, while they actually have different programming model.
	499	* This is a workaround to keep the existing i.MX6DL/S DTBs continue
	500	* working with the new kernel.
	501	*/
	502	if (of_machine_is_compatible("fsl,imx6dl"))
	503	type = GPT_TYPE_IMX6DL;
	504
c11cd416	505	return mxc_timer_init_dt(np, type);
bef11c88 SG	506	}
bef11c88 SG	507
c11cd416	508	static int __init imx6dl_timer_init_dt(struct device_node *np)
bef11c88	509	{
c11cd416	510	return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
bef11c88 SG	511	}
bef11c88 SG	512
17273395 DL	513	TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
	514	TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
	515	TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
	516	TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
	517	TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
	518	TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
	519	TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
	520	TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
	521	TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
	522	TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
	523	TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
	524	TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);