[linux-2.6-block.git] / drivers / clocksource / timer-imx-gpt.c

// SPDX-License-Identifier: GPL-2.0+
//
//  Copyright (C) 2000-2001 Deep Blue Solutions
//  Copyright (C) 2002 Shane Nay (shane@minirl.com)
//  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
//  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <soc/imx/timer.h>

/*
 * There are 4 versions of the timer hardware on Freescale MXC hardware.
 *  - MX1/MXL
 *  - MX21, MX27.
 *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
 *  - MX6DL, MX6SX, MX6Q(rev1.1+)
 */

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5, MX6 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_CLK_PER		(2 << 6)
#define V2_TCTL_CLK_OSC_DIV8	(5 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_TCTL_24MEN		(1 << 10)
#define V2_TPRER_PRE24M		12
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define V2_TIMER_RATE_OSC_DIV8	3000000

struct imx_timer {
	enum imx_gpt_type type;
	void __iomem *base;
	int irq;
	struct clk *clk_per;
	struct clk *clk_ipg;
	const struct imx_gpt_data *gpt;
	struct clock_event_device ced;
	struct irqaction act;
};

struct imx_gpt_data {
	int reg_tstat;
	int reg_tcn;
	int reg_tcmp;
	void (*gpt_setup_tctl)(struct imx_timer *imxtm);
	void (*gpt_irq_enable)(struct imx_timer *imxtm);
	void (*gpt_irq_disable)(struct imx_timer *imxtm);
	void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
	int (*set_next_event)(unsigned long evt,
			      struct clock_event_device *ced);
};

static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
{
	return container_of(ced, struct imx_timer, ced);
}

static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_disable imx1_gpt_irq_disable

static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable

static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_enable imx1_gpt_irq_enable

static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
{
	writel_relaxed(1<<0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable

static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
}

static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				imxtm->base + MX1_2_TSTAT);
}

static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
}
#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge

static void __iomem *sched_clock_reg;

static u64 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
}

#if defined(CONFIG_ARM)
static struct delay_timer imx_delay_timer;

static unsigned long imx_read_current_timer(void)
{
	return readl_relaxed(sched_clock_reg);
}
#endif

static int __init mxc_clocksource_init(struct imx_timer *imxtm)
{
	unsigned int c = clk_get_rate(imxtm->clk_per);
	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;

#if defined(CONFIG_ARM)
	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	imx_delay_timer.freq = c;
	register_current_timer_delay(&imx_delay_timer);
#endif

	sched_clock_reg = reg;

	sched_clock_register(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);

	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + V2_TCMP);

	return evt < 0x7fffffff &&
		(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

static int mxc_shutdown(struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	u32 tcn;

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
	/* Set event time into far-far future */
	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

	/* Clear pending interrupt */
	imxtm->gpt->gpt_irq_acknowledge(imxtm);

#ifdef DEBUG
	printk(KERN_INFO "%s: changing mode\n", __func__);
#endif /* DEBUG */

	return 0;
}

static int mxc_set_oneshot(struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	if (!clockevent_state_oneshot(ced)) {
		u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
		/* Set event time into far-far future */
		writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

		/* Clear pending interrupt */
		imxtm->gpt->gpt_irq_acknowledge(imxtm);
	}

#ifdef DEBUG
	printk(KERN_INFO "%s: changing mode\n", __func__);
#endif /* DEBUG */

	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
	imxtm->gpt->gpt_irq_enable(imxtm);

	return 0;
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ced = dev_id;
	struct imx_timer *imxtm = to_imx_timer(ced);
	uint32_t tstat;

	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);

	imxtm->gpt->gpt_irq_acknowledge(imxtm);

	ced->event_handler(ced);

	return IRQ_HANDLED;
}

static int __init mxc_clockevent_init(struct imx_timer *imxtm)
{
	struct clock_event_device *ced = &imxtm->ced;
	struct irqaction *act = &imxtm->act;

	ced->name = "mxc_timer1";
	ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
	ced->set_state_shutdown = mxc_shutdown;
	ced->set_state_oneshot = mxc_set_oneshot;
	ced->tick_resume = mxc_shutdown;
	ced->set_next_event = imxtm->gpt->set_next_event;
	ced->rating = 200;
	ced->cpumask = cpumask_of(0);
	ced->irq = imxtm->irq;
	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
					0xff, 0xfffffffe);

	act->name = "i.MX Timer Tick";
	act->flags = IRQF_TIMER | IRQF_IRQPOLL;
	act->handler = mxc_timer_interrupt;
	act->dev_id = ced;

	return setup_irq(imxtm->irq, act);
}

static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl

static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
	else
		tctl_val |= V2_TCTL_CLK_PER;

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
		/* 24 / 8 = 3 MHz */
		writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
		tctl_val |= V2_TCTL_24MEN;
	} else {
		tctl_val |= V2_TCTL_CLK_PER;
	}

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static const struct imx_gpt_data imx1_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx1_gpt_irq_enable,
	.gpt_irq_disable = imx1_gpt_irq_disable,
	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx1_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx21_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx21_gpt_irq_enable,
	.gpt_irq_disable = imx21_gpt_irq_disable,
	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx21_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx31_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx31_gpt_irq_enable,
	.gpt_irq_disable = imx31_gpt_irq_disable,
	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx31_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static const struct imx_gpt_data imx6dl_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx6dl_gpt_irq_enable,
	.gpt_irq_disable = imx6dl_gpt_irq_disable,
	.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static int __init _mxc_timer_init(struct imx_timer *imxtm)
{
	int ret;

	switch (imxtm->type) {
	case GPT_TYPE_IMX1:
		imxtm->gpt = &imx1_gpt_data;
		break;
	case GPT_TYPE_IMX21:
		imxtm->gpt = &imx21_gpt_data;
		break;
	case GPT_TYPE_IMX31:
		imxtm->gpt = &imx31_gpt_data;
		break;
	case GPT_TYPE_IMX6DL:
		imxtm->gpt = &imx6dl_gpt_data;
		break;
	default:
		return -EINVAL;
	}

	if (IS_ERR(imxtm->clk_per)) {
		pr_err("i.MX timer: unable to get clk\n");
		return PTR_ERR(imxtm->clk_per);
	}

	if (!IS_ERR(imxtm->clk_ipg))
		clk_prepare_enable(imxtm->clk_ipg);

	clk_prepare_enable(imxtm->clk_per);

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	writel_relaxed(0, imxtm->base + MXC_TCTL);
	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */

	imxtm->gpt->gpt_setup_tctl(imxtm);

	/* init and register the timer to the framework */
	ret = mxc_clocksource_init(imxtm);
	if (ret)
		return ret;

	return mxc_clockevent_init(imxtm);
}

void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
{
	struct imx_timer *imxtm;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	BUG_ON(!imxtm);

	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");

	imxtm->base = ioremap(pbase, SZ_4K);
	BUG_ON(!imxtm->base);

	imxtm->type = type;
	imxtm->irq = irq;

	_mxc_timer_init(imxtm);
}

static int __init mxc_timer_init_dt(struct device_node *np,  enum imx_gpt_type type)
{
	struct imx_timer *imxtm;
	static int initialized;
	int ret;

	/* Support one instance only */
	if (initialized)
		return 0;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	if (!imxtm)
		return -ENOMEM;

	imxtm->base = of_iomap(np, 0);
	if (!imxtm->base)
		return -ENXIO;

	imxtm->irq = irq_of_parse_and_map(np, 0);
	if (imxtm->irq <= 0)
		return -EINVAL;

	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");

	/* Try osc_per first, and fall back to per otherwise */
	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	if (IS_ERR(imxtm->clk_per))
		imxtm->clk_per = of_clk_get_by_name(np, "per");

	imxtm->type = type;

	ret = _mxc_timer_init(imxtm);
	if (ret)
		return ret;

	initialized = 1;

	return 0;
}

static int __init imx1_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX1);
}

static int __init imx21_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX21);
}

static int __init imx31_timer_init_dt(struct device_node *np)
{
	enum imx_gpt_type type = GPT_TYPE_IMX31;

	/*
	 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	 * GPT device, while they actually have different programming model.
	 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
	 * working with the new kernel.
	 */
	if (of_machine_is_compatible("fsl,imx6dl"))
		type = GPT_TYPE_IMX6DL;

	return mxc_timer_init_dt(np, type);
}

static int __init imx6dl_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
}

TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
Commit	Line	Data
c53bb605 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2000-2001 Deep Blue Solutions
	4	// Copyright (C) 2002 Shane Nay (shane@minirl.com)
	5	// Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	6	// Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
d0f349fb JB	7
	8	#include <linux/interrupt.h>
	9	#include <linux/irq.h>
	10	#include <linux/clockchips.h>
	11	#include <linux/clk.h>
1119c84a	12	#include <linux/delay.h>
821dc4df	13	#include <linux/err.h>
38ff87f7	14	#include <linux/sched_clock.h>
6dd74782	15	#include <linux/slab.h>
876292d6 GC	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_irq.h>
0931aff7	19	#include <soc/imx/timer.h>
d0f349fb	20
0f3332c4	21	/*
65d0a16d SW	22	* There are 4 versions of the timer hardware on Freescale MXC hardware.
	23	* - MX1/MXL
	24	* - MX21, MX27.
	25	* - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
	26	* - MX6DL, MX6SX, MX6Q(rev1.1+)
0f3332c4 SH	27	*/
0f3332c4 SH	28
ec996ba9 SH	29	/* defines common for all i.MX */
ec996ba9 SH	30	#define MXC_TCTL 0x00
0f3332c4	31	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	32	#define MXC_TPRER 0x04
	33
	34	/* MX1, MX21, MX27 */
	35	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	36	#define MX1_2_TCTL_IRQEN (1 << 4)
	37	#define MX1_2_TCTL_FRR (1 << 8)
	38	#define MX1_2_TCMP 0x08
	39	#define MX1_2_TCN 0x10
	40	#define MX1_2_TSTAT 0x14
	41
	42	/* MX21, MX27 */
	43	#define MX2_TSTAT_CAPT (1 << 1)
	44	#define MX2_TSTAT_COMP (1 << 0)
	45
bad3db10	46	/* MX31, MX35, MX25, MX5, MX6 */
38a66f51 AK	47	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
38a66f51 AK	48	#define V2_TCTL_CLK_IPG (1 << 6)
1f152b48	49	#define V2_TCTL_CLK_PER (2 << 6)
bad3db10	50	#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
38a66f51	51	#define V2_TCTL_FRR (1 << 9)
bad3db10 AH	52	#define V2_TCTL_24MEN (1 << 10)
bad3db10 AH	53	#define V2_TPRER_PRE24M 12
38a66f51 AK	54	#define V2_IR 0x0c
	55	#define V2_TSTAT 0x08
	56	#define V2_TSTAT_OF1 (1 << 0)
	57	#define V2_TCN 0x24
	58	#define V2_TCMP 0x10
d0f349fb	59
bad3db10 AH	60	#define V2_TIMER_RATE_OSC_DIV8 3000000
bad3db10 AH	61
6dd74782	62	struct imx_timer {
0931aff7	63	enum imx_gpt_type type;
6dd74782 SG	64	void __iomem *base;
	65	int irq;
	66	struct clk *clk_per;
	67	struct clk *clk_ipg;
9c8694bd	68	const struct imx_gpt_data *gpt;
e510d201	69	struct clock_event_device ced;
e510d201	70	struct irqaction act;
9c8694bd SG	71	};
	72
	73	struct imx_gpt_data {
24f74ad1 SG	74	int reg_tstat;
	75	int reg_tcn;
	76	int reg_tcmp;
9c8694bd	77	void (gpt_setup_tctl)(struct imx_timer imxtm);
db2ae4b4 SG	78	void (gpt_irq_enable)(struct imx_timer imxtm);
	79	void (gpt_irq_disable)(struct imx_timer imxtm);
	80	void (gpt_irq_acknowledge)(struct imx_timer imxtm);
5ab0475b SG	81	int (*set_next_event)(unsigned long evt,
5ab0475b SG	82	struct clock_event_device *ced);
6dd74782 SG	83	};
6dd74782 SG	84
e510d201 SG	85	static inline struct imx_timer to_imx_timer(struct clock_event_device ced)
	86	{
	87	return container_of(ced, struct imx_timer, ced);
	88	}
	89
db2ae4b4	90	static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
d0f349fb	91	{
ec996ba9 SH	92	unsigned int tmp;
ec996ba9 SH	93
db2ae4b4 SG	94	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
db2ae4b4 SG	95	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
ec996ba9	96	}
db2ae4b4	97	#define imx21_gpt_irq_disable imx1_gpt_irq_disable
ec996ba9	98
db2ae4b4	99	static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
ec996ba9	100	{
db2ae4b4 SG	101	writel_relaxed(0, imxtm->base + V2_IR);
	102	}
	103	#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
	104
	105	static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
	106	{
	107	unsigned int tmp;
	108
	109	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	110	writel_relaxed(tmp \| MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
	111	}
	112	#define imx21_gpt_irq_enable imx1_gpt_irq_enable
	113
	114	static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
	115	{
	116	writel_relaxed(1<<0, imxtm->base + V2_IR);
	117	}
	118	#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
	119
	120	static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
	121	{
	122	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	123	}
ec996ba9 SH	124
db2ae4b4	125	static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
ec996ba9	126	{
db2ae4b4	127	writel_relaxed(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
89955520	128	imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	129	}
ec996ba9 SH	130
db2ae4b4 SG	131	static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
	132	{
	133	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
	134	}
	135	#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
	136
234b6ced	137	static void __iomem *sched_clock_reg;
d0f349fb	138
b93767e3	139	static u64 notrace mxc_read_sched_clock(void)
c124befc	140	{
c7770bba	141	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
c124befc JW	142	}
c124befc JW	143
df181e38	144	#if defined(CONFIG_ARM)
1119c84a SAS	145	static struct delay_timer imx_delay_timer;
	146
	147	static unsigned long imx_read_current_timer(void)
	148	{
c7770bba	149	return readl_relaxed(sched_clock_reg);
1119c84a	150	}
df181e38	151	#endif
1119c84a	152
6dd74782	153	static int __init mxc_clocksource_init(struct imx_timer *imxtm)
d0f349fb	154	{
6dd74782	155	unsigned int c = clk_get_rate(imxtm->clk_per);
24f74ad1	156	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
d0f349fb	157
df181e38	158	#if defined(CONFIG_ARM)
1119c84a SAS	159	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	160	imx_delay_timer.freq = c;
	161	register_current_timer_delay(&imx_delay_timer);
df181e38	162	#endif
1119c84a	163
234b6ced	164	sched_clock_reg = reg;
ec996ba9	165
b93767e3	166	sched_clock_register(mxc_read_sched_clock, 32, c);
234b6ced RK	167	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	168	clocksource_mmio_readl_up);
d0f349fb JB	169	}
	170
	171	/* clock event */
	172
ec996ba9	173	static int mx1_2_set_next_event(unsigned long evt,
89955520	174	struct clock_event_device *ced)
d0f349fb	175	{
89955520	176	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	177	unsigned long tcmp;
d0f349fb JB	178
89955520	179	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
d0f349fb	180
89955520	181	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
ec996ba9	182
89955520	183	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
ec996ba9 SH	184	-ETIME : 0;
	185	}
	186
38a66f51	187	static int v2_set_next_event(unsigned long evt,
89955520	188	struct clock_event_device *ced)
ec996ba9	189	{
89955520	190	struct imx_timer *imxtm = to_imx_timer(ced);
ec996ba9 SH	191	unsigned long tcmp;
ec996ba9 SH	192
89955520	193	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
ec996ba9	194
89955520	195	writel_relaxed(tcmp, imxtm->base + V2_TCMP);
ec996ba9	196
eea8e326	197	return evt < 0x7fffffff &&
89955520	198	(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
d0f349fb JB	199	-ETIME : 0;
	200	}
	201
26b91f04 VK	202	static int mxc_shutdown(struct clock_event_device *ced)
	203	{
	204	struct imx_timer *imxtm = to_imx_timer(ced);
26b91f04 VK	205	u32 tcn;
26b91f04 VK	206
26b91f04 VK	207	/* Disable interrupt in GPT module */
	208	imxtm->gpt->gpt_irq_disable(imxtm);
	209
	210	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
	211	/* Set event time into far-far future */
	212	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
	213
	214	/* Clear pending interrupt */
	215	imxtm->gpt->gpt_irq_acknowledge(imxtm);
	216
d0f349fb	217	#ifdef DEBUG
26b91f04	218	printk(KERN_INFO "%s: changing mode\n", __func__);
d0f349fb JB	219	#endif /* DEBUG */
d0f349fb JB	220
26b91f04 VK	221	return 0;
	222	}
	223
	224	static int mxc_set_oneshot(struct clock_event_device *ced)
d0f349fb	225	{
e510d201	226	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	227
d0f349fb JB	228	/* Disable interrupt in GPT module */
db2ae4b4	229	imxtm->gpt->gpt_irq_disable(imxtm);
d0f349fb	230
26b91f04	231	if (!clockevent_state_oneshot(ced)) {
24f74ad1	232	u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
d0f349fb	233	/* Set event time into far-far future */
24f74ad1	234	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
ec996ba9	235
d0f349fb	236	/* Clear pending interrupt */
db2ae4b4	237	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb JB	238	}
	239
	240	#ifdef DEBUG
26b91f04	241	printk(KERN_INFO "%s: changing mode\n", __func__);
d0f349fb JB	242	#endif /* DEBUG */
d0f349fb JB	243
d0f349fb JB	244	/*
	245	* Do not put overhead of interrupt enable/disable into
	246	* mxc_set_next_event(), the core has about 4 minutes
	247	* to call mxc_set_next_event() or shutdown clock after
	248	* mode switching
	249	*/
26b91f04	250	imxtm->gpt->gpt_irq_enable(imxtm);
26b91f04 VK	251
26b91f04 VK	252	return 0;
d0f349fb JB	253	}
	254
	255	/*
	256	* IRQ handler for the timer
	257	*/
	258	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	259	{
e510d201	260	struct clock_event_device *ced = dev_id;
24f74ad1	261	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	262	uint32_t tstat;
d0f349fb JB	263
24f74ad1	264	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
d0f349fb	265
db2ae4b4	266	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb	267
e510d201	268	ced->event_handler(ced);
d0f349fb JB	269
	270	return IRQ_HANDLED;
	271	}
	272
6dd74782	273	static int __init mxc_clockevent_init(struct imx_timer *imxtm)
d0f349fb	274	{
e510d201 SG	275	struct clock_event_device *ced = &imxtm->ced;
	276	struct irqaction *act = &imxtm->act;
	277
e510d201	278	ced->name = "mxc_timer1";
f1c08c9b	279	ced->features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_DYNIRQ;
26b91f04 VK	280	ced->set_state_shutdown = mxc_shutdown;
	281	ced->set_state_oneshot = mxc_set_oneshot;
	282	ced->tick_resume = mxc_shutdown;
e510d201 SG	283	ced->set_next_event = imxtm->gpt->set_next_event;
	284	ced->rating = 200;
	285	ced->cpumask = cpumask_of(0);
f1c08c9b	286	ced->irq = imxtm->irq;
e510d201	287	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
838a2ae8	288	0xff, 0xfffffffe);
d0f349fb	289
e510d201 SG	290	act->name = "i.MX Timer Tick";
	291	act->flags = IRQF_TIMER \| IRQF_IRQPOLL;
	292	act->handler = mxc_timer_interrupt;
	293	act->dev_id = ced;
	294
	295	return setup_irq(imxtm->irq, act);
d0f349fb JB	296	}
d0f349fb JB	297
9c8694bd SG	298	static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
	299	{
	300	u32 tctl_val;
	301
	302	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	303	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	304	}
	305	#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
	306
	307	static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
	308	{
	309	u32 tctl_val;
	310
	311	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	312	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
	313	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	314	else
	315	tctl_val \|= V2_TCTL_CLK_PER;
	316
	317	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	318	}
	319
	320	static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
d0f349fb	321	{
9c8694bd SG	322	u32 tctl_val;
	323
	324	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	325	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
	326	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	327	/* 24 / 8 = 3 MHz */
	328	writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
	329	tctl_val \|= V2_TCTL_24MEN;
	330	} else {
	331	tctl_val \|= V2_TCTL_CLK_PER;
	332	}
	333
	334	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	335	}
821dc4df	336
9c8694bd	337	static const struct imx_gpt_data imx1_gpt_data = {
24f74ad1 SG	338	.reg_tstat = MX1_2_TSTAT,
	339	.reg_tcn = MX1_2_TCN,
	340	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	341	.gpt_irq_enable = imx1_gpt_irq_enable,
	342	.gpt_irq_disable = imx1_gpt_irq_disable,
	343	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
9c8694bd	344	.gpt_setup_tctl = imx1_gpt_setup_tctl,
5ab0475b	345	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	346	};
	347
	348	static const struct imx_gpt_data imx21_gpt_data = {
24f74ad1 SG	349	.reg_tstat = MX1_2_TSTAT,
	350	.reg_tcn = MX1_2_TCN,
	351	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	352	.gpt_irq_enable = imx21_gpt_irq_enable,
	353	.gpt_irq_disable = imx21_gpt_irq_disable,
	354	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
9c8694bd	355	.gpt_setup_tctl = imx21_gpt_setup_tctl,
5ab0475b	356	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	357	};
	358
	359	static const struct imx_gpt_data imx31_gpt_data = {
24f74ad1 SG	360	.reg_tstat = V2_TSTAT,
	361	.reg_tcn = V2_TCN,
	362	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	363	.gpt_irq_enable = imx31_gpt_irq_enable,
	364	.gpt_irq_disable = imx31_gpt_irq_disable,
	365	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
9c8694bd	366	.gpt_setup_tctl = imx31_gpt_setup_tctl,
5ab0475b	367	.set_next_event = v2_set_next_event,
9c8694bd SG	368	};
	369
	370	static const struct imx_gpt_data imx6dl_gpt_data = {
24f74ad1 SG	371	.reg_tstat = V2_TSTAT,
	372	.reg_tcn = V2_TCN,
	373	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	374	.gpt_irq_enable = imx6dl_gpt_irq_enable,
	375	.gpt_irq_disable = imx6dl_gpt_irq_disable,
	376	.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
9c8694bd	377	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
5ab0475b	378	.set_next_event = v2_set_next_event,
9c8694bd SG	379	};
9c8694bd SG	380
c11cd416	381	static int __init _mxc_timer_init(struct imx_timer *imxtm)
9c8694bd	382	{
c11cd416 DL	383	int ret;
c11cd416 DL	384
9c8694bd SG	385	switch (imxtm->type) {
	386	case GPT_TYPE_IMX1:
	387	imxtm->gpt = &imx1_gpt_data;
	388	break;
	389	case GPT_TYPE_IMX21:
	390	imxtm->gpt = &imx21_gpt_data;
	391	break;
	392	case GPT_TYPE_IMX31:
	393	imxtm->gpt = &imx31_gpt_data;
	394	break;
	395	case GPT_TYPE_IMX6DL:
	396	imxtm->gpt = &imx6dl_gpt_data;
	397	break;
	398	default:
c11cd416	399	return -EINVAL;
9c8694bd SG	400	}
9c8694bd SG	401
6dd74782	402	if (IS_ERR(imxtm->clk_per)) {
2cfb4518	403	pr_err("i.MX timer: unable to get clk\n");
c11cd416	404	return PTR_ERR(imxtm->clk_per);
821dc4df	405	}
ec996ba9	406
6dd74782 SG	407	if (!IS_ERR(imxtm->clk_ipg))
6dd74782 SG	408	clk_prepare_enable(imxtm->clk_ipg);
2cfb4518	409
6dd74782	410	clk_prepare_enable(imxtm->clk_per);
d0f349fb JB	411
	412	/*
	413	* Initialise to a known state (all timers off, and timing reset)
	414	*/
d0f349fb	415
6dd74782 SG	416	writel_relaxed(0, imxtm->base + MXC_TCTL);
6dd74782 SG	417	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
ec996ba9	418
9c8694bd	419	imxtm->gpt->gpt_setup_tctl(imxtm);
d0f349fb JB	420
d0f349fb JB	421	/* init and register the timer to the framework */
c11cd416 DL	422	ret = mxc_clocksource_init(imxtm);
	423	if (ret)
	424	return ret;
	425
	426	return mxc_clockevent_init(imxtm);
d0f349fb	427	}
876292d6	428
0931aff7	429	void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
f4696752	430	{
6dd74782 SG	431	struct imx_timer *imxtm;
	432
	433	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	434	BUG_ON(!imxtm);
f4696752	435
6dd74782 SG	436	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
6dd74782 SG	437	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
d7f98915	438
6dd74782 SG	439	imxtm->base = ioremap(pbase, SZ_4K);
	440	BUG_ON(!imxtm->base);
	441
0931aff7	442	imxtm->type = type;
be3b0f9b	443	imxtm->irq = irq;
0931aff7	444
6dd74782	445	_mxc_timer_init(imxtm);
f4696752 AS	446	}
f4696752 AS	447
c11cd416	448	static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
876292d6	449	{
6dd74782 SG	450	struct imx_timer *imxtm;
6dd74782 SG	451	static int initialized;
c11cd416	452	int ret;
876292d6	453
6dd74782 SG	454	/* Support one instance only */
6dd74782 SG	455	if (initialized)
c11cd416	456	return 0;
fd4959d8	457
6dd74782	458	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
c11cd416 DL	459	if (!imxtm)
c11cd416 DL	460	return -ENOMEM;
876292d6	461
6dd74782	462	imxtm->base = of_iomap(np, 0);
c11cd416 DL	463	if (!imxtm->base)
	464	return -ENXIO;
	465
6dd74782	466	imxtm->irq = irq_of_parse_and_map(np, 0);
c11cd416 DL	467	if (imxtm->irq <= 0)
c11cd416 DL	468	return -EINVAL;
6dd74782 SG	469
6dd74782 SG	470	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
f4696752	471
bad3db10	472	/* Try osc_per first, and fall back to per otherwise */
6dd74782 SG	473	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	474	if (IS_ERR(imxtm->clk_per))
	475	imxtm->clk_per = of_clk_get_by_name(np, "per");
	476
bef11c88 SG	477	imxtm->type = type;
bef11c88 SG	478
c11cd416 DL	479	ret = _mxc_timer_init(imxtm);
	480	if (ret)
	481	return ret;
bad3db10	482
6dd74782	483	initialized = 1;
c11cd416 DL	484
c11cd416 DL	485	return 0;
876292d6	486	}
bef11c88	487
c11cd416	488	static int __init imx1_timer_init_dt(struct device_node *np)
bef11c88	489	{
c11cd416	490	return mxc_timer_init_dt(np, GPT_TYPE_IMX1);
bef11c88 SG	491	}
bef11c88 SG	492
c11cd416	493	static int __init imx21_timer_init_dt(struct device_node *np)
bef11c88	494	{
c11cd416	495	return mxc_timer_init_dt(np, GPT_TYPE_IMX21);
bef11c88 SG	496	}
bef11c88 SG	497
c11cd416	498	static int __init imx31_timer_init_dt(struct device_node *np)
bef11c88 SG	499	{
	500	enum imx_gpt_type type = GPT_TYPE_IMX31;
	501
	502	/*
	503	* We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	504	* GPT device, while they actually have different programming model.
	505	* This is a workaround to keep the existing i.MX6DL/S DTBs continue
	506	* working with the new kernel.
	507	*/
	508	if (of_machine_is_compatible("fsl,imx6dl"))
	509	type = GPT_TYPE_IMX6DL;
	510
c11cd416	511	return mxc_timer_init_dt(np, type);
bef11c88 SG	512	}
bef11c88 SG	513
c11cd416	514	static int __init imx6dl_timer_init_dt(struct device_node *np)
bef11c88	515	{
c11cd416	516	return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
bef11c88 SG	517	}
bef11c88 SG	518
17273395 DL	519	TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
	520	TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
	521	TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
	522	TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
	523	TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
	524	TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
	525	TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
	526	TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
	527	TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
	528	TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
	529	TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
	530	TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);