[linux-2.6-block.git] / drivers / clocksource / timer-imx-gpt.c

// SPDX-License-Identifier: GPL-2.0+
//
//  Copyright (C) 2000-2001 Deep Blue Solutions
//  Copyright (C) 2002 Shane Nay (shane@minirl.com)
//  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
//  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

/*
 * There are 4 versions of the timer hardware on Freescale MXC hardware.
 *  - MX1/MXL
 *  - MX21, MX27.
 *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
 *  - MX6DL, MX6SX, MX6Q(rev1.1+)
 */
enum imx_gpt_type {
	GPT_TYPE_IMX1,		/* i.MX1 */
	GPT_TYPE_IMX21,		/* i.MX21/27 */
	GPT_TYPE_IMX31,		/* i.MX31/35/25/37/51/6Q */
	GPT_TYPE_IMX6DL,	/* i.MX6DL/SX/SL */
};

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5, MX6 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_CLK_PER		(2 << 6)
#define V2_TCTL_CLK_OSC_DIV8	(5 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_TCTL_24MEN		(1 << 10)
#define V2_TPRER_PRE24M		12
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define V2_TIMER_RATE_OSC_DIV8	3000000

struct imx_timer {
	enum imx_gpt_type type;
	void __iomem *base;
	int irq;
	struct clk *clk_per;
	struct clk *clk_ipg;
	const struct imx_gpt_data *gpt;
	struct clock_event_device ced;
};

struct imx_gpt_data {
	int reg_tstat;
	int reg_tcn;
	int reg_tcmp;
	void (*gpt_setup_tctl)(struct imx_timer *imxtm);
	void (*gpt_irq_enable)(struct imx_timer *imxtm);
	void (*gpt_irq_disable)(struct imx_timer *imxtm);
	void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
	int (*set_next_event)(unsigned long evt,
			      struct clock_event_device *ced);
};

static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
{
	return container_of(ced, struct imx_timer, ced);
}

static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}

static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + V2_IR);
}

static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}

static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
{
	writel_relaxed(1<<0, imxtm->base + V2_IR);
}

static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
}

static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				imxtm->base + MX1_2_TSTAT);
}

static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
}

static void __iomem *sched_clock_reg;

static u64 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
}

#if defined(CONFIG_ARM)
static struct delay_timer imx_delay_timer;

static unsigned long imx_read_current_timer(void)
{
	return readl_relaxed(sched_clock_reg);
}
#endif

static int __init mxc_clocksource_init(struct imx_timer *imxtm)
{
	unsigned int c = clk_get_rate(imxtm->clk_per);
	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;

#if defined(CONFIG_ARM)
	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	imx_delay_timer.freq = c;
	register_current_timer_delay(&imx_delay_timer);
#endif

	sched_clock_reg = reg;

	sched_clock_register(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);

	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + V2_TCMP);

	return evt < 0x7fffffff &&
		(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

static int mxc_shutdown(struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	u32 tcn;

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
	/* Set event time into far-far future */
	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

	/* Clear pending interrupt */
	imxtm->gpt->gpt_irq_acknowledge(imxtm);

#ifdef DEBUG
	printk(KERN_INFO "%s: changing mode\n", __func__);
#endif /* DEBUG */

	return 0;
}

static int mxc_set_oneshot(struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	if (!clockevent_state_oneshot(ced)) {
		u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
		/* Set event time into far-far future */
		writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

		/* Clear pending interrupt */
		imxtm->gpt->gpt_irq_acknowledge(imxtm);
	}

#ifdef DEBUG
	printk(KERN_INFO "%s: changing mode\n", __func__);
#endif /* DEBUG */

	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
	imxtm->gpt->gpt_irq_enable(imxtm);

	return 0;
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ced = dev_id;
	struct imx_timer *imxtm = to_imx_timer(ced);
	uint32_t tstat;

	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);

	imxtm->gpt->gpt_irq_acknowledge(imxtm);

	ced->event_handler(ced);

	return IRQ_HANDLED;
}

static int __init mxc_clockevent_init(struct imx_timer *imxtm)
{
	struct clock_event_device *ced = &imxtm->ced;

	ced->name = "mxc_timer1";
	ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
	ced->set_state_shutdown = mxc_shutdown;
	ced->set_state_oneshot = mxc_set_oneshot;
	ced->tick_resume = mxc_shutdown;
	ced->set_next_event = imxtm->gpt->set_next_event;
	ced->rating = 200;
	ced->cpumask = cpumask_of(0);
	ced->irq = imxtm->irq;
	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
					0xff, 0xfffffffe);

	return request_irq(imxtm->irq, mxc_timer_interrupt,
			   IRQF_TIMER | IRQF_IRQPOLL, "i.MX Timer Tick", ced);
}

static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
	else
		tctl_val |= V2_TCTL_CLK_PER;

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
		/* 24 / 8 = 3 MHz */
		writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
		tctl_val |= V2_TCTL_24MEN;
	} else {
		tctl_val |= V2_TCTL_CLK_PER;
	}

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static const struct imx_gpt_data imx1_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx1_gpt_irq_enable,
	.gpt_irq_disable = imx1_gpt_irq_disable,
	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx1_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx21_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx1_gpt_irq_enable,
	.gpt_irq_disable = imx1_gpt_irq_disable,
	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx1_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx31_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx31_gpt_irq_enable,
	.gpt_irq_disable = imx31_gpt_irq_disable,
	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx31_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static const struct imx_gpt_data imx6dl_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx31_gpt_irq_enable,
	.gpt_irq_disable = imx31_gpt_irq_disable,
	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static int __init _mxc_timer_init(struct imx_timer *imxtm)
{
	int ret;

	switch (imxtm->type) {
	case GPT_TYPE_IMX1:
		imxtm->gpt = &imx1_gpt_data;
		break;
	case GPT_TYPE_IMX21:
		imxtm->gpt = &imx21_gpt_data;
		break;
	case GPT_TYPE_IMX31:
		imxtm->gpt = &imx31_gpt_data;
		break;
	case GPT_TYPE_IMX6DL:
		imxtm->gpt = &imx6dl_gpt_data;
		break;
	default:
		return -EINVAL;
	}

	if (IS_ERR(imxtm->clk_per)) {
		pr_err("i.MX timer: unable to get clk\n");
		return PTR_ERR(imxtm->clk_per);
	}

	if (!IS_ERR(imxtm->clk_ipg))
		clk_prepare_enable(imxtm->clk_ipg);

	clk_prepare_enable(imxtm->clk_per);

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	writel_relaxed(0, imxtm->base + MXC_TCTL);
	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */

	imxtm->gpt->gpt_setup_tctl(imxtm);

	/* init and register the timer to the framework */
	ret = mxc_clocksource_init(imxtm);
	if (ret)
		return ret;

	return mxc_clockevent_init(imxtm);
}

static int __init mxc_timer_init_dt(struct device_node *np,  enum imx_gpt_type type)
{
	struct imx_timer *imxtm;
	static int initialized;
	int ret;

	/* Support one instance only */
	if (initialized)
		return 0;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	if (!imxtm)
		return -ENOMEM;

	imxtm->base = of_iomap(np, 0);
	if (!imxtm->base) {
		ret = -ENXIO;
		goto err_kfree;
	}

	imxtm->irq = irq_of_parse_and_map(np, 0);
	if (imxtm->irq <= 0) {
		ret = -EINVAL;
		goto err_kfree;
	}

	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");

	/* Try osc_per first, and fall back to per otherwise */
	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	if (IS_ERR(imxtm->clk_per))
		imxtm->clk_per = of_clk_get_by_name(np, "per");

	imxtm->type = type;

	ret = _mxc_timer_init(imxtm);
	if (ret)
		goto err_kfree;

	initialized = 1;

	return 0;

err_kfree:
	kfree(imxtm);
	return ret;
}

static int __init imx1_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX1);
}

static int __init imx21_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX21);
}

static int __init imx31_timer_init_dt(struct device_node *np)
{
	enum imx_gpt_type type = GPT_TYPE_IMX31;

	/*
	 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	 * GPT device, while they actually have different programming model.
	 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
	 * working with the new kernel.
	 */
	if (of_machine_is_compatible("fsl,imx6dl"))
		type = GPT_TYPE_IMX6DL;

	return mxc_timer_init_dt(np, type);
}

static int __init imx6dl_timer_init_dt(struct device_node *np)
{
	return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
}

TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
Commit	Line	Data
c53bb605 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2000-2001 Deep Blue Solutions
	4	// Copyright (C) 2002 Shane Nay (shane@minirl.com)
	5	// Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	6	// Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
d0f349fb JB	7
	8	#include <linux/interrupt.h>
	9	#include <linux/irq.h>
	10	#include <linux/clockchips.h>
	11	#include <linux/clk.h>
1119c84a	12	#include <linux/delay.h>
821dc4df	13	#include <linux/err.h>
38ff87f7	14	#include <linux/sched_clock.h>
6dd74782	15	#include <linux/slab.h>
876292d6 GC	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_irq.h>
d0f349fb	19
0f3332c4	20	/*
65d0a16d SW	21	* There are 4 versions of the timer hardware on Freescale MXC hardware.
	22	* - MX1/MXL
	23	* - MX21, MX27.
	24	* - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
	25	* - MX6DL, MX6SX, MX6Q(rev1.1+)
0f3332c4	26	*/
281bf6b9 UKK	27	enum imx_gpt_type {
	28	GPT_TYPE_IMX1, /* i.MX1 */
	29	GPT_TYPE_IMX21, /* i.MX21/27 */
	30	GPT_TYPE_IMX31, /* i.MX31/35/25/37/51/6Q */
	31	GPT_TYPE_IMX6DL, /* i.MX6DL/SX/SL */
	32	};
0f3332c4	33
ec996ba9 SH	34	/* defines common for all i.MX */
ec996ba9 SH	35	#define MXC_TCTL 0x00
0f3332c4	36	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	37	#define MXC_TPRER 0x04
	38
	39	/* MX1, MX21, MX27 */
	40	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	41	#define MX1_2_TCTL_IRQEN (1 << 4)
	42	#define MX1_2_TCTL_FRR (1 << 8)
	43	#define MX1_2_TCMP 0x08
	44	#define MX1_2_TCN 0x10
	45	#define MX1_2_TSTAT 0x14
	46
	47	/* MX21, MX27 */
	48	#define MX2_TSTAT_CAPT (1 << 1)
	49	#define MX2_TSTAT_COMP (1 << 0)
	50
bad3db10	51	/* MX31, MX35, MX25, MX5, MX6 */
38a66f51 AK	52	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
38a66f51 AK	53	#define V2_TCTL_CLK_IPG (1 << 6)
1f152b48	54	#define V2_TCTL_CLK_PER (2 << 6)
bad3db10	55	#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
38a66f51	56	#define V2_TCTL_FRR (1 << 9)
bad3db10 AH	57	#define V2_TCTL_24MEN (1 << 10)
bad3db10 AH	58	#define V2_TPRER_PRE24M 12
38a66f51 AK	59	#define V2_IR 0x0c
	60	#define V2_TSTAT 0x08
	61	#define V2_TSTAT_OF1 (1 << 0)
	62	#define V2_TCN 0x24
	63	#define V2_TCMP 0x10
d0f349fb	64
bad3db10 AH	65	#define V2_TIMER_RATE_OSC_DIV8 3000000
bad3db10 AH	66
6dd74782	67	struct imx_timer {
0931aff7	68	enum imx_gpt_type type;
6dd74782 SG	69	void __iomem *base;
	70	int irq;
	71	struct clk *clk_per;
	72	struct clk *clk_ipg;
9c8694bd	73	const struct imx_gpt_data *gpt;
e510d201	74	struct clock_event_device ced;
9c8694bd SG	75	};
	76
	77	struct imx_gpt_data {
24f74ad1 SG	78	int reg_tstat;
	79	int reg_tcn;
	80	int reg_tcmp;
9c8694bd	81	void (gpt_setup_tctl)(struct imx_timer imxtm);
db2ae4b4 SG	82	void (gpt_irq_enable)(struct imx_timer imxtm);
	83	void (gpt_irq_disable)(struct imx_timer imxtm);
	84	void (gpt_irq_acknowledge)(struct imx_timer imxtm);
5ab0475b SG	85	int (*set_next_event)(unsigned long evt,
5ab0475b SG	86	struct clock_event_device *ced);
6dd74782 SG	87	};
6dd74782 SG	88
e510d201 SG	89	static inline struct imx_timer to_imx_timer(struct clock_event_device ced)
	90	{
	91	return container_of(ced, struct imx_timer, ced);
	92	}
	93
db2ae4b4	94	static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
d0f349fb	95	{
ec996ba9 SH	96	unsigned int tmp;
ec996ba9 SH	97
db2ae4b4 SG	98	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
db2ae4b4 SG	99	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
ec996ba9 SH	100	}
ec996ba9 SH	101
db2ae4b4	102	static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
ec996ba9	103	{
db2ae4b4 SG	104	writel_relaxed(0, imxtm->base + V2_IR);
db2ae4b4 SG	105	}
db2ae4b4 SG	106
	107	static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
	108	{
	109	unsigned int tmp;
	110
	111	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	112	writel_relaxed(tmp \| MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
	113	}
db2ae4b4 SG	114
	115	static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
	116	{
	117	writel_relaxed(1<<0, imxtm->base + V2_IR);
	118	}
db2ae4b4 SG	119
	120	static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
	121	{
	122	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	123	}
ec996ba9 SH	124
db2ae4b4	125	static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
ec996ba9	126	{
db2ae4b4	127	writel_relaxed(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
89955520	128	imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	129	}
ec996ba9 SH	130
db2ae4b4 SG	131	static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
	132	{
	133	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
	134	}
db2ae4b4	135
234b6ced	136	static void __iomem *sched_clock_reg;
d0f349fb	137
b93767e3	138	static u64 notrace mxc_read_sched_clock(void)
c124befc	139	{
c7770bba	140	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
c124befc JW	141	}
c124befc JW	142
df181e38	143	#if defined(CONFIG_ARM)
1119c84a SAS	144	static struct delay_timer imx_delay_timer;
	145
	146	static unsigned long imx_read_current_timer(void)
	147	{
c7770bba	148	return readl_relaxed(sched_clock_reg);
1119c84a	149	}
df181e38	150	#endif
1119c84a	151
6dd74782	152	static int __init mxc_clocksource_init(struct imx_timer *imxtm)
d0f349fb	153	{
6dd74782	154	unsigned int c = clk_get_rate(imxtm->clk_per);
24f74ad1	155	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
d0f349fb	156
df181e38	157	#if defined(CONFIG_ARM)
1119c84a SAS	158	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	159	imx_delay_timer.freq = c;
	160	register_current_timer_delay(&imx_delay_timer);
df181e38	161	#endif
1119c84a	162
234b6ced	163	sched_clock_reg = reg;
ec996ba9	164
b93767e3	165	sched_clock_register(mxc_read_sched_clock, 32, c);
234b6ced RK	166	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	167	clocksource_mmio_readl_up);
d0f349fb JB	168	}
	169
	170	/* clock event */
	171
ec996ba9	172	static int mx1_2_set_next_event(unsigned long evt,
89955520	173	struct clock_event_device *ced)
d0f349fb	174	{
89955520	175	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	176	unsigned long tcmp;
d0f349fb JB	177
89955520	178	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
d0f349fb	179
89955520	180	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
ec996ba9	181
89955520	182	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
ec996ba9 SH	183	-ETIME : 0;
	184	}
	185
38a66f51	186	static int v2_set_next_event(unsigned long evt,
89955520	187	struct clock_event_device *ced)
ec996ba9	188	{
89955520	189	struct imx_timer *imxtm = to_imx_timer(ced);
ec996ba9 SH	190	unsigned long tcmp;
ec996ba9 SH	191
89955520	192	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
ec996ba9	193
89955520	194	writel_relaxed(tcmp, imxtm->base + V2_TCMP);
ec996ba9	195
eea8e326	196	return evt < 0x7fffffff &&
89955520	197	(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
d0f349fb JB	198	-ETIME : 0;
	199	}
	200
26b91f04 VK	201	static int mxc_shutdown(struct clock_event_device *ced)
	202	{
	203	struct imx_timer *imxtm = to_imx_timer(ced);
26b91f04 VK	204	u32 tcn;
26b91f04 VK	205
26b91f04 VK	206	/* Disable interrupt in GPT module */
	207	imxtm->gpt->gpt_irq_disable(imxtm);
	208
	209	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
	210	/* Set event time into far-far future */
	211	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
	212
	213	/* Clear pending interrupt */
	214	imxtm->gpt->gpt_irq_acknowledge(imxtm);
	215
d0f349fb	216	#ifdef DEBUG
26b91f04	217	printk(KERN_INFO "%s: changing mode\n", __func__);
d0f349fb JB	218	#endif /* DEBUG */
d0f349fb JB	219
26b91f04 VK	220	return 0;
	221	}
	222
	223	static int mxc_set_oneshot(struct clock_event_device *ced)
d0f349fb	224	{
e510d201	225	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	226
d0f349fb JB	227	/* Disable interrupt in GPT module */
db2ae4b4	228	imxtm->gpt->gpt_irq_disable(imxtm);
d0f349fb	229
26b91f04	230	if (!clockevent_state_oneshot(ced)) {
24f74ad1	231	u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
d0f349fb	232	/* Set event time into far-far future */
24f74ad1	233	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
ec996ba9	234
d0f349fb	235	/* Clear pending interrupt */
db2ae4b4	236	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb JB	237	}
	238
	239	#ifdef DEBUG
26b91f04	240	printk(KERN_INFO "%s: changing mode\n", __func__);
d0f349fb JB	241	#endif /* DEBUG */
d0f349fb JB	242
d0f349fb JB	243	/*
	244	* Do not put overhead of interrupt enable/disable into
	245	* mxc_set_next_event(), the core has about 4 minutes
	246	* to call mxc_set_next_event() or shutdown clock after
	247	* mode switching
	248	*/
26b91f04	249	imxtm->gpt->gpt_irq_enable(imxtm);
26b91f04 VK	250
26b91f04 VK	251	return 0;
d0f349fb JB	252	}
	253
	254	/*
	255	* IRQ handler for the timer
	256	*/
	257	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	258	{
e510d201	259	struct clock_event_device *ced = dev_id;
24f74ad1	260	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	261	uint32_t tstat;
d0f349fb JB	262
24f74ad1	263	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
d0f349fb	264
db2ae4b4	265	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb	266
e510d201	267	ced->event_handler(ced);
d0f349fb JB	268
	269	return IRQ_HANDLED;
	270	}
	271
6dd74782	272	static int __init mxc_clockevent_init(struct imx_timer *imxtm)
d0f349fb	273	{
e510d201	274	struct clock_event_device *ced = &imxtm->ced;
e510d201	275
e510d201	276	ced->name = "mxc_timer1";
f1c08c9b	277	ced->features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_DYNIRQ;
26b91f04 VK	278	ced->set_state_shutdown = mxc_shutdown;
	279	ced->set_state_oneshot = mxc_set_oneshot;
	280	ced->tick_resume = mxc_shutdown;
e510d201 SG	281	ced->set_next_event = imxtm->gpt->set_next_event;
	282	ced->rating = 200;
	283	ced->cpumask = cpumask_of(0);
f1c08c9b	284	ced->irq = imxtm->irq;
e510d201	285	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
838a2ae8	286	0xff, 0xfffffffe);
d0f349fb	287
cc2550b4	288	return request_irq(imxtm->irq, mxc_timer_interrupt,
cc2550b4	289	IRQF_TIMER \| IRQF_IRQPOLL, "i.MX Timer Tick", ced);
d0f349fb JB	290	}
d0f349fb JB	291
9c8694bd SG	292	static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
	293	{
	294	u32 tctl_val;
	295
	296	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	297	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	298	}
9c8694bd SG	299
	300	static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
	301	{
	302	u32 tctl_val;
	303
	304	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	305	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
	306	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	307	else
	308	tctl_val \|= V2_TCTL_CLK_PER;
	309
	310	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	311	}
	312
	313	static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
d0f349fb	314	{
9c8694bd SG	315	u32 tctl_val;
	316
	317	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	318	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
	319	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	320	/* 24 / 8 = 3 MHz */
	321	writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
	322	tctl_val \|= V2_TCTL_24MEN;
	323	} else {
	324	tctl_val \|= V2_TCTL_CLK_PER;
	325	}
	326
	327	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	328	}
821dc4df	329
9c8694bd	330	static const struct imx_gpt_data imx1_gpt_data = {
24f74ad1 SG	331	.reg_tstat = MX1_2_TSTAT,
	332	.reg_tcn = MX1_2_TCN,
	333	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	334	.gpt_irq_enable = imx1_gpt_irq_enable,
	335	.gpt_irq_disable = imx1_gpt_irq_disable,
	336	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
9c8694bd	337	.gpt_setup_tctl = imx1_gpt_setup_tctl,
5ab0475b	338	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	339	};
	340
	341	static const struct imx_gpt_data imx21_gpt_data = {
24f74ad1 SG	342	.reg_tstat = MX1_2_TSTAT,
	343	.reg_tcn = MX1_2_TCN,
	344	.reg_tcmp = MX1_2_TCMP,
95aded1b UKK	345	.gpt_irq_enable = imx1_gpt_irq_enable,
95aded1b UKK	346	.gpt_irq_disable = imx1_gpt_irq_disable,
db2ae4b4	347	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
95aded1b	348	.gpt_setup_tctl = imx1_gpt_setup_tctl,
5ab0475b	349	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	350	};
	351
	352	static const struct imx_gpt_data imx31_gpt_data = {
24f74ad1 SG	353	.reg_tstat = V2_TSTAT,
	354	.reg_tcn = V2_TCN,
	355	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	356	.gpt_irq_enable = imx31_gpt_irq_enable,
	357	.gpt_irq_disable = imx31_gpt_irq_disable,
	358	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
9c8694bd	359	.gpt_setup_tctl = imx31_gpt_setup_tctl,
5ab0475b	360	.set_next_event = v2_set_next_event,
9c8694bd SG	361	};
	362
	363	static const struct imx_gpt_data imx6dl_gpt_data = {
24f74ad1 SG	364	.reg_tstat = V2_TSTAT,
	365	.reg_tcn = V2_TCN,
	366	.reg_tcmp = V2_TCMP,
95aded1b UKK	367	.gpt_irq_enable = imx31_gpt_irq_enable,
	368	.gpt_irq_disable = imx31_gpt_irq_disable,
	369	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
9c8694bd	370	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
5ab0475b	371	.set_next_event = v2_set_next_event,
9c8694bd SG	372	};
9c8694bd SG	373
c11cd416	374	static int __init _mxc_timer_init(struct imx_timer *imxtm)
9c8694bd	375	{
c11cd416 DL	376	int ret;
c11cd416 DL	377
9c8694bd SG	378	switch (imxtm->type) {
	379	case GPT_TYPE_IMX1:
	380	imxtm->gpt = &imx1_gpt_data;
	381	break;
	382	case GPT_TYPE_IMX21:
	383	imxtm->gpt = &imx21_gpt_data;
	384	break;
	385	case GPT_TYPE_IMX31:
	386	imxtm->gpt = &imx31_gpt_data;
	387	break;
	388	case GPT_TYPE_IMX6DL:
	389	imxtm->gpt = &imx6dl_gpt_data;
	390	break;
	391	default:
c11cd416	392	return -EINVAL;
9c8694bd SG	393	}
9c8694bd SG	394
6dd74782	395	if (IS_ERR(imxtm->clk_per)) {
2cfb4518	396	pr_err("i.MX timer: unable to get clk\n");
c11cd416	397	return PTR_ERR(imxtm->clk_per);
821dc4df	398	}
ec996ba9	399
6dd74782 SG	400	if (!IS_ERR(imxtm->clk_ipg))
6dd74782 SG	401	clk_prepare_enable(imxtm->clk_ipg);
2cfb4518	402
6dd74782	403	clk_prepare_enable(imxtm->clk_per);
d0f349fb JB	404
	405	/*
	406	* Initialise to a known state (all timers off, and timing reset)
	407	*/
d0f349fb	408
6dd74782 SG	409	writel_relaxed(0, imxtm->base + MXC_TCTL);
6dd74782 SG	410	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
ec996ba9	411
9c8694bd	412	imxtm->gpt->gpt_setup_tctl(imxtm);
d0f349fb JB	413
d0f349fb JB	414	/* init and register the timer to the framework */
c11cd416 DL	415	ret = mxc_clocksource_init(imxtm);
	416	if (ret)
	417	return ret;
	418
	419	return mxc_clockevent_init(imxtm);
d0f349fb	420	}
876292d6	421
c11cd416	422	static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
876292d6	423	{
6dd74782 SG	424	struct imx_timer *imxtm;
6dd74782 SG	425	static int initialized;
c11cd416	426	int ret;
876292d6	427
6dd74782 SG	428	/* Support one instance only */
6dd74782 SG	429	if (initialized)
c11cd416	430	return 0;
fd4959d8	431
6dd74782	432	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
c11cd416 DL	433	if (!imxtm)
c11cd416 DL	434	return -ENOMEM;
876292d6	435
6dd74782	436	imxtm->base = of_iomap(np, 0);
8051a993 JB	437	if (!imxtm->base) {
	438	ret = -ENXIO;
	439	goto err_kfree;
	440	}
c11cd416	441
6dd74782	442	imxtm->irq = irq_of_parse_and_map(np, 0);
8051a993 JB	443	if (imxtm->irq <= 0) {
	444	ret = -EINVAL;
	445	goto err_kfree;
	446	}
6dd74782 SG	447
6dd74782 SG	448	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
f4696752	449
bad3db10	450	/* Try osc_per first, and fall back to per otherwise */
6dd74782 SG	451	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	452	if (IS_ERR(imxtm->clk_per))
	453	imxtm->clk_per = of_clk_get_by_name(np, "per");
	454
bef11c88 SG	455	imxtm->type = type;
bef11c88 SG	456
c11cd416 DL	457	ret = _mxc_timer_init(imxtm);
c11cd416 DL	458	if (ret)
8051a993	459	goto err_kfree;
bad3db10	460
6dd74782	461	initialized = 1;
c11cd416 DL	462
c11cd416 DL	463	return 0;
8051a993 JB	464
	465	err_kfree:
	466	kfree(imxtm);
	467	return ret;
876292d6	468	}
bef11c88	469
c11cd416	470	static int __init imx1_timer_init_dt(struct device_node *np)
bef11c88	471	{
c11cd416	472	return mxc_timer_init_dt(np, GPT_TYPE_IMX1);
bef11c88 SG	473	}
bef11c88 SG	474
c11cd416	475	static int __init imx21_timer_init_dt(struct device_node *np)
bef11c88	476	{
c11cd416	477	return mxc_timer_init_dt(np, GPT_TYPE_IMX21);
bef11c88 SG	478	}
bef11c88 SG	479
c11cd416	480	static int __init imx31_timer_init_dt(struct device_node *np)
bef11c88 SG	481	{
	482	enum imx_gpt_type type = GPT_TYPE_IMX31;
	483
	484	/*
	485	* We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	486	* GPT device, while they actually have different programming model.
	487	* This is a workaround to keep the existing i.MX6DL/S DTBs continue
	488	* working with the new kernel.
	489	*/
	490	if (of_machine_is_compatible("fsl,imx6dl"))
	491	type = GPT_TYPE_IMX6DL;
	492
c11cd416	493	return mxc_timer_init_dt(np, type);
bef11c88 SG	494	}
bef11c88 SG	495
c11cd416	496	static int __init imx6dl_timer_init_dt(struct device_node *np)
bef11c88	497	{
c11cd416	498	return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
bef11c88 SG	499	}
bef11c88 SG	500
17273395 DL	501	TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
	502	TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
	503	TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
	504	TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
	505	TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
	506	TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
	507	TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
	508	TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
	509	TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
	510	TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
	511	TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
	512	TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);