[linux-2.6-block.git] / drivers / clocksource / timer-fttmr010.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Faraday Technology FTTMR010 timer driver
 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
 *
 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
 * Copyright (C) 2001-2006 Storlink, Corp.
 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 */
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/delay.h>

/*
 * Register definitions common for all the timer variants.
 */
#define TIMER1_COUNT		(0x00)
#define TIMER1_LOAD		(0x04)
#define TIMER1_MATCH1		(0x08)
#define TIMER1_MATCH2		(0x0c)
#define TIMER2_COUNT		(0x10)
#define TIMER2_LOAD		(0x14)
#define TIMER2_MATCH1		(0x18)
#define TIMER2_MATCH2		(0x1c)
#define TIMER3_COUNT		(0x20)
#define TIMER3_LOAD		(0x24)
#define TIMER3_MATCH1		(0x28)
#define TIMER3_MATCH2		(0x2c)
#define TIMER_CR		(0x30)

/*
 * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
 */
#define TIMER_1_CR_ENABLE	BIT(0)
#define TIMER_1_CR_CLOCK	BIT(1)
#define TIMER_1_CR_INT		BIT(2)
#define TIMER_2_CR_ENABLE	BIT(3)
#define TIMER_2_CR_CLOCK	BIT(4)
#define TIMER_2_CR_INT		BIT(5)
#define TIMER_3_CR_ENABLE	BIT(6)
#define TIMER_3_CR_CLOCK	BIT(7)
#define TIMER_3_CR_INT		BIT(8)
#define TIMER_1_CR_UPDOWN	BIT(9)
#define TIMER_2_CR_UPDOWN	BIT(10)
#define TIMER_3_CR_UPDOWN	BIT(11)

/*
 * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
 * The aspeed timers move bits around in the control register and lacks
 * bits for setting the timer to count upwards.
 */
#define TIMER_1_CR_ASPEED_ENABLE	BIT(0)
#define TIMER_1_CR_ASPEED_CLOCK		BIT(1)
#define TIMER_1_CR_ASPEED_INT		BIT(2)
#define TIMER_2_CR_ASPEED_ENABLE	BIT(4)
#define TIMER_2_CR_ASPEED_CLOCK		BIT(5)
#define TIMER_2_CR_ASPEED_INT		BIT(6)
#define TIMER_3_CR_ASPEED_ENABLE	BIT(8)
#define TIMER_3_CR_ASPEED_CLOCK		BIT(9)
#define TIMER_3_CR_ASPEED_INT		BIT(10)

/*
 * Interrupt status/mask register definitions for fttmr010/gemini/moxart
 * timers.
 * The registers don't exist and they are not needed on aspeed timers
 * because:
 *   - aspeed timer overflow interrupt is controlled by bits in Control
 *     Register (TMC30).
 *   - aspeed timers always generate interrupt when either one of the
 *     Match registers equals to Status register.
 */
#define TIMER_INTR_STATE	(0x34)
#define TIMER_INTR_MASK		(0x38)
#define TIMER_1_INT_MATCH1	BIT(0)
#define TIMER_1_INT_MATCH2	BIT(1)
#define TIMER_1_INT_OVERFLOW	BIT(2)
#define TIMER_2_INT_MATCH1	BIT(3)
#define TIMER_2_INT_MATCH2	BIT(4)
#define TIMER_2_INT_OVERFLOW	BIT(5)
#define TIMER_3_INT_MATCH1	BIT(6)
#define TIMER_3_INT_MATCH2	BIT(7)
#define TIMER_3_INT_OVERFLOW	BIT(8)
#define TIMER_INT_ALL_MASK	0x1ff

struct fttmr010 {
	void __iomem *base;
	unsigned int tick_rate;
	bool is_aspeed;
	u32 t1_enable_val;
	struct clock_event_device clkevt;
#ifdef CONFIG_ARM
	struct delay_timer delay_timer;
#endif
};

/*
 * A local singleton used by sched_clock and delay timer reads, which are
 * fast and stateless
 */
static struct fttmr010 *local_fttmr;

static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
{
	return container_of(evt, struct fttmr010, clkevt);
}

static unsigned long fttmr010_read_current_timer_up(void)
{
	return readl(local_fttmr->base + TIMER2_COUNT);
}

static unsigned long fttmr010_read_current_timer_down(void)
{
	return ~readl(local_fttmr->base + TIMER2_COUNT);
}

static u64 notrace fttmr010_read_sched_clock_up(void)
{
	return fttmr010_read_current_timer_up();
}

static u64 notrace fttmr010_read_sched_clock_down(void)
{
	return fttmr010_read_current_timer_down();
}

static int fttmr010_timer_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	if (fttmr010->is_aspeed) {
		/*
		 * ASPEED Timer Controller will load TIMER1_LOAD register
		 * into TIMER1_COUNT register when the timer is re-enabled.
		 */
		writel(cycles, fttmr010->base + TIMER1_LOAD);
	} else {
		/* Setup the match register forward in time */
		cr = readl(fttmr010->base + TIMER1_COUNT);
		writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
	}

	/* Start */
	cr = readl(fttmr010->base + TIMER_CR);
	cr |= fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

static int fttmr010_timer_shutdown(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	/* Setup counter start from 0 or ~0 */
	writel(0, fttmr010->base + TIMER1_COUNT);
	if (fttmr010->is_aspeed) {
		writel(~0, fttmr010->base + TIMER1_LOAD);
	} else {
		writel(0, fttmr010->base + TIMER1_LOAD);

		/* Enable interrupt */
		cr = readl(fttmr010->base + TIMER_INTR_MASK);
		cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
		cr |= TIMER_1_INT_MATCH1;
		writel(cr, fttmr010->base + TIMER_INTR_MASK);
	}

	return 0;
}

static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	/* Setup timer to fire at 1/HZ intervals. */
	if (fttmr010->is_aspeed) {
		writel(period, fttmr010->base + TIMER1_LOAD);
	} else {
		cr = 0xffffffff - (period - 1);
		writel(cr, fttmr010->base + TIMER1_COUNT);
		writel(cr, fttmr010->base + TIMER1_LOAD);

		/* Enable interrupt on overflow */
		cr = readl(fttmr010->base + TIMER_INTR_MASK);
		cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
		cr |= TIMER_1_INT_OVERFLOW;
		writel(cr, fttmr010->base + TIMER_INTR_MASK);
	}

	/* Start the timer */
	cr = readl(fttmr010->base + TIMER_CR);
	cr |= fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
{
	struct fttmr010 *fttmr010;
	int irq;
	struct clk *clk;
	int ret;
	u32 val;

	/*
	 * These implementations require a clock reference.
	 * FIXME: we currently only support clocking using PCLK
	 * and using EXTCLK is not supported in the driver.
	 */
	clk = of_clk_get_by_name(np, "PCLK");
	if (IS_ERR(clk)) {
		pr_err("could not get PCLK\n");
		return PTR_ERR(clk);
	}
	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("failed to enable PCLK\n");
		return ret;
	}

	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
	if (!fttmr010) {
		ret = -ENOMEM;
		goto out_disable_clock;
	}
	fttmr010->tick_rate = clk_get_rate(clk);

	fttmr010->base = of_iomap(np, 0);
	if (!fttmr010->base) {
		pr_err("Can't remap registers\n");
		ret = -ENXIO;
		goto out_free;
	}
	/* IRQ for timer 1 */
	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0) {
		pr_err("Can't parse IRQ\n");
		ret = -EINVAL;
		goto out_unmap;
	}

	/*
	 * The Aspeed timers move bits around in the control register.
	 */
	if (is_aspeed) {
		fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
			TIMER_1_CR_ASPEED_INT;
		fttmr010->is_aspeed = true;
	} else {
		fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;

		/*
		 * Reset the interrupt mask and status
		 */
		writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
		writel(0, fttmr010->base + TIMER_INTR_STATE);
	}

	/*
	 * Enable timer 1 count up, timer 2 count up, except on Aspeed,
	 * where everything just counts down.
	 */
	if (is_aspeed)
		val = TIMER_2_CR_ASPEED_ENABLE;
	else {
		val = TIMER_2_CR_ENABLE | TIMER_1_CR_UPDOWN |
			TIMER_2_CR_UPDOWN;
	}
	writel(val, fttmr010->base + TIMER_CR);

	/*
	 * Setup free-running clocksource timer (interrupts
	 * disabled.)
	 */
	local_fttmr = fttmr010;
	writel(0, fttmr010->base + TIMER2_COUNT);
	writel(0, fttmr010->base + TIMER2_MATCH1);
	writel(0, fttmr010->base + TIMER2_MATCH2);

	if (fttmr010->is_aspeed) {
		writel(~0, fttmr010->base + TIMER2_LOAD);
		clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
				      "FTTMR010-TIMER2",
				      fttmr010->tick_rate,
				      300, 32, clocksource_mmio_readl_down);
		sched_clock_register(fttmr010_read_sched_clock_down, 32,
				     fttmr010->tick_rate);
	} else {
		writel(0, fttmr010->base + TIMER2_LOAD);
		clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
				      "FTTMR010-TIMER2",
				      fttmr010->tick_rate,
				      300, 32, clocksource_mmio_readl_up);
		sched_clock_register(fttmr010_read_sched_clock_up, 32,
				     fttmr010->tick_rate);
	}

	/*
	 * Setup clockevent timer (interrupt-driven) on timer 1.
	 */
	writel(0, fttmr010->base + TIMER1_COUNT);
	writel(0, fttmr010->base + TIMER1_LOAD);
	writel(0, fttmr010->base + TIMER1_MATCH1);
	writel(0, fttmr010->base + TIMER1_MATCH2);
	ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
			  "FTTMR010-TIMER1", &fttmr010->clkevt);
	if (ret) {
		pr_err("FTTMR010-TIMER1 no IRQ\n");
		goto out_unmap;
	}

	fttmr010->clkevt.name = "FTTMR010-TIMER1";
	/* Reasonably fast and accurate clock event */
	fttmr010->clkevt.rating = 300;
	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
		CLOCK_EVT_FEAT_ONESHOT;
	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
	fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
	fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
	fttmr010->clkevt.cpumask = cpumask_of(0);
	fttmr010->clkevt.irq = irq;
	clockevents_config_and_register(&fttmr010->clkevt,
					fttmr010->tick_rate,
					1, 0xffffffff);

#ifdef CONFIG_ARM
	/* Also use this timer for delays */
	if (fttmr010->is_aspeed)
		fttmr010->delay_timer.read_current_timer =
			fttmr010_read_current_timer_down;
	else
		fttmr010->delay_timer.read_current_timer =
			fttmr010_read_current_timer_up;
	fttmr010->delay_timer.freq = fttmr010->tick_rate;
	register_current_timer_delay(&fttmr010->delay_timer);
#endif

	return 0;

out_unmap:
	iounmap(fttmr010->base);
out_free:
	kfree(fttmr010);
out_disable_clock:
	clk_disable_unprepare(clk);

	return ret;
}

static __init int aspeed_timer_init(struct device_node *np)
{
	return fttmr010_common_init(np, true);
}

static __init int fttmr010_timer_init(struct device_node *np)
{
	return fttmr010_common_init(np, false);
}

TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
4750535b	2	/*
f5bf0ee4	3	* Faraday Technology FTTMR010 timer driver
4750535b LW	4	* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
	5	*
	6	* Based on a rewrite of arch/arm/mach-gemini/timer.c:
	7	* Copyright (C) 2001-2006 Storlink, Corp.
	8	* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
	9	*/
	10	#include <linux/interrupt.h>
	11	#include <linux/io.h>
	12	#include <linux/of.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
4750535b LW	15	#include <linux/clockchips.h>
	16	#include <linux/clocksource.h>
	17	#include <linux/sched_clock.h>
28e71e2f	18	#include <linux/clk.h>
e7bad212	19	#include <linux/slab.h>
d0d76d57	20	#include <linux/bitops.h>
385c98fc	21	#include <linux/delay.h>
4750535b LW	22
4750535b LW	23	/*
86fe57fc	24	* Register definitions common for all the timer variants.
4750535b LW	25	*/
	26	#define TIMER1_COUNT (0x00)
	27	#define TIMER1_LOAD (0x04)
	28	#define TIMER1_MATCH1 (0x08)
	29	#define TIMER1_MATCH2 (0x0c)
	30	#define TIMER2_COUNT (0x10)
	31	#define TIMER2_LOAD (0x14)
	32	#define TIMER2_MATCH1 (0x18)
	33	#define TIMER2_MATCH2 (0x1c)
	34	#define TIMER3_COUNT (0x20)
	35	#define TIMER3_LOAD (0x24)
	36	#define TIMER3_MATCH1 (0x28)
	37	#define TIMER3_MATCH2 (0x2c)
	38	#define TIMER_CR (0x30)
4750535b	39
86fe57fc TR	40	/*
	41	* Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
	42	*/
d0d76d57 LW	43	#define TIMER_1_CR_ENABLE BIT(0)
	44	#define TIMER_1_CR_CLOCK BIT(1)
	45	#define TIMER_1_CR_INT BIT(2)
	46	#define TIMER_2_CR_ENABLE BIT(3)
	47	#define TIMER_2_CR_CLOCK BIT(4)
	48	#define TIMER_2_CR_INT BIT(5)
	49	#define TIMER_3_CR_ENABLE BIT(6)
	50	#define TIMER_3_CR_CLOCK BIT(7)
	51	#define TIMER_3_CR_INT BIT(8)
	52	#define TIMER_1_CR_UPDOWN BIT(9)
	53	#define TIMER_2_CR_UPDOWN BIT(10)
	54	#define TIMER_3_CR_UPDOWN BIT(11)
4750535b	55
ec14ba1e	56	/*
86fe57fc TR	57	* Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
	58	* The aspeed timers move bits around in the control register and lacks
	59	* bits for setting the timer to count upwards.
ec14ba1e LW	60	*/
	61	#define TIMER_1_CR_ASPEED_ENABLE BIT(0)
	62	#define TIMER_1_CR_ASPEED_CLOCK BIT(1)
	63	#define TIMER_1_CR_ASPEED_INT BIT(2)
	64	#define TIMER_2_CR_ASPEED_ENABLE BIT(4)
	65	#define TIMER_2_CR_ASPEED_CLOCK BIT(5)
	66	#define TIMER_2_CR_ASPEED_INT BIT(6)
	67	#define TIMER_3_CR_ASPEED_ENABLE BIT(8)
	68	#define TIMER_3_CR_ASPEED_CLOCK BIT(9)
	69	#define TIMER_3_CR_ASPEED_INT BIT(10)
	70
86fe57fc TR	71	/*
	72	* Interrupt status/mask register definitions for fttmr010/gemini/moxart
	73	* timers.
	74	* The registers don't exist and they are not needed on aspeed timers
	75	* because:
	76	* - aspeed timer overflow interrupt is controlled by bits in Control
	77	* Register (TMC30).
	78	* - aspeed timers always generate interrupt when either one of the
	79	* Match registers equals to Status register.
	80	*/
	81	#define TIMER_INTR_STATE (0x34)
	82	#define TIMER_INTR_MASK (0x38)
d0d76d57 LW	83	#define TIMER_1_INT_MATCH1 BIT(0)
	84	#define TIMER_1_INT_MATCH2 BIT(1)
	85	#define TIMER_1_INT_OVERFLOW BIT(2)
	86	#define TIMER_2_INT_MATCH1 BIT(3)
	87	#define TIMER_2_INT_MATCH2 BIT(4)
	88	#define TIMER_2_INT_OVERFLOW BIT(5)
	89	#define TIMER_3_INT_MATCH1 BIT(6)
	90	#define TIMER_3_INT_MATCH2 BIT(7)
	91	#define TIMER_3_INT_OVERFLOW BIT(8)
4750535b LW	92	#define TIMER_INT_ALL_MASK 0x1ff
4750535b LW	93
e7bad212 LW	94	struct fttmr010 {
	95	void __iomem *base;
	96	unsigned int tick_rate;
86fe57fc	97	bool is_aspeed;
ec14ba1e	98	u32 t1_enable_val;
e7bad212	99	struct clock_event_device clkevt;
385c98fc LW	100	#ifdef CONFIG_ARM
	101	struct delay_timer delay_timer;
	102	#endif
e7bad212 LW	103	};
e7bad212 LW	104
385c98fc LW	105	/*
	106	* A local singleton used by sched_clock and delay timer reads, which are
	107	* fast and stateless
	108	*/
e7bad212 LW	109	static struct fttmr010 *local_fttmr;
	110
	111	static inline struct fttmr010 to_fttmr010(struct clock_event_device evt)
	112	{
	113	return container_of(evt, struct fttmr010, clkevt);
	114	}
4750535b	115
c4779902	116	static unsigned long fttmr010_read_current_timer_up(void)
4750535b	117	{
b589da8b	118	return readl(local_fttmr->base + TIMER2_COUNT);
4750535b LW	119	}
4750535b LW	120
c4779902	121	static unsigned long fttmr010_read_current_timer_down(void)
740e237a LW	122	{
	123	return ~readl(local_fttmr->base + TIMER2_COUNT);
	124	}
	125
c4779902	126	static u64 notrace fttmr010_read_sched_clock_up(void)
385c98fc	127	{
c4779902	128	return fttmr010_read_current_timer_up();
385c98fc LW	129	}
385c98fc LW	130
c4779902	131	static u64 notrace fttmr010_read_sched_clock_down(void)
385c98fc	132	{
c4779902	133	return fttmr010_read_current_timer_down();
385c98fc LW	134	}
385c98fc LW	135
f5bf0ee4	136	static int fttmr010_timer_set_next_event(unsigned long cycles,
4750535b LW	137	struct clock_event_device *evt)
4750535b LW	138	{
e7bad212	139	struct fttmr010 *fttmr010 = to_fttmr010(evt);
4750535b LW	140	u32 cr;
4750535b LW	141
ec14ba1e LW	142	/* Stop */
	143	cr = readl(fttmr010->base + TIMER_CR);
	144	cr &= ~fttmr010->t1_enable_val;
	145	writel(cr, fttmr010->base + TIMER_CR);
	146
86fe57fc	147	if (fttmr010->is_aspeed) {
4451d3f5 TR	148	/*
	149	* ASPEED Timer Controller will load TIMER1_LOAD register
	150	* into TIMER1_COUNT register when the timer is re-enabled.
	151	*/
	152	writel(cycles, fttmr010->base + TIMER1_LOAD);
	153	} else {
	154	/* Setup the match register forward in time */
	155	cr = readl(fttmr010->base + TIMER1_COUNT);
	156	writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
	157	}
ec14ba1e LW	158
	159	/* Start */
	160	cr = readl(fttmr010->base + TIMER_CR);
	161	cr \|= fttmr010->t1_enable_val;
	162	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	163
	164	return 0;
	165	}
	166
f5bf0ee4	167	static int fttmr010_timer_shutdown(struct clock_event_device *evt)
4750535b	168	{
e7bad212 LW	169	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	170	u32 cr;
	171
ec14ba1e	172	/* Stop */
e7bad212	173	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	174	cr &= ~fttmr010->t1_enable_val;
e7bad212 LW	175	writel(cr, fttmr010->base + TIMER_CR);
	176
	177	return 0;
	178	}
	179
	180	static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
	181	{
	182	struct fttmr010 *fttmr010 = to_fttmr010(evt);
4750535b LW	183	u32 cr;
4750535b LW	184
ec14ba1e	185	/* Stop */
e7bad212	186	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	187	cr &= ~fttmr010->t1_enable_val;
e7bad212	188	writel(cr, fttmr010->base + TIMER_CR);
4750535b	189
ec14ba1e	190	/* Setup counter start from 0 or ~0 */
e7bad212	191	writel(0, fttmr010->base + TIMER1_COUNT);
86fe57fc	192	if (fttmr010->is_aspeed) {
ec14ba1e	193	writel(~0, fttmr010->base + TIMER1_LOAD);
86fe57fc	194	} else {
ec14ba1e	195	writel(0, fttmr010->base + TIMER1_LOAD);
4750535b	196
86fe57fc TR	197	/* Enable interrupt */
	198	cr = readl(fttmr010->base + TIMER_INTR_MASK);
	199	cr &= ~(TIMER_1_INT_OVERFLOW \| TIMER_1_INT_MATCH2);
	200	cr \|= TIMER_1_INT_MATCH1;
	201	writel(cr, fttmr010->base + TIMER_INTR_MASK);
	202	}
4750535b	203
4750535b LW	204	return 0;
	205	}
	206
f5bf0ee4	207	static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
4750535b	208	{
e7bad212 LW	209	struct fttmr010 *fttmr010 = to_fttmr010(evt);
e7bad212 LW	210	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
4750535b LW	211	u32 cr;
4750535b LW	212
ec14ba1e	213	/* Stop */
e7bad212	214	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	215	cr &= ~fttmr010->t1_enable_val;
e7bad212	216	writel(cr, fttmr010->base + TIMER_CR);
4750535b	217
ec14ba1e	218	/* Setup timer to fire at 1/HZ intervals. */
86fe57fc	219	if (fttmr010->is_aspeed) {
ec14ba1e	220	writel(period, fttmr010->base + TIMER1_LOAD);
ec14ba1e LW	221	} else {
	222	cr = 0xffffffff - (period - 1);
	223	writel(cr, fttmr010->base + TIMER1_COUNT);
	224	writel(cr, fttmr010->base + TIMER1_LOAD);
	225
	226	/* Enable interrupt on overflow */
	227	cr = readl(fttmr010->base + TIMER_INTR_MASK);
	228	cr &= ~(TIMER_1_INT_MATCH1 \| TIMER_1_INT_MATCH2);
	229	cr \|= TIMER_1_INT_OVERFLOW;
	230	writel(cr, fttmr010->base + TIMER_INTR_MASK);
	231	}
4750535b LW	232
4750535b LW	233	/* Start the timer */
e7bad212	234	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	235	cr \|= fttmr010->t1_enable_val;
e7bad212	236	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	237
	238	return 0;
	239	}
	240
4750535b LW	241	/*
	242	* IRQ handler for the timer
	243	*/
f5bf0ee4	244	static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
4750535b	245	{
e7bad212	246	struct clock_event_device *evt = dev_id;
4750535b LW	247
	248	evt->event_handler(evt);
	249	return IRQ_HANDLED;
	250	}
	251
ef89718a	252	static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
4750535b	253	{
e7bad212	254	struct fttmr010 *fttmr010;
4750535b	255	int irq;
dd98442e LW	256	struct clk *clk;
dd98442e LW	257	int ret;
ec14ba1e	258	u32 val;
dd98442e LW	259
	260	/*
	261	* These implementations require a clock reference.
	262	* FIXME: we currently only support clocking using PCLK
	263	* and using EXTCLK is not supported in the driver.
	264	*/
	265	clk = of_clk_get_by_name(np, "PCLK");
	266	if (IS_ERR(clk)) {
	267	pr_err("could not get PCLK\n");
	268	return PTR_ERR(clk);
	269	}
	270	ret = clk_prepare_enable(clk);
	271	if (ret) {
	272	pr_err("failed to enable PCLK\n");
	273	return ret;
	274	}
4750535b	275
e7bad212 LW	276	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
	277	if (!fttmr010) {
	278	ret = -ENOMEM;
	279	goto out_disable_clock;
	280	}
	281	fttmr010->tick_rate = clk_get_rate(clk);
	282
	283	fttmr010->base = of_iomap(np, 0);
	284	if (!fttmr010->base) {
1893428b	285	pr_err("Can't remap registers\n");
e7bad212 LW	286	ret = -ENXIO;
e7bad212 LW	287	goto out_free;
4750535b LW	288	}
	289	/* IRQ for timer 1 */
	290	irq = irq_of_parse_and_map(np, 0);
	291	if (irq <= 0) {
1893428b	292	pr_err("Can't parse IRQ\n");
e7bad212 LW	293	ret = -EINVAL;
e7bad212 LW	294	goto out_unmap;
4750535b LW	295	}
4750535b LW	296
ec14ba1e	297	/*
86fe57fc	298	* The Aspeed timers move bits around in the control register.
ec14ba1e	299	*/
ef89718a	300	if (is_aspeed) {
ec14ba1e LW	301	fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE \|
ec14ba1e LW	302	TIMER_1_CR_ASPEED_INT;
86fe57fc	303	fttmr010->is_aspeed = true;
ec14ba1e LW	304	} else {
ec14ba1e LW	305	fttmr010->t1_enable_val = TIMER_1_CR_ENABLE \| TIMER_1_CR_INT;
ec14ba1e	306
86fe57fc TR	307	/*
	308	* Reset the interrupt mask and status
	309	*/
	310	writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
	311	writel(0, fttmr010->base + TIMER_INTR_STATE);
	312	}
ec14ba1e LW	313
	314	/*
	315	* Enable timer 1 count up, timer 2 count up, except on Aspeed,
	316	* where everything just counts down.
	317	*/
ef89718a	318	if (is_aspeed)
ec14ba1e LW	319	val = TIMER_2_CR_ASPEED_ENABLE;
ec14ba1e LW	320	else {
86fe57fc TR	321	val = TIMER_2_CR_ENABLE \| TIMER_1_CR_UPDOWN \|
86fe57fc TR	322	TIMER_2_CR_UPDOWN;
ec14ba1e LW	323	}
ec14ba1e LW	324	writel(val, fttmr010->base + TIMER_CR);
4750535b LW	325
	326	/*
	327	* Setup free-running clocksource timer (interrupts
	328	* disabled.)
	329	*/
e7bad212	330	local_fttmr = fttmr010;
b589da8b	331	writel(0, fttmr010->base + TIMER2_COUNT);
b589da8b LW	332	writel(0, fttmr010->base + TIMER2_MATCH1);
b589da8b LW	333	writel(0, fttmr010->base + TIMER2_MATCH2);
ec14ba1e	334
86fe57fc	335	if (fttmr010->is_aspeed) {
ec14ba1e LW	336	writel(~0, fttmr010->base + TIMER2_LOAD);
	337	clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
	338	"FTTMR010-TIMER2",
	339	fttmr010->tick_rate,
	340	300, 32, clocksource_mmio_readl_down);
740e237a LW	341	sched_clock_register(fttmr010_read_sched_clock_down, 32,
740e237a LW	342	fttmr010->tick_rate);
ec14ba1e LW	343	} else {
	344	writel(0, fttmr010->base + TIMER2_LOAD);
	345	clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
	346	"FTTMR010-TIMER2",
	347	fttmr010->tick_rate,
	348	300, 32, clocksource_mmio_readl_up);
740e237a LW	349	sched_clock_register(fttmr010_read_sched_clock_up, 32,
740e237a LW	350	fttmr010->tick_rate);
ec14ba1e	351	}
4750535b LW	352
4750535b LW	353	/*
e7bad212	354	* Setup clockevent timer (interrupt-driven) on timer 1.
4750535b	355	*/
e7bad212 LW	356	writel(0, fttmr010->base + TIMER1_COUNT);
	357	writel(0, fttmr010->base + TIMER1_LOAD);
	358	writel(0, fttmr010->base + TIMER1_MATCH1);
	359	writel(0, fttmr010->base + TIMER1_MATCH2);
	360	ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
	361	"FTTMR010-TIMER1", &fttmr010->clkevt);
	362	if (ret) {
	363	pr_err("FTTMR010-TIMER1 no IRQ\n");
	364	goto out_unmap;
	365	}
	366
	367	fttmr010->clkevt.name = "FTTMR010-TIMER1";
	368	/* Reasonably fast and accurate clock event */
	369	fttmr010->clkevt.rating = 300;
	370	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC \|
	371	CLOCK_EVT_FEAT_ONESHOT;
	372	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
	373	fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
	374	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
	375	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
	376	fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
	377	fttmr010->clkevt.cpumask = cpumask_of(0);
	378	fttmr010->clkevt.irq = irq;
	379	clockevents_config_and_register(&fttmr010->clkevt,
	380	fttmr010->tick_rate,
4750535b LW	381	1, 0xffffffff);
4750535b LW	382
385c98fc LW	383	#ifdef CONFIG_ARM
385c98fc LW	384	/* Also use this timer for delays */
86fe57fc	385	if (fttmr010->is_aspeed)
385c98fc LW	386	fttmr010->delay_timer.read_current_timer =
	387	fttmr010_read_current_timer_down;
	388	else
	389	fttmr010->delay_timer.read_current_timer =
	390	fttmr010_read_current_timer_up;
	391	fttmr010->delay_timer.freq = fttmr010->tick_rate;
	392	register_current_timer_delay(&fttmr010->delay_timer);
	393	#endif
	394
4750535b	395	return 0;
e7bad212 LW	396
	397	out_unmap:
	398	iounmap(fttmr010->base);
	399	out_free:
	400	kfree(fttmr010);
	401	out_disable_clock:
	402	clk_disable_unprepare(clk);
	403
	404	return ret;
4750535b	405	}
ef89718a DL	406
	407	static __init int aspeed_timer_init(struct device_node *np)
	408	{
	409	return fttmr010_common_init(np, true);
	410	}
	411
	412	static __init int fttmr010_timer_init(struct device_node *np)
	413	{
	414	return fttmr010_common_init(np, false);
	415	}
	416
17273395 DL	417	TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
	418	TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
	419	TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
	420	TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
	421	TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);