[linux-2.6-block.git] / drivers / clocksource / timer-fttmr010.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Faraday Technology FTTMR010 timer driver
 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
 *
 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
 * Copyright (C) 2001-2006 Storlink, Corp.
 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 */
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/delay.h>

/*
 * Register definitions common for all the timer variants.
 */
#define TIMER1_COUNT		(0x00)
#define TIMER1_LOAD		(0x04)
#define TIMER1_MATCH1		(0x08)
#define TIMER1_MATCH2		(0x0c)
#define TIMER2_COUNT		(0x10)
#define TIMER2_LOAD		(0x14)
#define TIMER2_MATCH1		(0x18)
#define TIMER2_MATCH2		(0x1c)
#define TIMER3_COUNT		(0x20)
#define TIMER3_LOAD		(0x24)
#define TIMER3_MATCH1		(0x28)
#define TIMER3_MATCH2		(0x2c)
#define TIMER_CR		(0x30)

/*
 * Control register set to clear for ast2600 only.
 */
#define AST2600_TIMER_CR_CLR	(0x3c)

/*
 * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
 */
#define TIMER_1_CR_ENABLE	BIT(0)
#define TIMER_1_CR_CLOCK	BIT(1)
#define TIMER_1_CR_INT		BIT(2)
#define TIMER_2_CR_ENABLE	BIT(3)
#define TIMER_2_CR_CLOCK	BIT(4)
#define TIMER_2_CR_INT		BIT(5)
#define TIMER_3_CR_ENABLE	BIT(6)
#define TIMER_3_CR_CLOCK	BIT(7)
#define TIMER_3_CR_INT		BIT(8)
#define TIMER_1_CR_UPDOWN	BIT(9)
#define TIMER_2_CR_UPDOWN	BIT(10)
#define TIMER_3_CR_UPDOWN	BIT(11)

/*
 * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
 * The aspeed timers move bits around in the control register and lacks
 * bits for setting the timer to count upwards.
 */
#define TIMER_1_CR_ASPEED_ENABLE	BIT(0)
#define TIMER_1_CR_ASPEED_CLOCK		BIT(1)
#define TIMER_1_CR_ASPEED_INT		BIT(2)
#define TIMER_2_CR_ASPEED_ENABLE	BIT(4)
#define TIMER_2_CR_ASPEED_CLOCK		BIT(5)
#define TIMER_2_CR_ASPEED_INT		BIT(6)
#define TIMER_3_CR_ASPEED_ENABLE	BIT(8)
#define TIMER_3_CR_ASPEED_CLOCK		BIT(9)
#define TIMER_3_CR_ASPEED_INT		BIT(10)

/*
 * Interrupt status/mask register definitions for fttmr010/gemini/moxart
 * timers.
 * The registers don't exist and they are not needed on aspeed timers
 * because:
 *   - aspeed timer overflow interrupt is controlled by bits in Control
 *     Register (TMC30).
 *   - aspeed timers always generate interrupt when either one of the
 *     Match registers equals to Status register.
 */
#define TIMER_INTR_STATE	(0x34)
#define TIMER_INTR_MASK		(0x38)
#define TIMER_1_INT_MATCH1	BIT(0)
#define TIMER_1_INT_MATCH2	BIT(1)
#define TIMER_1_INT_OVERFLOW	BIT(2)
#define TIMER_2_INT_MATCH1	BIT(3)
#define TIMER_2_INT_MATCH2	BIT(4)
#define TIMER_2_INT_OVERFLOW	BIT(5)
#define TIMER_3_INT_MATCH1	BIT(6)
#define TIMER_3_INT_MATCH2	BIT(7)
#define TIMER_3_INT_OVERFLOW	BIT(8)
#define TIMER_INT_ALL_MASK	0x1ff

struct fttmr010 {
	void __iomem *base;
	unsigned int tick_rate;
	bool is_aspeed;
	u32 t1_enable_val;
	struct clock_event_device clkevt;
	int (*timer_shutdown)(struct clock_event_device *evt);
#ifdef CONFIG_ARM
	struct delay_timer delay_timer;
#endif
};

/*
 * A local singleton used by sched_clock and delay timer reads, which are
 * fast and stateless
 */
static struct fttmr010 *local_fttmr;

static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
{
	return container_of(evt, struct fttmr010, clkevt);
}

static unsigned long fttmr010_read_current_timer_up(void)
{
	return readl(local_fttmr->base + TIMER2_COUNT);
}

static unsigned long fttmr010_read_current_timer_down(void)
{
	return ~readl(local_fttmr->base + TIMER2_COUNT);
}

static u64 notrace fttmr010_read_sched_clock_up(void)
{
	return fttmr010_read_current_timer_up();
}

static u64 notrace fttmr010_read_sched_clock_down(void)
{
	return fttmr010_read_current_timer_down();
}

static int fttmr010_timer_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	fttmr010->timer_shutdown(evt);

	if (fttmr010->is_aspeed) {
		/*
		 * ASPEED Timer Controller will load TIMER1_LOAD register
		 * into TIMER1_COUNT register when the timer is re-enabled.
		 */
		writel(cycles, fttmr010->base + TIMER1_LOAD);
	} else {
		/* Setup the match register forward in time */
		cr = readl(fttmr010->base + TIMER1_COUNT);
		writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
	}

	/* Start */
	cr = readl(fttmr010->base + TIMER_CR);
	cr |= fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

static int ast2600_timer_shutdown(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);

	/* Stop */
	writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR);

	return 0;
}

static int fttmr010_timer_shutdown(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	fttmr010->timer_shutdown(evt);

	/* Setup counter start from 0 or ~0 */
	writel(0, fttmr010->base + TIMER1_COUNT);
	if (fttmr010->is_aspeed) {
		writel(~0, fttmr010->base + TIMER1_LOAD);
	} else {
		writel(0, fttmr010->base + TIMER1_LOAD);

		/* Enable interrupt */
		cr = readl(fttmr010->base + TIMER_INTR_MASK);
		cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
		cr |= TIMER_1_INT_MATCH1;
		writel(cr, fttmr010->base + TIMER_INTR_MASK);
	}

	return 0;
}

static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
	u32 cr;

	/* Stop */
	fttmr010->timer_shutdown(evt);

	/* Setup timer to fire at 1/HZ intervals. */
	if (fttmr010->is_aspeed) {
		writel(period, fttmr010->base + TIMER1_LOAD);
	} else {
		cr = 0xffffffff - (period - 1);
		writel(cr, fttmr010->base + TIMER1_COUNT);
		writel(cr, fttmr010->base + TIMER1_LOAD);

		/* Enable interrupt on overflow */
		cr = readl(fttmr010->base + TIMER_INTR_MASK);
		cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
		cr |= TIMER_1_INT_OVERFLOW;
		writel(cr, fttmr010->base + TIMER_INTR_MASK);
	}

	/* Start the timer */
	cr = readl(fttmr010->base + TIMER_CR);
	cr |= fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static irqreturn_t ast2600_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	struct fttmr010 *fttmr010 = to_fttmr010(evt);

	writel(0x1, fttmr010->base + TIMER_INTR_STATE);

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int __init fttmr010_common_init(struct device_node *np,
		bool is_aspeed,
		int (*timer_shutdown)(struct clock_event_device *),
		irq_handler_t irq_handler)
{
	struct fttmr010 *fttmr010;
	int irq;
	struct clk *clk;
	int ret;
	u32 val;

	/*
	 * These implementations require a clock reference.
	 * FIXME: we currently only support clocking using PCLK
	 * and using EXTCLK is not supported in the driver.
	 */
	clk = of_clk_get_by_name(np, "PCLK");
	if (IS_ERR(clk)) {
		pr_err("could not get PCLK\n");
		return PTR_ERR(clk);
	}
	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("failed to enable PCLK\n");
		return ret;
	}

	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
	if (!fttmr010) {
		ret = -ENOMEM;
		goto out_disable_clock;
	}
	fttmr010->tick_rate = clk_get_rate(clk);

	fttmr010->base = of_iomap(np, 0);
	if (!fttmr010->base) {
		pr_err("Can't remap registers\n");
		ret = -ENXIO;
		goto out_free;
	}
	/* IRQ for timer 1 */
	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0) {
		pr_err("Can't parse IRQ\n");
		ret = -EINVAL;
		goto out_unmap;
	}

	/*
	 * The Aspeed timers move bits around in the control register.
	 */
	if (is_aspeed) {
		fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
			TIMER_1_CR_ASPEED_INT;
		fttmr010->is_aspeed = true;
	} else {
		fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;

		/*
		 * Reset the interrupt mask and status
		 */
		writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
		writel(0, fttmr010->base + TIMER_INTR_STATE);
	}

	/*
	 * Enable timer 1 count up, timer 2 count up, except on Aspeed,
	 * where everything just counts down.
	 */
	if (is_aspeed)
		val = TIMER_2_CR_ASPEED_ENABLE;
	else {
		val = TIMER_2_CR_ENABLE | TIMER_1_CR_UPDOWN |
			TIMER_2_CR_UPDOWN;
	}
	writel(val, fttmr010->base + TIMER_CR);

	/*
	 * Setup free-running clocksource timer (interrupts
	 * disabled.)
	 */
	local_fttmr = fttmr010;
	writel(0, fttmr010->base + TIMER2_COUNT);
	writel(0, fttmr010->base + TIMER2_MATCH1);
	writel(0, fttmr010->base + TIMER2_MATCH2);

	if (fttmr010->is_aspeed) {
		writel(~0, fttmr010->base + TIMER2_LOAD);
		clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
				      "FTTMR010-TIMER2",
				      fttmr010->tick_rate,
				      300, 32, clocksource_mmio_readl_down);
		sched_clock_register(fttmr010_read_sched_clock_down, 32,
				     fttmr010->tick_rate);
	} else {
		writel(0, fttmr010->base + TIMER2_LOAD);
		clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
				      "FTTMR010-TIMER2",
				      fttmr010->tick_rate,
				      300, 32, clocksource_mmio_readl_up);
		sched_clock_register(fttmr010_read_sched_clock_up, 32,
				     fttmr010->tick_rate);
	}

	fttmr010->timer_shutdown = timer_shutdown;

	/*
	 * Setup clockevent timer (interrupt-driven) on timer 1.
	 */
	writel(0, fttmr010->base + TIMER1_COUNT);
	writel(0, fttmr010->base + TIMER1_LOAD);
	writel(0, fttmr010->base + TIMER1_MATCH1);
	writel(0, fttmr010->base + TIMER1_MATCH2);
	ret = request_irq(irq, irq_handler, IRQF_TIMER,
			  "FTTMR010-TIMER1", &fttmr010->clkevt);
	if (ret) {
		pr_err("FTTMR010-TIMER1 no IRQ\n");
		goto out_unmap;
	}

	fttmr010->clkevt.name = "FTTMR010-TIMER1";
	/* Reasonably fast and accurate clock event */
	fttmr010->clkevt.rating = 300;
	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
		CLOCK_EVT_FEAT_ONESHOT;
	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
	fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown;
	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
	fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown;
	fttmr010->clkevt.cpumask = cpumask_of(0);
	fttmr010->clkevt.irq = irq;
	clockevents_config_and_register(&fttmr010->clkevt,
					fttmr010->tick_rate,
					1, 0xffffffff);

#ifdef CONFIG_ARM
	/* Also use this timer for delays */
	if (fttmr010->is_aspeed)
		fttmr010->delay_timer.read_current_timer =
			fttmr010_read_current_timer_down;
	else
		fttmr010->delay_timer.read_current_timer =
			fttmr010_read_current_timer_up;
	fttmr010->delay_timer.freq = fttmr010->tick_rate;
	register_current_timer_delay(&fttmr010->delay_timer);
#endif

	return 0;

out_unmap:
	iounmap(fttmr010->base);
out_free:
	kfree(fttmr010);
out_disable_clock:
	clk_disable_unprepare(clk);

	return ret;
}

static __init int ast2600_timer_init(struct device_node *np)
{
	return fttmr010_common_init(np, true,
			ast2600_timer_shutdown,
			ast2600_timer_interrupt);
}

static __init int aspeed_timer_init(struct device_node *np)
{
	return fttmr010_common_init(np, true,
			fttmr010_timer_shutdown,
			fttmr010_timer_interrupt);
}

static __init int fttmr010_timer_init(struct device_node *np)
{
	return fttmr010_common_init(np, false,
			fttmr010_timer_shutdown,
			fttmr010_timer_interrupt);
}

TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
TIMER_OF_DECLARE(ast2600, "aspeed,ast2600-timer", ast2600_timer_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
4750535b	2	/*
f5bf0ee4	3	* Faraday Technology FTTMR010 timer driver
4750535b LW	4	* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
	5	*
	6	* Based on a rewrite of arch/arm/mach-gemini/timer.c:
	7	* Copyright (C) 2001-2006 Storlink, Corp.
	8	* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
	9	*/
	10	#include <linux/interrupt.h>
	11	#include <linux/io.h>
	12	#include <linux/of.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
4750535b LW	15	#include <linux/clockchips.h>
	16	#include <linux/clocksource.h>
	17	#include <linux/sched_clock.h>
28e71e2f	18	#include <linux/clk.h>
e7bad212	19	#include <linux/slab.h>
d0d76d57	20	#include <linux/bitops.h>
385c98fc	21	#include <linux/delay.h>
4750535b LW	22
4750535b LW	23	/*
86fe57fc	24	* Register definitions common for all the timer variants.
4750535b LW	25	*/
	26	#define TIMER1_COUNT (0x00)
	27	#define TIMER1_LOAD (0x04)
	28	#define TIMER1_MATCH1 (0x08)
	29	#define TIMER1_MATCH2 (0x0c)
	30	#define TIMER2_COUNT (0x10)
	31	#define TIMER2_LOAD (0x14)
	32	#define TIMER2_MATCH1 (0x18)
	33	#define TIMER2_MATCH2 (0x1c)
	34	#define TIMER3_COUNT (0x20)
	35	#define TIMER3_LOAD (0x24)
	36	#define TIMER3_MATCH1 (0x28)
	37	#define TIMER3_MATCH2 (0x2c)
	38	#define TIMER_CR (0x30)
4750535b	39
5422413c JS	40	/*
	41	* Control register set to clear for ast2600 only.
	42	*/
	43	#define AST2600_TIMER_CR_CLR (0x3c)
	44
86fe57fc TR	45	/*
	46	* Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
	47	*/
d0d76d57 LW	48	#define TIMER_1_CR_ENABLE BIT(0)
	49	#define TIMER_1_CR_CLOCK BIT(1)
	50	#define TIMER_1_CR_INT BIT(2)
	51	#define TIMER_2_CR_ENABLE BIT(3)
	52	#define TIMER_2_CR_CLOCK BIT(4)
	53	#define TIMER_2_CR_INT BIT(5)
	54	#define TIMER_3_CR_ENABLE BIT(6)
	55	#define TIMER_3_CR_CLOCK BIT(7)
	56	#define TIMER_3_CR_INT BIT(8)
	57	#define TIMER_1_CR_UPDOWN BIT(9)
	58	#define TIMER_2_CR_UPDOWN BIT(10)
	59	#define TIMER_3_CR_UPDOWN BIT(11)
4750535b	60
ec14ba1e	61	/*
86fe57fc TR	62	* Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
	63	* The aspeed timers move bits around in the control register and lacks
	64	* bits for setting the timer to count upwards.
ec14ba1e LW	65	*/
	66	#define TIMER_1_CR_ASPEED_ENABLE BIT(0)
	67	#define TIMER_1_CR_ASPEED_CLOCK BIT(1)
	68	#define TIMER_1_CR_ASPEED_INT BIT(2)
	69	#define TIMER_2_CR_ASPEED_ENABLE BIT(4)
	70	#define TIMER_2_CR_ASPEED_CLOCK BIT(5)
	71	#define TIMER_2_CR_ASPEED_INT BIT(6)
	72	#define TIMER_3_CR_ASPEED_ENABLE BIT(8)
	73	#define TIMER_3_CR_ASPEED_CLOCK BIT(9)
	74	#define TIMER_3_CR_ASPEED_INT BIT(10)
	75
86fe57fc TR	76	/*
	77	* Interrupt status/mask register definitions for fttmr010/gemini/moxart
	78	* timers.
	79	* The registers don't exist and they are not needed on aspeed timers
	80	* because:
	81	* - aspeed timer overflow interrupt is controlled by bits in Control
	82	* Register (TMC30).
	83	* - aspeed timers always generate interrupt when either one of the
	84	* Match registers equals to Status register.
	85	*/
	86	#define TIMER_INTR_STATE (0x34)
	87	#define TIMER_INTR_MASK (0x38)
d0d76d57 LW	88	#define TIMER_1_INT_MATCH1 BIT(0)
	89	#define TIMER_1_INT_MATCH2 BIT(1)
	90	#define TIMER_1_INT_OVERFLOW BIT(2)
	91	#define TIMER_2_INT_MATCH1 BIT(3)
	92	#define TIMER_2_INT_MATCH2 BIT(4)
	93	#define TIMER_2_INT_OVERFLOW BIT(5)
	94	#define TIMER_3_INT_MATCH1 BIT(6)
	95	#define TIMER_3_INT_MATCH2 BIT(7)
	96	#define TIMER_3_INT_OVERFLOW BIT(8)
4750535b LW	97	#define TIMER_INT_ALL_MASK 0x1ff
4750535b LW	98
e7bad212 LW	99	struct fttmr010 {
	100	void __iomem *base;
	101	unsigned int tick_rate;
86fe57fc	102	bool is_aspeed;
ec14ba1e	103	u32 t1_enable_val;
e7bad212	104	struct clock_event_device clkevt;
84fb64c2	105	int (timer_shutdown)(struct clock_event_device evt);
385c98fc LW	106	#ifdef CONFIG_ARM
	107	struct delay_timer delay_timer;
	108	#endif
e7bad212 LW	109	};
e7bad212 LW	110
385c98fc LW	111	/*
	112	* A local singleton used by sched_clock and delay timer reads, which are
	113	* fast and stateless
	114	*/
e7bad212 LW	115	static struct fttmr010 *local_fttmr;
	116
	117	static inline struct fttmr010 to_fttmr010(struct clock_event_device evt)
	118	{
	119	return container_of(evt, struct fttmr010, clkevt);
	120	}
4750535b	121
c4779902	122	static unsigned long fttmr010_read_current_timer_up(void)
4750535b	123	{
b589da8b	124	return readl(local_fttmr->base + TIMER2_COUNT);
4750535b LW	125	}
4750535b LW	126
c4779902	127	static unsigned long fttmr010_read_current_timer_down(void)
740e237a LW	128	{
	129	return ~readl(local_fttmr->base + TIMER2_COUNT);
	130	}
	131
c4779902	132	static u64 notrace fttmr010_read_sched_clock_up(void)
385c98fc	133	{
c4779902	134	return fttmr010_read_current_timer_up();
385c98fc LW	135	}
385c98fc LW	136
c4779902	137	static u64 notrace fttmr010_read_sched_clock_down(void)
385c98fc	138	{
c4779902	139	return fttmr010_read_current_timer_down();
385c98fc LW	140	}
385c98fc LW	141
f5bf0ee4	142	static int fttmr010_timer_set_next_event(unsigned long cycles,
4750535b LW	143	struct clock_event_device *evt)
4750535b LW	144	{
e7bad212	145	struct fttmr010 *fttmr010 = to_fttmr010(evt);
4750535b LW	146	u32 cr;
4750535b LW	147
ec14ba1e	148	/* Stop */
84fb64c2	149	fttmr010->timer_shutdown(evt);
ec14ba1e	150
86fe57fc	151	if (fttmr010->is_aspeed) {
4451d3f5 TR	152	/*
	153	* ASPEED Timer Controller will load TIMER1_LOAD register
	154	* into TIMER1_COUNT register when the timer is re-enabled.
	155	*/
	156	writel(cycles, fttmr010->base + TIMER1_LOAD);
	157	} else {
	158	/* Setup the match register forward in time */
	159	cr = readl(fttmr010->base + TIMER1_COUNT);
	160	writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
	161	}
ec14ba1e LW	162
	163	/* Start */
	164	cr = readl(fttmr010->base + TIMER_CR);
	165	cr \|= fttmr010->t1_enable_val;
	166	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	167
	168	return 0;
	169	}
	170
5422413c JS	171	static int ast2600_timer_shutdown(struct clock_event_device *evt)
	172	{
	173	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	174
	175	/* Stop */
	176	writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR);
	177
	178	return 0;
	179	}
	180
f5bf0ee4	181	static int fttmr010_timer_shutdown(struct clock_event_device *evt)
4750535b	182	{
e7bad212 LW	183	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	184	u32 cr;
	185
ec14ba1e	186	/* Stop */
e7bad212	187	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	188	cr &= ~fttmr010->t1_enable_val;
e7bad212 LW	189	writel(cr, fttmr010->base + TIMER_CR);
	190
	191	return 0;
	192	}
	193
	194	static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
	195	{
	196	struct fttmr010 *fttmr010 = to_fttmr010(evt);
4750535b LW	197	u32 cr;
4750535b LW	198
ec14ba1e	199	/* Stop */
84fb64c2	200	fttmr010->timer_shutdown(evt);
4750535b	201
ec14ba1e	202	/* Setup counter start from 0 or ~0 */
e7bad212	203	writel(0, fttmr010->base + TIMER1_COUNT);
86fe57fc	204	if (fttmr010->is_aspeed) {
ec14ba1e	205	writel(~0, fttmr010->base + TIMER1_LOAD);
86fe57fc	206	} else {
ec14ba1e	207	writel(0, fttmr010->base + TIMER1_LOAD);
4750535b	208
86fe57fc TR	209	/* Enable interrupt */
	210	cr = readl(fttmr010->base + TIMER_INTR_MASK);
	211	cr &= ~(TIMER_1_INT_OVERFLOW \| TIMER_1_INT_MATCH2);
	212	cr \|= TIMER_1_INT_MATCH1;
	213	writel(cr, fttmr010->base + TIMER_INTR_MASK);
	214	}
4750535b	215
4750535b LW	216	return 0;
	217	}
	218
f5bf0ee4	219	static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
4750535b	220	{
e7bad212 LW	221	struct fttmr010 *fttmr010 = to_fttmr010(evt);
e7bad212 LW	222	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
4750535b LW	223	u32 cr;
4750535b LW	224
ec14ba1e	225	/* Stop */
84fb64c2	226	fttmr010->timer_shutdown(evt);
4750535b	227
ec14ba1e	228	/* Setup timer to fire at 1/HZ intervals. */
86fe57fc	229	if (fttmr010->is_aspeed) {
ec14ba1e	230	writel(period, fttmr010->base + TIMER1_LOAD);
ec14ba1e LW	231	} else {
	232	cr = 0xffffffff - (period - 1);
	233	writel(cr, fttmr010->base + TIMER1_COUNT);
	234	writel(cr, fttmr010->base + TIMER1_LOAD);
	235
	236	/* Enable interrupt on overflow */
	237	cr = readl(fttmr010->base + TIMER_INTR_MASK);
	238	cr &= ~(TIMER_1_INT_MATCH1 \| TIMER_1_INT_MATCH2);
	239	cr \|= TIMER_1_INT_OVERFLOW;
	240	writel(cr, fttmr010->base + TIMER_INTR_MASK);
	241	}
4750535b LW	242
4750535b LW	243	/* Start the timer */
e7bad212	244	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	245	cr \|= fttmr010->t1_enable_val;
e7bad212	246	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	247
	248	return 0;
	249	}
	250
4750535b LW	251	/*
	252	* IRQ handler for the timer
	253	*/
f5bf0ee4	254	static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
4750535b	255	{
e7bad212	256	struct clock_event_device *evt = dev_id;
4750535b LW	257
	258	evt->event_handler(evt);
	259	return IRQ_HANDLED;
	260	}
	261
5422413c JS	262	static irqreturn_t ast2600_timer_interrupt(int irq, void *dev_id)
	263	{
	264	struct clock_event_device *evt = dev_id;
	265	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	266
	267	writel(0x1, fttmr010->base + TIMER_INTR_STATE);
	268
	269	evt->event_handler(evt);
	270	return IRQ_HANDLED;
	271	}
	272
	273	static int __init fttmr010_common_init(struct device_node *np,
	274	bool is_aspeed,
	275	int (timer_shutdown)(struct clock_event_device ),
	276	irq_handler_t irq_handler)
4750535b	277	{
e7bad212	278	struct fttmr010 *fttmr010;
4750535b	279	int irq;
dd98442e LW	280	struct clk *clk;
dd98442e LW	281	int ret;
ec14ba1e	282	u32 val;
dd98442e LW	283
	284	/*
	285	* These implementations require a clock reference.
	286	* FIXME: we currently only support clocking using PCLK
	287	* and using EXTCLK is not supported in the driver.
	288	*/
	289	clk = of_clk_get_by_name(np, "PCLK");
	290	if (IS_ERR(clk)) {
	291	pr_err("could not get PCLK\n");
	292	return PTR_ERR(clk);
	293	}
	294	ret = clk_prepare_enable(clk);
	295	if (ret) {
	296	pr_err("failed to enable PCLK\n");
	297	return ret;
	298	}
4750535b	299
e7bad212 LW	300	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
	301	if (!fttmr010) {
	302	ret = -ENOMEM;
	303	goto out_disable_clock;
	304	}
	305	fttmr010->tick_rate = clk_get_rate(clk);
	306
	307	fttmr010->base = of_iomap(np, 0);
	308	if (!fttmr010->base) {
1893428b	309	pr_err("Can't remap registers\n");
e7bad212 LW	310	ret = -ENXIO;
e7bad212 LW	311	goto out_free;
4750535b LW	312	}
	313	/* IRQ for timer 1 */
	314	irq = irq_of_parse_and_map(np, 0);
	315	if (irq <= 0) {
1893428b	316	pr_err("Can't parse IRQ\n");
e7bad212 LW	317	ret = -EINVAL;
e7bad212 LW	318	goto out_unmap;
4750535b LW	319	}
4750535b LW	320
ec14ba1e	321	/*
86fe57fc	322	* The Aspeed timers move bits around in the control register.
ec14ba1e	323	*/
ef89718a	324	if (is_aspeed) {
ec14ba1e LW	325	fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE \|
ec14ba1e LW	326	TIMER_1_CR_ASPEED_INT;
86fe57fc	327	fttmr010->is_aspeed = true;
ec14ba1e LW	328	} else {
ec14ba1e LW	329	fttmr010->t1_enable_val = TIMER_1_CR_ENABLE \| TIMER_1_CR_INT;
ec14ba1e	330
86fe57fc TR	331	/*
	332	* Reset the interrupt mask and status
	333	*/
	334	writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
	335	writel(0, fttmr010->base + TIMER_INTR_STATE);
	336	}
ec14ba1e LW	337
	338	/*
	339	* Enable timer 1 count up, timer 2 count up, except on Aspeed,
	340	* where everything just counts down.
	341	*/
ef89718a	342	if (is_aspeed)
ec14ba1e LW	343	val = TIMER_2_CR_ASPEED_ENABLE;
ec14ba1e LW	344	else {
86fe57fc TR	345	val = TIMER_2_CR_ENABLE \| TIMER_1_CR_UPDOWN \|
86fe57fc TR	346	TIMER_2_CR_UPDOWN;
ec14ba1e LW	347	}
ec14ba1e LW	348	writel(val, fttmr010->base + TIMER_CR);
4750535b LW	349
	350	/*
	351	* Setup free-running clocksource timer (interrupts
	352	* disabled.)
	353	*/
e7bad212	354	local_fttmr = fttmr010;
b589da8b	355	writel(0, fttmr010->base + TIMER2_COUNT);
b589da8b LW	356	writel(0, fttmr010->base + TIMER2_MATCH1);
b589da8b LW	357	writel(0, fttmr010->base + TIMER2_MATCH2);
ec14ba1e	358
86fe57fc	359	if (fttmr010->is_aspeed) {
ec14ba1e LW	360	writel(~0, fttmr010->base + TIMER2_LOAD);
	361	clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
	362	"FTTMR010-TIMER2",
	363	fttmr010->tick_rate,
	364	300, 32, clocksource_mmio_readl_down);
740e237a LW	365	sched_clock_register(fttmr010_read_sched_clock_down, 32,
740e237a LW	366	fttmr010->tick_rate);
ec14ba1e LW	367	} else {
	368	writel(0, fttmr010->base + TIMER2_LOAD);
	369	clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
	370	"FTTMR010-TIMER2",
	371	fttmr010->tick_rate,
	372	300, 32, clocksource_mmio_readl_up);
740e237a LW	373	sched_clock_register(fttmr010_read_sched_clock_up, 32,
740e237a LW	374	fttmr010->tick_rate);
ec14ba1e	375	}
4750535b	376
5422413c	377	fttmr010->timer_shutdown = timer_shutdown;
84fb64c2	378
4750535b	379	/*
e7bad212	380	* Setup clockevent timer (interrupt-driven) on timer 1.
4750535b	381	*/
e7bad212 LW	382	writel(0, fttmr010->base + TIMER1_COUNT);
	383	writel(0, fttmr010->base + TIMER1_LOAD);
	384	writel(0, fttmr010->base + TIMER1_MATCH1);
	385	writel(0, fttmr010->base + TIMER1_MATCH2);
5422413c	386	ret = request_irq(irq, irq_handler, IRQF_TIMER,
e7bad212 LW	387	"FTTMR010-TIMER1", &fttmr010->clkevt);
	388	if (ret) {
	389	pr_err("FTTMR010-TIMER1 no IRQ\n");
	390	goto out_unmap;
	391	}
	392
	393	fttmr010->clkevt.name = "FTTMR010-TIMER1";
	394	/* Reasonably fast and accurate clock event */
	395	fttmr010->clkevt.rating = 300;
	396	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC \|
	397	CLOCK_EVT_FEAT_ONESHOT;
	398	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
84fb64c2	399	fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown;
e7bad212 LW	400	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
e7bad212 LW	401	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
84fb64c2	402	fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown;
e7bad212 LW	403	fttmr010->clkevt.cpumask = cpumask_of(0);
	404	fttmr010->clkevt.irq = irq;
	405	clockevents_config_and_register(&fttmr010->clkevt,
	406	fttmr010->tick_rate,
4750535b LW	407	1, 0xffffffff);
4750535b LW	408
385c98fc LW	409	#ifdef CONFIG_ARM
385c98fc LW	410	/* Also use this timer for delays */
86fe57fc	411	if (fttmr010->is_aspeed)
385c98fc LW	412	fttmr010->delay_timer.read_current_timer =
	413	fttmr010_read_current_timer_down;
	414	else
	415	fttmr010->delay_timer.read_current_timer =
	416	fttmr010_read_current_timer_up;
	417	fttmr010->delay_timer.freq = fttmr010->tick_rate;
	418	register_current_timer_delay(&fttmr010->delay_timer);
	419	#endif
	420
4750535b	421	return 0;
e7bad212 LW	422
	423	out_unmap:
	424	iounmap(fttmr010->base);
	425	out_free:
	426	kfree(fttmr010);
	427	out_disable_clock:
	428	clk_disable_unprepare(clk);
	429
	430	return ret;
4750535b	431	}
ef89718a	432
5422413c JS	433	static __init int ast2600_timer_init(struct device_node *np)
	434	{
	435	return fttmr010_common_init(np, true,
	436	ast2600_timer_shutdown,
	437	ast2600_timer_interrupt);
	438	}
	439
ef89718a DL	440	static __init int aspeed_timer_init(struct device_node *np)
ef89718a DL	441	{
5422413c JS	442	return fttmr010_common_init(np, true,
	443	fttmr010_timer_shutdown,
	444	fttmr010_timer_interrupt);
ef89718a DL	445	}
	446
	447	static __init int fttmr010_timer_init(struct device_node *np)
	448	{
5422413c JS	449	return fttmr010_common_init(np, false,
	450	fttmr010_timer_shutdown,
	451	fttmr010_timer_interrupt);
ef89718a DL	452	}
ef89718a DL	453
17273395 DL	454	TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
	455	TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
	456	TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
	457	TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
	458	TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
5422413c	459	TIMER_OF_DECLARE(ast2600, "aspeed,ast2600-timer", ast2600_timer_init);