[linux-2.6-block.git] / drivers / clocksource / timer-fttmr010.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Faraday Technology FTTMR010 timer driver
 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
 *
 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
 * Copyright (C) 2001-2006 Storlink, Corp.
 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 */
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/delay.h>

/*
 * Register definitions for the timers
 */
#define TIMER1_COUNT		(0x00)
#define TIMER1_LOAD		(0x04)
#define TIMER1_MATCH1		(0x08)
#define TIMER1_MATCH2		(0x0c)
#define TIMER2_COUNT		(0x10)
#define TIMER2_LOAD		(0x14)
#define TIMER2_MATCH1		(0x18)
#define TIMER2_MATCH2		(0x1c)
#define TIMER3_COUNT		(0x20)
#define TIMER3_LOAD		(0x24)
#define TIMER3_MATCH1		(0x28)
#define TIMER3_MATCH2		(0x2c)
#define TIMER_CR		(0x30)
#define TIMER_INTR_STATE	(0x34)
#define TIMER_INTR_MASK		(0x38)

#define TIMER_1_CR_ENABLE	BIT(0)
#define TIMER_1_CR_CLOCK	BIT(1)
#define TIMER_1_CR_INT		BIT(2)
#define TIMER_2_CR_ENABLE	BIT(3)
#define TIMER_2_CR_CLOCK	BIT(4)
#define TIMER_2_CR_INT		BIT(5)
#define TIMER_3_CR_ENABLE	BIT(6)
#define TIMER_3_CR_CLOCK	BIT(7)
#define TIMER_3_CR_INT		BIT(8)
#define TIMER_1_CR_UPDOWN	BIT(9)
#define TIMER_2_CR_UPDOWN	BIT(10)
#define TIMER_3_CR_UPDOWN	BIT(11)

/*
 * The Aspeed AST2400 moves bits around in the control register
 * and lacks bits for setting the timer to count upwards.
 */
#define TIMER_1_CR_ASPEED_ENABLE	BIT(0)
#define TIMER_1_CR_ASPEED_CLOCK		BIT(1)
#define TIMER_1_CR_ASPEED_INT		BIT(2)
#define TIMER_2_CR_ASPEED_ENABLE	BIT(4)
#define TIMER_2_CR_ASPEED_CLOCK		BIT(5)
#define TIMER_2_CR_ASPEED_INT		BIT(6)
#define TIMER_3_CR_ASPEED_ENABLE	BIT(8)
#define TIMER_3_CR_ASPEED_CLOCK		BIT(9)
#define TIMER_3_CR_ASPEED_INT		BIT(10)

#define TIMER_1_INT_MATCH1	BIT(0)
#define TIMER_1_INT_MATCH2	BIT(1)
#define TIMER_1_INT_OVERFLOW	BIT(2)
#define TIMER_2_INT_MATCH1	BIT(3)
#define TIMER_2_INT_MATCH2	BIT(4)
#define TIMER_2_INT_OVERFLOW	BIT(5)
#define TIMER_3_INT_MATCH1	BIT(6)
#define TIMER_3_INT_MATCH2	BIT(7)
#define TIMER_3_INT_OVERFLOW	BIT(8)
#define TIMER_INT_ALL_MASK	0x1ff

struct fttmr010 {
	void __iomem *base;
	unsigned int tick_rate;
	bool count_down;
	u32 t1_enable_val;
	struct clock_event_device clkevt;
#ifdef CONFIG_ARM
	struct delay_timer delay_timer;
#endif
};

/*
 * A local singleton used by sched_clock and delay timer reads, which are
 * fast and stateless
 */
static struct fttmr010 *local_fttmr;

static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
{
	return container_of(evt, struct fttmr010, clkevt);
}

static unsigned long fttmr010_read_current_timer_up(void)
{
	return readl(local_fttmr->base + TIMER2_COUNT);
}

static unsigned long fttmr010_read_current_timer_down(void)
{
	return ~readl(local_fttmr->base + TIMER2_COUNT);
}

static u64 notrace fttmr010_read_sched_clock_up(void)
{
	return fttmr010_read_current_timer_up();
}

static u64 notrace fttmr010_read_sched_clock_down(void)
{
	return fttmr010_read_current_timer_down();
}

static int fttmr010_timer_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	if (fttmr010->count_down) {
		/*
		 * ASPEED Timer Controller will load TIMER1_LOAD register
		 * into TIMER1_COUNT register when the timer is re-enabled.
		 */
		writel(cycles, fttmr010->base + TIMER1_LOAD);
	} else {
		/* Setup the match register forward in time */
		cr = readl(fttmr010->base + TIMER1_COUNT);
		writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
	}

	/* Start */
	cr = readl(fttmr010->base + TIMER_CR);
	cr |= fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

static int fttmr010_timer_shutdown(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	/* Setup counter start from 0 or ~0 */
	writel(0, fttmr010->base + TIMER1_COUNT);
	if (fttmr010->count_down)
		writel(~0, fttmr010->base + TIMER1_LOAD);
	else
		writel(0, fttmr010->base + TIMER1_LOAD);

	/* Enable interrupt */
	cr = readl(fttmr010->base + TIMER_INTR_MASK);
	cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
	cr |= TIMER_1_INT_MATCH1;
	writel(cr, fttmr010->base + TIMER_INTR_MASK);

	return 0;
}

static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
	u32 cr;

	/* Stop */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	/* Setup timer to fire at 1/HZ intervals. */
	if (fttmr010->count_down) {
		writel(period, fttmr010->base + TIMER1_LOAD);
		writel(0, fttmr010->base + TIMER1_MATCH1);
	} else {
		cr = 0xffffffff - (period - 1);
		writel(cr, fttmr010->base + TIMER1_COUNT);
		writel(cr, fttmr010->base + TIMER1_LOAD);

		/* Enable interrupt on overflow */
		cr = readl(fttmr010->base + TIMER_INTR_MASK);
		cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
		cr |= TIMER_1_INT_OVERFLOW;
		writel(cr, fttmr010->base + TIMER_INTR_MASK);
	}

	/* Start the timer */
	cr = readl(fttmr010->base + TIMER_CR);
	cr |= fttmr010->t1_enable_val;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
{
	struct fttmr010 *fttmr010;
	int irq;
	struct clk *clk;
	int ret;
	u32 val;

	/*
	 * These implementations require a clock reference.
	 * FIXME: we currently only support clocking using PCLK
	 * and using EXTCLK is not supported in the driver.
	 */
	clk = of_clk_get_by_name(np, "PCLK");
	if (IS_ERR(clk)) {
		pr_err("could not get PCLK\n");
		return PTR_ERR(clk);
	}
	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("failed to enable PCLK\n");
		return ret;
	}

	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
	if (!fttmr010) {
		ret = -ENOMEM;
		goto out_disable_clock;
	}
	fttmr010->tick_rate = clk_get_rate(clk);

	fttmr010->base = of_iomap(np, 0);
	if (!fttmr010->base) {
		pr_err("Can't remap registers\n");
		ret = -ENXIO;
		goto out_free;
	}
	/* IRQ for timer 1 */
	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0) {
		pr_err("Can't parse IRQ\n");
		ret = -EINVAL;
		goto out_unmap;
	}

	/*
	 * The Aspeed AST2400 moves bits around in the control register,
	 * otherwise it works the same.
	 */
	if (is_aspeed) {
		fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
			TIMER_1_CR_ASPEED_INT;
		/* Downward not available */
		fttmr010->count_down = true;
	} else {
		fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
	}

	/*
	 * Reset the interrupt mask and status
	 */
	writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
	writel(0, fttmr010->base + TIMER_INTR_STATE);

	/*
	 * Enable timer 1 count up, timer 2 count up, except on Aspeed,
	 * where everything just counts down.
	 */
	if (is_aspeed)
		val = TIMER_2_CR_ASPEED_ENABLE;
	else {
		val = TIMER_2_CR_ENABLE;
		if (!fttmr010->count_down)
			val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN;
	}
	writel(val, fttmr010->base + TIMER_CR);

	/*
	 * Setup free-running clocksource timer (interrupts
	 * disabled.)
	 */
	local_fttmr = fttmr010;
	writel(0, fttmr010->base + TIMER2_COUNT);
	writel(0, fttmr010->base + TIMER2_MATCH1);
	writel(0, fttmr010->base + TIMER2_MATCH2);

	if (fttmr010->count_down) {
		writel(~0, fttmr010->base + TIMER2_LOAD);
		clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
				      "FTTMR010-TIMER2",
				      fttmr010->tick_rate,
				      300, 32, clocksource_mmio_readl_down);
		sched_clock_register(fttmr010_read_sched_clock_down, 32,
				     fttmr010->tick_rate);
	} else {
		writel(0, fttmr010->base + TIMER2_LOAD);
		clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
				      "FTTMR010-TIMER2",
				      fttmr010->tick_rate,
				      300, 32, clocksource_mmio_readl_up);
		sched_clock_register(fttmr010_read_sched_clock_up, 32,
				     fttmr010->tick_rate);
	}

	/*
	 * Setup clockevent timer (interrupt-driven) on timer 1.
	 */
	writel(0, fttmr010->base + TIMER1_COUNT);
	writel(0, fttmr010->base + TIMER1_LOAD);
	writel(0, fttmr010->base + TIMER1_MATCH1);
	writel(0, fttmr010->base + TIMER1_MATCH2);
	ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
			  "FTTMR010-TIMER1", &fttmr010->clkevt);
	if (ret) {
		pr_err("FTTMR010-TIMER1 no IRQ\n");
		goto out_unmap;
	}

	fttmr010->clkevt.name = "FTTMR010-TIMER1";
	/* Reasonably fast and accurate clock event */
	fttmr010->clkevt.rating = 300;
	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
		CLOCK_EVT_FEAT_ONESHOT;
	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
	fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
	fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
	fttmr010->clkevt.cpumask = cpumask_of(0);
	fttmr010->clkevt.irq = irq;
	clockevents_config_and_register(&fttmr010->clkevt,
					fttmr010->tick_rate,
					1, 0xffffffff);

#ifdef CONFIG_ARM
	/* Also use this timer for delays */
	if (fttmr010->count_down)
		fttmr010->delay_timer.read_current_timer =
			fttmr010_read_current_timer_down;
	else
		fttmr010->delay_timer.read_current_timer =
			fttmr010_read_current_timer_up;
	fttmr010->delay_timer.freq = fttmr010->tick_rate;
	register_current_timer_delay(&fttmr010->delay_timer);
#endif

	return 0;

out_unmap:
	iounmap(fttmr010->base);
out_free:
	kfree(fttmr010);
out_disable_clock:
	clk_disable_unprepare(clk);

	return ret;
}

static __init int aspeed_timer_init(struct device_node *np)
{
	return fttmr010_common_init(np, true);
}

static __init int fttmr010_timer_init(struct device_node *np)
{
	return fttmr010_common_init(np, false);
}

TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
4750535b	2	/*
f5bf0ee4	3	* Faraday Technology FTTMR010 timer driver
4750535b LW	4	* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
	5	*
	6	* Based on a rewrite of arch/arm/mach-gemini/timer.c:
	7	* Copyright (C) 2001-2006 Storlink, Corp.
	8	* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
	9	*/
	10	#include <linux/interrupt.h>
	11	#include <linux/io.h>
	12	#include <linux/of.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
4750535b LW	15	#include <linux/clockchips.h>
	16	#include <linux/clocksource.h>
	17	#include <linux/sched_clock.h>
28e71e2f	18	#include <linux/clk.h>
e7bad212	19	#include <linux/slab.h>
d0d76d57	20	#include <linux/bitops.h>
385c98fc	21	#include <linux/delay.h>
4750535b LW	22
	23	/*
	24	* Register definitions for the timers
	25	*/
	26	#define TIMER1_COUNT (0x00)
	27	#define TIMER1_LOAD (0x04)
	28	#define TIMER1_MATCH1 (0x08)
	29	#define TIMER1_MATCH2 (0x0c)
	30	#define TIMER2_COUNT (0x10)
	31	#define TIMER2_LOAD (0x14)
	32	#define TIMER2_MATCH1 (0x18)
	33	#define TIMER2_MATCH2 (0x1c)
	34	#define TIMER3_COUNT (0x20)
	35	#define TIMER3_LOAD (0x24)
	36	#define TIMER3_MATCH1 (0x28)
	37	#define TIMER3_MATCH2 (0x2c)
	38	#define TIMER_CR (0x30)
	39	#define TIMER_INTR_STATE (0x34)
	40	#define TIMER_INTR_MASK (0x38)
	41
d0d76d57 LW	42	#define TIMER_1_CR_ENABLE BIT(0)
	43	#define TIMER_1_CR_CLOCK BIT(1)
	44	#define TIMER_1_CR_INT BIT(2)
	45	#define TIMER_2_CR_ENABLE BIT(3)
	46	#define TIMER_2_CR_CLOCK BIT(4)
	47	#define TIMER_2_CR_INT BIT(5)
	48	#define TIMER_3_CR_ENABLE BIT(6)
	49	#define TIMER_3_CR_CLOCK BIT(7)
	50	#define TIMER_3_CR_INT BIT(8)
	51	#define TIMER_1_CR_UPDOWN BIT(9)
	52	#define TIMER_2_CR_UPDOWN BIT(10)
	53	#define TIMER_3_CR_UPDOWN BIT(11)
4750535b	54
ec14ba1e LW	55	/*
	56	* The Aspeed AST2400 moves bits around in the control register
	57	* and lacks bits for setting the timer to count upwards.
	58	*/
	59	#define TIMER_1_CR_ASPEED_ENABLE BIT(0)
	60	#define TIMER_1_CR_ASPEED_CLOCK BIT(1)
	61	#define TIMER_1_CR_ASPEED_INT BIT(2)
	62	#define TIMER_2_CR_ASPEED_ENABLE BIT(4)
	63	#define TIMER_2_CR_ASPEED_CLOCK BIT(5)
	64	#define TIMER_2_CR_ASPEED_INT BIT(6)
	65	#define TIMER_3_CR_ASPEED_ENABLE BIT(8)
	66	#define TIMER_3_CR_ASPEED_CLOCK BIT(9)
	67	#define TIMER_3_CR_ASPEED_INT BIT(10)
	68
d0d76d57 LW	69	#define TIMER_1_INT_MATCH1 BIT(0)
	70	#define TIMER_1_INT_MATCH2 BIT(1)
	71	#define TIMER_1_INT_OVERFLOW BIT(2)
	72	#define TIMER_2_INT_MATCH1 BIT(3)
	73	#define TIMER_2_INT_MATCH2 BIT(4)
	74	#define TIMER_2_INT_OVERFLOW BIT(5)
	75	#define TIMER_3_INT_MATCH1 BIT(6)
	76	#define TIMER_3_INT_MATCH2 BIT(7)
	77	#define TIMER_3_INT_OVERFLOW BIT(8)
4750535b LW	78	#define TIMER_INT_ALL_MASK 0x1ff
4750535b LW	79
e7bad212 LW	80	struct fttmr010 {
	81	void __iomem *base;
	82	unsigned int tick_rate;
ec14ba1e LW	83	bool count_down;
ec14ba1e LW	84	u32 t1_enable_val;
e7bad212	85	struct clock_event_device clkevt;
385c98fc LW	86	#ifdef CONFIG_ARM
	87	struct delay_timer delay_timer;
	88	#endif
e7bad212 LW	89	};
e7bad212 LW	90
385c98fc LW	91	/*
	92	* A local singleton used by sched_clock and delay timer reads, which are
	93	* fast and stateless
	94	*/
e7bad212 LW	95	static struct fttmr010 *local_fttmr;
	96
	97	static inline struct fttmr010 to_fttmr010(struct clock_event_device evt)
	98	{
	99	return container_of(evt, struct fttmr010, clkevt);
	100	}
4750535b	101
c4779902	102	static unsigned long fttmr010_read_current_timer_up(void)
4750535b	103	{
b589da8b	104	return readl(local_fttmr->base + TIMER2_COUNT);
4750535b LW	105	}
4750535b LW	106
c4779902	107	static unsigned long fttmr010_read_current_timer_down(void)
740e237a LW	108	{
	109	return ~readl(local_fttmr->base + TIMER2_COUNT);
	110	}
	111
c4779902	112	static u64 notrace fttmr010_read_sched_clock_up(void)
385c98fc	113	{
c4779902	114	return fttmr010_read_current_timer_up();
385c98fc LW	115	}
385c98fc LW	116
c4779902	117	static u64 notrace fttmr010_read_sched_clock_down(void)
385c98fc	118	{
c4779902	119	return fttmr010_read_current_timer_down();
385c98fc LW	120	}
385c98fc LW	121
f5bf0ee4	122	static int fttmr010_timer_set_next_event(unsigned long cycles,
4750535b LW	123	struct clock_event_device *evt)
4750535b LW	124	{
e7bad212	125	struct fttmr010 *fttmr010 = to_fttmr010(evt);
4750535b LW	126	u32 cr;
4750535b LW	127
ec14ba1e LW	128	/* Stop */
	129	cr = readl(fttmr010->base + TIMER_CR);
	130	cr &= ~fttmr010->t1_enable_val;
	131	writel(cr, fttmr010->base + TIMER_CR);
	132
4451d3f5 TR	133	if (fttmr010->count_down) {
	134	/*
	135	* ASPEED Timer Controller will load TIMER1_LOAD register
	136	* into TIMER1_COUNT register when the timer is re-enabled.
	137	*/
	138	writel(cycles, fttmr010->base + TIMER1_LOAD);
	139	} else {
	140	/* Setup the match register forward in time */
	141	cr = readl(fttmr010->base + TIMER1_COUNT);
	142	writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
	143	}
ec14ba1e LW	144
	145	/* Start */
	146	cr = readl(fttmr010->base + TIMER_CR);
	147	cr \|= fttmr010->t1_enable_val;
	148	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	149
	150	return 0;
	151	}
	152
f5bf0ee4	153	static int fttmr010_timer_shutdown(struct clock_event_device *evt)
4750535b	154	{
e7bad212 LW	155	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	156	u32 cr;
	157
ec14ba1e	158	/* Stop */
e7bad212	159	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	160	cr &= ~fttmr010->t1_enable_val;
e7bad212 LW	161	writel(cr, fttmr010->base + TIMER_CR);
	162
	163	return 0;
	164	}
	165
	166	static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
	167	{
	168	struct fttmr010 *fttmr010 = to_fttmr010(evt);
4750535b LW	169	u32 cr;
4750535b LW	170
ec14ba1e	171	/* Stop */
e7bad212	172	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	173	cr &= ~fttmr010->t1_enable_val;
e7bad212	174	writel(cr, fttmr010->base + TIMER_CR);
4750535b	175
ec14ba1e	176	/* Setup counter start from 0 or ~0 */
e7bad212	177	writel(0, fttmr010->base + TIMER1_COUNT);
ec14ba1e LW	178	if (fttmr010->count_down)
	179	writel(~0, fttmr010->base + TIMER1_LOAD);
	180	else
	181	writel(0, fttmr010->base + TIMER1_LOAD);
4750535b	182
e7bad212 LW	183	/* Enable interrupt */
e7bad212 LW	184	cr = readl(fttmr010->base + TIMER_INTR_MASK);
4750535b LW	185	cr &= ~(TIMER_1_INT_OVERFLOW \| TIMER_1_INT_MATCH2);
4750535b LW	186	cr \|= TIMER_1_INT_MATCH1;
e7bad212	187	writel(cr, fttmr010->base + TIMER_INTR_MASK);
4750535b	188
4750535b LW	189	return 0;
	190	}
	191
f5bf0ee4	192	static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
4750535b	193	{
e7bad212 LW	194	struct fttmr010 *fttmr010 = to_fttmr010(evt);
e7bad212 LW	195	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
4750535b LW	196	u32 cr;
4750535b LW	197
ec14ba1e	198	/* Stop */
e7bad212	199	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	200	cr &= ~fttmr010->t1_enable_val;
e7bad212	201	writel(cr, fttmr010->base + TIMER_CR);
4750535b	202
ec14ba1e LW	203	/* Setup timer to fire at 1/HZ intervals. */
	204	if (fttmr010->count_down) {
	205	writel(period, fttmr010->base + TIMER1_LOAD);
	206	writel(0, fttmr010->base + TIMER1_MATCH1);
	207	} else {
	208	cr = 0xffffffff - (period - 1);
	209	writel(cr, fttmr010->base + TIMER1_COUNT);
	210	writel(cr, fttmr010->base + TIMER1_LOAD);
	211
	212	/* Enable interrupt on overflow */
	213	cr = readl(fttmr010->base + TIMER_INTR_MASK);
	214	cr &= ~(TIMER_1_INT_MATCH1 \| TIMER_1_INT_MATCH2);
	215	cr \|= TIMER_1_INT_OVERFLOW;
	216	writel(cr, fttmr010->base + TIMER_INTR_MASK);
	217	}
4750535b LW	218
4750535b LW	219	/* Start the timer */
e7bad212	220	cr = readl(fttmr010->base + TIMER_CR);
ec14ba1e	221	cr \|= fttmr010->t1_enable_val;
e7bad212	222	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	223
	224	return 0;
	225	}
	226
4750535b LW	227	/*
	228	* IRQ handler for the timer
	229	*/
f5bf0ee4	230	static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
4750535b	231	{
e7bad212	232	struct clock_event_device *evt = dev_id;
4750535b LW	233
	234	evt->event_handler(evt);
	235	return IRQ_HANDLED;
	236	}
	237
ef89718a	238	static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
4750535b	239	{
e7bad212	240	struct fttmr010 *fttmr010;
4750535b	241	int irq;
dd98442e LW	242	struct clk *clk;
dd98442e LW	243	int ret;
ec14ba1e	244	u32 val;
dd98442e LW	245
	246	/*
	247	* These implementations require a clock reference.
	248	* FIXME: we currently only support clocking using PCLK
	249	* and using EXTCLK is not supported in the driver.
	250	*/
	251	clk = of_clk_get_by_name(np, "PCLK");
	252	if (IS_ERR(clk)) {
	253	pr_err("could not get PCLK\n");
	254	return PTR_ERR(clk);
	255	}
	256	ret = clk_prepare_enable(clk);
	257	if (ret) {
	258	pr_err("failed to enable PCLK\n");
	259	return ret;
	260	}
4750535b	261
e7bad212 LW	262	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
	263	if (!fttmr010) {
	264	ret = -ENOMEM;
	265	goto out_disable_clock;
	266	}
	267	fttmr010->tick_rate = clk_get_rate(clk);
	268
	269	fttmr010->base = of_iomap(np, 0);
	270	if (!fttmr010->base) {
1893428b	271	pr_err("Can't remap registers\n");
e7bad212 LW	272	ret = -ENXIO;
e7bad212 LW	273	goto out_free;
4750535b LW	274	}
	275	/* IRQ for timer 1 */
	276	irq = irq_of_parse_and_map(np, 0);
	277	if (irq <= 0) {
1893428b	278	pr_err("Can't parse IRQ\n");
e7bad212 LW	279	ret = -EINVAL;
e7bad212 LW	280	goto out_unmap;
4750535b LW	281	}
4750535b LW	282
ec14ba1e LW	283	/*
	284	* The Aspeed AST2400 moves bits around in the control register,
	285	* otherwise it works the same.
	286	*/
ef89718a	287	if (is_aspeed) {
ec14ba1e LW	288	fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE \|
	289	TIMER_1_CR_ASPEED_INT;
	290	/* Downward not available */
	291	fttmr010->count_down = true;
	292	} else {
	293	fttmr010->t1_enable_val = TIMER_1_CR_ENABLE \| TIMER_1_CR_INT;
	294	}
	295
4750535b LW	296	/*
	297	* Reset the interrupt mask and status
	298	*/
e7bad212 LW	299	writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
e7bad212 LW	300	writel(0, fttmr010->base + TIMER_INTR_STATE);
ec14ba1e LW	301
	302	/*
	303	* Enable timer 1 count up, timer 2 count up, except on Aspeed,
	304	* where everything just counts down.
	305	*/
ef89718a	306	if (is_aspeed)
ec14ba1e LW	307	val = TIMER_2_CR_ASPEED_ENABLE;
	308	else {
	309	val = TIMER_2_CR_ENABLE;
	310	if (!fttmr010->count_down)
	311	val \|= TIMER_1_CR_UPDOWN \| TIMER_2_CR_UPDOWN;
	312	}
	313	writel(val, fttmr010->base + TIMER_CR);
4750535b LW	314
	315	/*
	316	* Setup free-running clocksource timer (interrupts
	317	* disabled.)
	318	*/
e7bad212	319	local_fttmr = fttmr010;
b589da8b	320	writel(0, fttmr010->base + TIMER2_COUNT);
b589da8b LW	321	writel(0, fttmr010->base + TIMER2_MATCH1);
b589da8b LW	322	writel(0, fttmr010->base + TIMER2_MATCH2);
ec14ba1e LW	323
	324	if (fttmr010->count_down) {
	325	writel(~0, fttmr010->base + TIMER2_LOAD);
	326	clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
	327	"FTTMR010-TIMER2",
	328	fttmr010->tick_rate,
	329	300, 32, clocksource_mmio_readl_down);
740e237a LW	330	sched_clock_register(fttmr010_read_sched_clock_down, 32,
740e237a LW	331	fttmr010->tick_rate);
ec14ba1e LW	332	} else {
	333	writel(0, fttmr010->base + TIMER2_LOAD);
	334	clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
	335	"FTTMR010-TIMER2",
	336	fttmr010->tick_rate,
	337	300, 32, clocksource_mmio_readl_up);
740e237a LW	338	sched_clock_register(fttmr010_read_sched_clock_up, 32,
740e237a LW	339	fttmr010->tick_rate);
ec14ba1e	340	}
4750535b LW	341
4750535b LW	342	/*
e7bad212	343	* Setup clockevent timer (interrupt-driven) on timer 1.
4750535b	344	*/
e7bad212 LW	345	writel(0, fttmr010->base + TIMER1_COUNT);
	346	writel(0, fttmr010->base + TIMER1_LOAD);
	347	writel(0, fttmr010->base + TIMER1_MATCH1);
	348	writel(0, fttmr010->base + TIMER1_MATCH2);
	349	ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
	350	"FTTMR010-TIMER1", &fttmr010->clkevt);
	351	if (ret) {
	352	pr_err("FTTMR010-TIMER1 no IRQ\n");
	353	goto out_unmap;
	354	}
	355
	356	fttmr010->clkevt.name = "FTTMR010-TIMER1";
	357	/* Reasonably fast and accurate clock event */
	358	fttmr010->clkevt.rating = 300;
	359	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC \|
	360	CLOCK_EVT_FEAT_ONESHOT;
	361	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
	362	fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
	363	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
	364	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
	365	fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
	366	fttmr010->clkevt.cpumask = cpumask_of(0);
	367	fttmr010->clkevt.irq = irq;
	368	clockevents_config_and_register(&fttmr010->clkevt,
	369	fttmr010->tick_rate,
4750535b LW	370	1, 0xffffffff);
4750535b LW	371
385c98fc LW	372	#ifdef CONFIG_ARM
	373	/* Also use this timer for delays */
	374	if (fttmr010->count_down)
	375	fttmr010->delay_timer.read_current_timer =
	376	fttmr010_read_current_timer_down;
	377	else
	378	fttmr010->delay_timer.read_current_timer =
	379	fttmr010_read_current_timer_up;
	380	fttmr010->delay_timer.freq = fttmr010->tick_rate;
	381	register_current_timer_delay(&fttmr010->delay_timer);
	382	#endif
	383
4750535b	384	return 0;
e7bad212 LW	385
	386	out_unmap:
	387	iounmap(fttmr010->base);
	388	out_free:
	389	kfree(fttmr010);
	390	out_disable_clock:
	391	clk_disable_unprepare(clk);
	392
	393	return ret;
4750535b	394	}
ef89718a DL	395
	396	static __init int aspeed_timer_init(struct device_node *np)
	397	{
	398	return fttmr010_common_init(np, true);
	399	}
	400
	401	static __init int fttmr010_timer_init(struct device_node *np)
	402	{
	403	return fttmr010_common_init(np, false);
	404	}
	405
17273395 DL	406	TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
	407	TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
	408	TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
	409	TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
	410	TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);