[linux-2.6-block.git] / drivers / clocksource / timer-cs5535.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Clock event driver for the CS5535/CS5536
 *
 * Copyright (C) 2006, Advanced Micro Devices, Inc.
 * Copyright (C) 2007  Andres Salomon <dilinger@debian.org>
 * Copyright (C) 2009  Andres Salomon <dilinger@collabora.co.uk>
 *
 * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
 */

#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/cs5535.h>
#include <linux/clockchips.h>

#define DRV_NAME "cs5535-clockevt"

static int timer_irq;
module_param_hw_named(irq, timer_irq, int, irq, 0644);
MODULE_PARM_DESC(irq, "Which IRQ to use for the clock source MFGPT ticks.");

/*
 * We are using the 32.768kHz input clock - it's the only one that has the
 * ranges we find desirable.  The following table lists the suitable
 * divisors and the associated Hz, minimum interval and the maximum interval:
 *
 *  Divisor   Hz      Min Delta (s)  Max Delta (s)
 *   1        32768   .00048828125      2.000
 *   2        16384   .0009765625       4.000
 *   4         8192   .001953125        8.000
 *   8         4096   .00390625        16.000
 *   16        2048   .0078125         32.000
 *   32        1024   .015625          64.000
 *   64         512   .03125          128.000
 *  128         256   .0625           256.000
 *  256         128   .125            512.000
 */

static struct cs5535_mfgpt_timer *cs5535_event_clock;

/* Selected from the table above */

#define MFGPT_DIVISOR 16
#define MFGPT_SCALE  4     /* divisor = 2^(scale) */
#define MFGPT_HZ  (32768 / MFGPT_DIVISOR)
#define MFGPT_PERIODIC (MFGPT_HZ / HZ)

/*
 * The MFGPT timers on the CS5536 provide us with suitable timers to use
 * as clock event sources - not as good as a HPET or APIC, but certainly
 * better than the PIT.  This isn't a general purpose MFGPT driver, but
 * a simplified one designed specifically to act as a clock event source.
 * For full details about the MFGPT, please consult the CS5536 data sheet.
 */

static void disable_timer(struct cs5535_mfgpt_timer *timer)
{
	/* avoid races by clearing CMP1 and CMP2 unconditionally */
	cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
			(uint16_t) ~MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP1 |
				MFGPT_SETUP_CMP2);
}

static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta)
{
	cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta);
	cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0);

	cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
			MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
}

static int mfgpt_shutdown(struct clock_event_device *evt)
{
	disable_timer(cs5535_event_clock);
	return 0;
}

static int mfgpt_set_periodic(struct clock_event_device *evt)
{
	disable_timer(cs5535_event_clock);
	start_timer(cs5535_event_clock, MFGPT_PERIODIC);
	return 0;
}

static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
{
	start_timer(cs5535_event_clock, delta);
	return 0;
}

static struct clock_event_device cs5535_clockevent = {
	.name = DRV_NAME,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown = mfgpt_shutdown,
	.set_state_periodic = mfgpt_set_periodic,
	.set_state_oneshot = mfgpt_shutdown,
	.tick_resume = mfgpt_shutdown,
	.set_next_event = mfgpt_next_event,
	.rating = 250,
};

static irqreturn_t mfgpt_tick(int irq, void *dev_id)
{
	uint16_t val = cs5535_mfgpt_read(cs5535_event_clock, MFGPT_REG_SETUP);

	/* See if the interrupt was for us */
	if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1)))
		return IRQ_NONE;

	/* Turn off the clock (and clear the event) */
	disable_timer(cs5535_event_clock);

	if (clockevent_state_detached(&cs5535_clockevent) ||
	    clockevent_state_shutdown(&cs5535_clockevent))
		return IRQ_HANDLED;

	/* Clear the counter */
	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0);

	/* Restart the clock in periodic mode */

	if (clockevent_state_periodic(&cs5535_clockevent))
		cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
				MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);

	cs5535_clockevent.event_handler(&cs5535_clockevent);
	return IRQ_HANDLED;
}

static struct irqaction mfgptirq  = {
	.handler = mfgpt_tick,
	.flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
	.name = DRV_NAME,
};

static int __init cs5535_mfgpt_init(void)
{
	struct cs5535_mfgpt_timer *timer;
	int ret;
	uint16_t val;

	timer = cs5535_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
	if (!timer) {
		printk(KERN_ERR DRV_NAME ": Could not allocate MFGPT timer\n");
		return -ENODEV;
	}
	cs5535_event_clock = timer;

	/* Set up the IRQ on the MFGPT side */
	if (cs5535_mfgpt_setup_irq(timer, MFGPT_CMP2, &timer_irq)) {
		printk(KERN_ERR DRV_NAME ": Could not set up IRQ %d\n",
				timer_irq);
		goto err_timer;
	}

	/* And register it with the kernel */
	ret = setup_irq(timer_irq, &mfgptirq);
	if (ret) {
		printk(KERN_ERR DRV_NAME ": Unable to set up the interrupt.\n");
		goto err_irq;
	}

	/* Set the clock scale and enable the event mode for CMP2 */
	val = MFGPT_SCALE | (3 << 8);

	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, val);

	/* Set up the clock event */
	printk(KERN_INFO DRV_NAME
		": Registering MFGPT timer as a clock event, using IRQ %d\n",
		timer_irq);
	clockevents_config_and_register(&cs5535_clockevent, MFGPT_HZ,
					0xF, 0xFFFE);

	return 0;

err_irq:
	cs5535_mfgpt_release_irq(cs5535_event_clock, MFGPT_CMP2, &timer_irq);
err_timer:
	cs5535_mfgpt_free_timer(cs5535_event_clock);
	printk(KERN_ERR DRV_NAME ": Unable to set up the MFGPT clock source\n");
	return -EIO;
}

module_init(cs5535_mfgpt_init);

MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
MODULE_DESCRIPTION("CS5535/CS5536 MFGPT clock event driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
25763b3c	1	// SPDX-License-Identifier: GPL-2.0-only
c30d7d2b AS	2	/*
	3	* Clock event driver for the CS5535/CS5536
	4	*
	5	* Copyright (C) 2006, Advanced Micro Devices, Inc.
	6	* Copyright (C) 2007 Andres Salomon <dilinger@debian.org>
	7	* Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
	8	*
c30d7d2b AS	9	* The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/irq.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/module.h>
	16	#include <linux/cs5535.h>
	17	#include <linux/clockchips.h>
	18
	19	#define DRV_NAME "cs5535-clockevt"
	20
115079aa	21	static int timer_irq;
cc9c6175	22	module_param_hw_named(irq, timer_irq, int, irq, 0644);
c30d7d2b AS	23	MODULE_PARM_DESC(irq, "Which IRQ to use for the clock source MFGPT ticks.");
	24
	25	/*
	26	* We are using the 32.768kHz input clock - it's the only one that has the
	27	* ranges we find desirable. The following table lists the suitable
	28	* divisors and the associated Hz, minimum interval and the maximum interval:
	29	*
	30	* Divisor Hz Min Delta (s) Max Delta (s)
	31	* 1 32768 .00048828125 2.000
	32	* 2 16384 .0009765625 4.000
	33	* 4 8192 .001953125 8.000
	34	* 8 4096 .00390625 16.000
	35	* 16 2048 .0078125 32.000
	36	* 32 1024 .015625 64.000
	37	* 64 512 .03125 128.000
	38	* 128 256 .0625 256.000
	39	* 256 128 .125 512.000
	40	*/
	41
c30d7d2b AS	42	static struct cs5535_mfgpt_timer *cs5535_event_clock;
	43
	44	/* Selected from the table above */
	45
	46	#define MFGPT_DIVISOR 16
	47	#define MFGPT_SCALE 4 /* divisor = 2^(scale) */
	48	#define MFGPT_HZ (32768 / MFGPT_DIVISOR)
	49	#define MFGPT_PERIODIC (MFGPT_HZ / HZ)
	50
	51	/*
61e01be2	52	* The MFGPT timers on the CS5536 provide us with suitable timers to use
c30d7d2b AS	53	* as clock event sources - not as good as a HPET or APIC, but certainly
	54	* better than the PIT. This isn't a general purpose MFGPT driver, but
	55	* a simplified one designed specifically to act as a clock event source.
	56	* For full details about the MFGPT, please consult the CS5536 data sheet.
	57	*/
	58
	59	static void disable_timer(struct cs5535_mfgpt_timer *timer)
	60	{
	61	/* avoid races by clearing CMP1 and CMP2 unconditionally */
	62	cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
	63	(uint16_t) ~MFGPT_SETUP_CNTEN \| MFGPT_SETUP_CMP1 \|
	64	MFGPT_SETUP_CMP2);
	65	}
	66
	67	static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta)
	68	{
	69	cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta);
	70	cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0);
	71
	72	cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
	73	MFGPT_SETUP_CNTEN \| MFGPT_SETUP_CMP2);
	74	}
	75
8f9327cb	76	static int mfgpt_shutdown(struct clock_event_device *evt)
c30d7d2b AS	77	{
c30d7d2b AS	78	disable_timer(cs5535_event_clock);
8f9327cb VK	79	return 0;
8f9327cb VK	80	}
c30d7d2b	81
8f9327cb VK	82	static int mfgpt_set_periodic(struct clock_event_device *evt)
	83	{
	84	disable_timer(cs5535_event_clock);
	85	start_timer(cs5535_event_clock, MFGPT_PERIODIC);
	86	return 0;
c30d7d2b AS	87	}
	88
	89	static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
	90	{
	91	start_timer(cs5535_event_clock, delta);
	92	return 0;
	93	}
	94
	95	static struct clock_event_device cs5535_clockevent = {
	96	.name = DRV_NAME,
	97	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
8f9327cb VK	98	.set_state_shutdown = mfgpt_shutdown,
	99	.set_state_periodic = mfgpt_set_periodic,
	100	.set_state_oneshot = mfgpt_shutdown,
	101	.tick_resume = mfgpt_shutdown,
c30d7d2b AS	102	.set_next_event = mfgpt_next_event,
c30d7d2b AS	103	.rating = 250,
c30d7d2b AS	104	};
	105
	106	static irqreturn_t mfgpt_tick(int irq, void *dev_id)
	107	{
	108	uint16_t val = cs5535_mfgpt_read(cs5535_event_clock, MFGPT_REG_SETUP);
	109
	110	/* See if the interrupt was for us */
	111	if (!(val & (MFGPT_SETUP_SETUP \| MFGPT_SETUP_CMP2 \| MFGPT_SETUP_CMP1)))
	112	return IRQ_NONE;
	113
	114	/* Turn off the clock (and clear the event) */
	115	disable_timer(cs5535_event_clock);
	116
eb39a7c0 DK	117	if (clockevent_state_detached(&cs5535_clockevent) \|\|
eb39a7c0 DK	118	clockevent_state_shutdown(&cs5535_clockevent))
c30d7d2b AS	119	return IRQ_HANDLED;
	120
	121	/* Clear the counter */
	122	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0);
	123
	124	/* Restart the clock in periodic mode */
	125
8f9327cb	126	if (clockevent_state_periodic(&cs5535_clockevent))
c30d7d2b AS	127	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
	128	MFGPT_SETUP_CNTEN \| MFGPT_SETUP_CMP2);
	129
	130	cs5535_clockevent.event_handler(&cs5535_clockevent);
	131	return IRQ_HANDLED;
	132	}
	133
	134	static struct irqaction mfgptirq = {
	135	.handler = mfgpt_tick,
38c30a84	136	.flags = IRQF_NOBALANCING \| IRQF_TIMER \| IRQF_SHARED,
c30d7d2b AS	137	.name = DRV_NAME,
	138	};
	139
	140	static int __init cs5535_mfgpt_init(void)
	141	{
	142	struct cs5535_mfgpt_timer *timer;
	143	int ret;
	144	uint16_t val;
	145
	146	timer = cs5535_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
	147	if (!timer) {
61e01be2	148	printk(KERN_ERR DRV_NAME ": Could not allocate MFGPT timer\n");
c30d7d2b AS	149	return -ENODEV;
	150	}
	151	cs5535_event_clock = timer;
	152
	153	/* Set up the IRQ on the MFGPT side */
	154	if (cs5535_mfgpt_setup_irq(timer, MFGPT_CMP2, &timer_irq)) {
	155	printk(KERN_ERR DRV_NAME ": Could not set up IRQ %d\n",
	156	timer_irq);
fdb19a6c	157	goto err_timer;
c30d7d2b AS	158	}
	159
	160	/* And register it with the kernel */
	161	ret = setup_irq(timer_irq, &mfgptirq);
	162	if (ret) {
	163	printk(KERN_ERR DRV_NAME ": Unable to set up the interrupt.\n");
fdb19a6c	164	goto err_irq;
c30d7d2b AS	165	}
	166
	167	/* Set the clock scale and enable the event mode for CMP2 */
	168	val = MFGPT_SCALE \| (3 << 8);
	169
	170	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, val);
	171
	172	/* Set up the clock event */
c30d7d2b AS	173	printk(KERN_INFO DRV_NAME
	174	": Registering MFGPT timer as a clock event, using IRQ %d\n",
	175	timer_irq);
77cc982f SG	176	clockevents_config_and_register(&cs5535_clockevent, MFGPT_HZ,
77cc982f SG	177	0xF, 0xFFFE);
c30d7d2b AS	178
	179	return 0;
	180
fdb19a6c	181	err_irq:
c30d7d2b	182	cs5535_mfgpt_release_irq(cs5535_event_clock, MFGPT_CMP2, &timer_irq);
fdb19a6c JR	183	err_timer:
fdb19a6c JR	184	cs5535_mfgpt_free_timer(cs5535_event_clock);
c30d7d2b AS	185	printk(KERN_ERR DRV_NAME ": Unable to set up the MFGPT clock source\n");
	186	return -EIO;
	187	}
	188
	189	module_init(cs5535_mfgpt_init);
	190
d45840d9	191	MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
c30d7d2b AS	192	MODULE_DESCRIPTION("CS5535/CS5536 MFGPT clock event driver");
c30d7d2b AS	193	MODULE_LICENSE("GPL");