[linux-2.6-block.git] / drivers / clocksource / timer-cadence-ttc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * This file contains driver for the Cadence Triple Timer Counter Rev 06
 *
 *  Copyright (C) 2011-2013 Xilinx
 *
 * based on arch/mips/kernel/time.c timer driver
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>

/*
 * This driver configures the 2 16/32-bit count-up timers as follows:
 *
 * T1: Timer 1, clocksource for generic timekeeping
 * T2: Timer 2, clockevent source for hrtimers
 * T3: Timer 3, <unused>
 *
 * The input frequency to the timer module for emulation is 2.5MHz which is
 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
 * the timers are clocked at 78.125KHz (12.8 us resolution).

 * The input frequency to the timer module in silicon is configurable and
 * obtained from device tree. The pre-scaler of 32 is used.
 */

/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
#define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
#define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
#define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
#define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */

#define TTC_CNT_CNTRL_DISABLE_MASK	0x1

#define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */
#define TTC_CLK_CNTRL_PSV_MASK		0x1e
#define TTC_CLK_CNTRL_PSV_SHIFT		1

/*
 * Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
#define CNT_CNTRL_RESET		(1 << 4)

#define MAX_F_ERR 50

/**
 * struct ttc_timer - This definition defines local timer structure
 *
 * @base_addr:	Base address of timer
 * @freq:	Timer input clock frequency
 * @clk:	Associated clock source
 * @clk_rate_change_nb	Notifier block for clock rate changes
 */
struct ttc_timer {
	void __iomem *base_addr;
	unsigned long freq;
	struct clk *clk;
	struct notifier_block clk_rate_change_nb;
};

#define to_ttc_timer(x) \
		container_of(x, struct ttc_timer, clk_rate_change_nb)

struct ttc_timer_clocksource {
	u32			scale_clk_ctrl_reg_old;
	u32			scale_clk_ctrl_reg_new;
	struct ttc_timer	ttc;
	struct clocksource	cs;
};

#define to_ttc_timer_clksrc(x) \
		container_of(x, struct ttc_timer_clocksource, cs)

struct ttc_timer_clockevent {
	struct ttc_timer		ttc;
	struct clock_event_device	ce;
};

#define to_ttc_timer_clkevent(x) \
		container_of(x, struct ttc_timer_clockevent, ce)

static void __iomem *ttc_sched_clock_val_reg;

/**
 * ttc_set_interval - Set the timer interval value
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
static void ttc_set_interval(struct ttc_timer *timer,
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);

	/*
	 * Reset the counter (0x10) so that it starts from 0, one-shot
	 * mode makes this needed for timing to be right.
	 */
	ctrl_reg |= CNT_CNTRL_RESET;
	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
}

/**
 * ttc_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the ttc_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
{
	struct ttc_timer_clockevent *ttce = dev_id;
	struct ttc_timer *timer = &ttce->ttc;

	/* Acknowledge the interrupt and call event handler */
	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);

	ttce->ce.event_handler(&ttce->ce);

	return IRQ_HANDLED;
}

/**
 * __ttc_clocksource_read - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
static u64 __ttc_clocksource_read(struct clocksource *cs)
{
	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;

	return (u64)readl_relaxed(timer->base_addr +
				TTC_COUNT_VAL_OFFSET);
}

static u64 notrace ttc_sched_clock_read(void)
{
	return readl_relaxed(ttc_sched_clock_val_reg);
}

/**
 * ttc_set_next_event - Sets the time interval for next event
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
static int ttc_set_next_event(unsigned long cycles,
					struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;

	ttc_set_interval(timer, cycles);
	return 0;
}

/**
 * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
 *
 * @evt:	Address of clock event instance
 **/
static int ttc_shutdown(struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
	u32 ctrl_reg;

	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	return 0;
}

static int ttc_set_periodic(struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;

	ttc_set_interval(timer,
			 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
	return 0;
}

static int ttc_resume(struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
	u32 ctrl_reg;

	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	return 0;
}

static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clocksource *ttccs = container_of(ttc,
			struct ttc_timer_clocksource, ttc);

	switch (event) {
	case PRE_RATE_CHANGE:
	{
		u32 psv;
		unsigned long factor, rate_low, rate_high;

		if (ndata->new_rate > ndata->old_rate) {
			factor = DIV_ROUND_CLOSEST(ndata->new_rate,
					ndata->old_rate);
			rate_low = ndata->old_rate;
			rate_high = ndata->new_rate;
		} else {
			factor = DIV_ROUND_CLOSEST(ndata->old_rate,
					ndata->new_rate);
			rate_low = ndata->new_rate;
			rate_high = ndata->old_rate;
		}

		if (!is_power_of_2(factor))
				return NOTIFY_BAD;

		if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
			return NOTIFY_BAD;

		factor = __ilog2_u32(factor);

		/*
		 * store timer clock ctrl register so we can restore it in case
		 * of an abort.
		 */
		ttccs->scale_clk_ctrl_reg_old =
			readl_relaxed(ttccs->ttc.base_addr +
			TTC_CLK_CNTRL_OFFSET);

		psv = (ttccs->scale_clk_ctrl_reg_old &
				TTC_CLK_CNTRL_PSV_MASK) >>
				TTC_CLK_CNTRL_PSV_SHIFT;
		if (ndata->new_rate < ndata->old_rate)
			psv -= factor;
		else
			psv += factor;

		/* prescaler within legal range? */
		if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
			return NOTIFY_BAD;

		ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
			~TTC_CLK_CNTRL_PSV_MASK;
		ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;


		/* scale down: adjust divider in post-change notification */
		if (ndata->new_rate < ndata->old_rate)
			return NOTIFY_DONE;

		/* scale up: adjust divider now - before frequency change */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		break;
	}
	case POST_RATE_CHANGE:
		/* scale up: pre-change notification did the adjustment */
		if (ndata->new_rate > ndata->old_rate)
			return NOTIFY_OK;

		/* scale down: adjust divider now - after frequency change */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		break;

	case ABORT_RATE_CHANGE:
		/* we have to undo the adjustment in case we scale up */
		if (ndata->new_rate < ndata->old_rate)
			return NOTIFY_OK;

		/* restore original register value */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		/* fall through */
	default:
		return NOTIFY_DONE;
	}

	return NOTIFY_DONE;
}

static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
					 u32 timer_width)
{
	struct ttc_timer_clocksource *ttccs;
	int err;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (!ttccs)
		return -ENOMEM;

	ttccs->ttc.clk = clk;

	err = clk_prepare_enable(ttccs->ttc.clk);
	if (err) {
		kfree(ttccs);
		return err;
	}

	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);

	ttccs->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clocksource_cb;
	ttccs->ttc.clk_rate_change_nb.next = NULL;

	err = clk_notifier_register(ttccs->ttc.clk,
				    &ttccs->ttc.clk_rate_change_nb);
	if (err)
		pr_warn("Unable to register clock notifier.\n");

	ttccs->ttc.base_addr = base;
	ttccs->cs.name = "ttc_clocksource";
	ttccs->cs.rating = 200;
	ttccs->cs.read = __ttc_clocksource_read;
	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	/*
	 * Setup the clock source counter to be an incrementing counter
	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
	 * it by 32 also. Let it start running now.
	 */
	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	writel_relaxed(CNT_CNTRL_RESET,
		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);

	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
	if (err) {
		kfree(ttccs);
		return err;
	}

	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
	sched_clock_register(ttc_sched_clock_read, timer_width,
			     ttccs->ttc.freq / PRESCALE);

	return 0;
}

static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clockevent *ttcce = container_of(ttc,
			struct ttc_timer_clockevent, ttc);

	switch (event) {
	case POST_RATE_CHANGE:
		/* update cached frequency */
		ttc->freq = ndata->new_rate;

		clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);

		/* fall through */
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

static int __init ttc_setup_clockevent(struct clk *clk,
				       void __iomem *base, u32 irq)
{
	struct ttc_timer_clockevent *ttcce;
	int err;

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (!ttcce)
		return -ENOMEM;

	ttcce->ttc.clk = clk;

	err = clk_prepare_enable(ttcce->ttc.clk);
	if (err) {
		kfree(ttcce);
		return err;
	}

	ttcce->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clockevent_cb;
	ttcce->ttc.clk_rate_change_nb.next = NULL;

	err = clk_notifier_register(ttcce->ttc.clk,
				    &ttcce->ttc.clk_rate_change_nb);
	if (err) {
		pr_warn("Unable to register clock notifier.\n");
		return err;
	}

	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);

	ttcce->ttc.base_addr = base;
	ttcce->ce.name = "ttc_clockevent";
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ttcce->ce.set_next_event = ttc_set_next_event;
	ttcce->ce.set_state_shutdown = ttc_shutdown;
	ttcce->ce.set_state_periodic = ttc_set_periodic;
	ttcce->ce.set_state_oneshot = ttc_shutdown;
	ttcce->ce.tick_resume = ttc_resume;
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;
	ttcce->ce.cpumask = cpu_possible_mask;

	/*
	 * Setup the clock event timer to be an interval timer which
	 * is prescaled by 32 using the interval interrupt. Leave it
	 * disabled for now.
	 */
	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);

	err = request_irq(irq, ttc_clock_event_interrupt,
			  IRQF_TIMER, ttcce->ce.name, ttcce);
	if (err) {
		kfree(ttcce);
		return err;
	}

	clockevents_config_and_register(&ttcce->ce,
			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);

	return 0;
}

/**
 * ttc_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 */
static int __init ttc_timer_init(struct device_node *timer)
{
	unsigned int irq;
	void __iomem *timer_baseaddr;
	struct clk *clk_cs, *clk_ce;
	static int initialized;
	int clksel, ret;
	u32 timer_width = 16;

	if (initialized)
		return 0;

	initialized = 1;

	/*
	 * Get the 1st Triple Timer Counter (TTC) block from the device tree
	 * and use it. Note that the event timer uses the interrupt and it's the
	 * 2nd TTC hence the irq_of_parse_and_map(,1)
	 */
	timer_baseaddr = of_iomap(timer, 0);
	if (!timer_baseaddr) {
		pr_err("ERROR: invalid timer base address\n");
		return -ENXIO;
	}

	irq = irq_of_parse_and_map(timer, 1);
	if (irq <= 0) {
		pr_err("ERROR: invalid interrupt number\n");
		return -EINVAL;
	}

	of_property_read_u32(timer, "timer-width", &timer_width);

	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_cs = of_clk_get(timer, clksel);
	if (IS_ERR(clk_cs)) {
		pr_err("ERROR: timer input clock not found\n");
		return PTR_ERR(clk_cs);
	}

	clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_ce = of_clk_get(timer, clksel);
	if (IS_ERR(clk_ce)) {
		pr_err("ERROR: timer input clock not found\n");
		return PTR_ERR(clk_ce);
	}

	ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
	if (ret)
		return ret;

	ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
	if (ret)
		return ret;

	pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);

	return 0;
}

TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
b85a3ef4	2	/*
9e09dc5f	3	* This file contains driver for the Cadence Triple Timer Counter Rev 06
b85a3ef4	4	*
e932900a	5	* Copyright (C) 2011-2013 Xilinx
b85a3ef4 JL	6	*
b85a3ef4 JL	7	* based on arch/mips/kernel/time.c timer driver
b85a3ef4 JL	8	*/
b85a3ef4 JL	9
e932900a	10	#include <linux/clk.h>
b85a3ef4	11	#include <linux/interrupt.h>
b85a3ef4	12	#include <linux/clockchips.h>
459fa246	13	#include <linux/clocksource.h>
91dc985c JC	14	#include <linux/of_address.h>
	15	#include <linux/of_irq.h>
	16	#include <linux/slab.h>
3d77b30e	17	#include <linux/sched_clock.h>
b85a3ef4	18
e932900a	19	/*
4e2bec0c	20	* This driver configures the 2 16/32-bit count-up timers as follows:
e932900a MS	21	*
	22	* T1: Timer 1, clocksource for generic timekeeping
	23	* T2: Timer 2, clockevent source for hrtimers
	24	* T3: Timer 3, <unused>
	25	*
	26	* The input frequency to the timer module for emulation is 2.5MHz which is
	27	* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
	28	* the timers are clocked at 78.125KHz (12.8 us resolution).
	29
	30	* The input frequency to the timer module in silicon is configurable and
	31	* obtained from device tree. The pre-scaler of 32 is used.
	32	*/
	33
b85a3ef4 JL	34	/*
	35	* Timer Register Offset Definitions of Timer 1, Increment base address by 4
	36	* and use same offsets for Timer 2
	37	*/
9e09dc5f MS	38	#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
	39	#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
	40	#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
	41	#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
	42	#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
	43	#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
f184c5ca	44
9e09dc5f	45	#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
b85a3ef4	46
30e1e285	47	#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
b3e90722 SB	48	#define TTC_CLK_CNTRL_PSV_MASK 0x1e
b3e90722 SB	49	#define TTC_CLK_CNTRL_PSV_SHIFT 1
30e1e285	50
03377e58 SB	51	/*
03377e58 SB	52	* Setup the timers to use pre-scaling, using a fixed value for now that will
91dc985c JC	53	* work across most input frequency, but it may need to be more dynamic
	54	*/
	55	#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
	56	#define PRESCALE 2048 /* The exponent must match this */
	57	#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
	58	#define CLK_CNTRL_PRESCALE_EN 1
e932900a	59	#define CNT_CNTRL_RESET (1 << 4)
b85a3ef4	60
b3e90722 SB	61	#define MAX_F_ERR 50
b3e90722 SB	62
b85a3ef4	63	/**
9e09dc5f	64	* struct ttc_timer - This definition defines local timer structure
b85a3ef4 JL	65	*
b85a3ef4 JL	66	* @base_addr: Base address of timer
c1dcc927	67	* @freq: Timer input clock frequency
e932900a MS	68	* @clk: Associated clock source
	69	* @clk_rate_change_nb Notifier block for clock rate changes
	70	*/
9e09dc5f	71	struct ttc_timer {
e932900a	72	void __iomem *base_addr;
c1dcc927	73	unsigned long freq;
e932900a MS	74	struct clk *clk;
e932900a MS	75	struct notifier_block clk_rate_change_nb;
91dc985c JC	76	};
91dc985c JC	77
9e09dc5f MS	78	#define to_ttc_timer(x) \
9e09dc5f MS	79	container_of(x, struct ttc_timer, clk_rate_change_nb)
e932900a	80
9e09dc5f	81	struct ttc_timer_clocksource {
b3e90722 SB	82	u32 scale_clk_ctrl_reg_old;
b3e90722 SB	83	u32 scale_clk_ctrl_reg_new;
9e09dc5f	84	struct ttc_timer ttc;
91dc985c	85	struct clocksource cs;
b85a3ef4 JL	86	};
b85a3ef4 JL	87
9e09dc5f MS	88	#define to_ttc_timer_clksrc(x) \
9e09dc5f MS	89	container_of(x, struct ttc_timer_clocksource, cs)
91dc985c	90
9e09dc5f MS	91	struct ttc_timer_clockevent {
9e09dc5f MS	92	struct ttc_timer ttc;
91dc985c	93	struct clock_event_device ce;
91dc985c JC	94	};
91dc985c JC	95
9e09dc5f MS	96	#define to_ttc_timer_clkevent(x) \
9e09dc5f MS	97	container_of(x, struct ttc_timer_clockevent, ce)
b85a3ef4	98
3d77b30e SB	99	static void __iomem *ttc_sched_clock_val_reg;
3d77b30e SB	100
b85a3ef4	101	/**
9e09dc5f	102	* ttc_set_interval - Set the timer interval value
b85a3ef4 JL	103	*
	104	* @timer: Pointer to the timer instance
	105	* @cycles: Timer interval ticks
	106	**/
9e09dc5f	107	static void ttc_set_interval(struct ttc_timer *timer,
b85a3ef4 JL	108	unsigned long cycles)
	109	{
	110	u32 ctrl_reg;
	111
	112	/* Disable the counter, set the counter value and re-enable counter */
87ab4361	113	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
9e09dc5f	114	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
87ab4361	115	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4	116
87ab4361	117	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
b85a3ef4	118
03377e58 SB	119	/*
	120	* Reset the counter (0x10) so that it starts from 0, one-shot
	121	* mode makes this needed for timing to be right.
	122	*/
91dc985c	123	ctrl_reg \|= CNT_CNTRL_RESET;
9e09dc5f	124	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
87ab4361	125	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	126	}
	127
	128	/**
9e09dc5f	129	* ttc_clock_event_interrupt - Clock event timer interrupt handler
b85a3ef4 JL	130	*
b85a3ef4 JL	131	* @irq: IRQ number of the Timer
9e09dc5f	132	* @dev_id: void pointer to the ttc_timer instance
b85a3ef4 JL	133	*
	134	* returns: Always IRQ_HANDLED - success
	135	**/
9e09dc5f	136	static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
b85a3ef4	137	{
9e09dc5f MS	138	struct ttc_timer_clockevent *ttce = dev_id;
9e09dc5f MS	139	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	140
b85a3ef4 JL	141	/* Acknowledge the interrupt and call event handler */
87ab4361	142	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
b85a3ef4	143
9e09dc5f	144	ttce->ce.event_handler(&ttce->ce);
b85a3ef4 JL	145
	146	return IRQ_HANDLED;
	147	}
	148
b85a3ef4	149	/**
9e09dc5f	150	* __ttc_clocksource_read - Reads the timer counter register
b85a3ef4 JL	151	*
	152	* returns: Current timer counter register value
	153	**/
a5a1d1c2	154	static u64 __ttc_clocksource_read(struct clocksource *cs)
b85a3ef4	155	{
9e09dc5f	156	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
b85a3ef4	157
a5a1d1c2	158	return (u64)readl_relaxed(timer->base_addr +
9e09dc5f	159	TTC_COUNT_VAL_OFFSET);
b85a3ef4 JL	160	}
b85a3ef4 JL	161
dfded009	162	static u64 notrace ttc_sched_clock_read(void)
3d77b30e	163	{
87ab4361	164	return readl_relaxed(ttc_sched_clock_val_reg);
3d77b30e SB	165	}
3d77b30e SB	166
b85a3ef4	167	/**
9e09dc5f	168	* ttc_set_next_event - Sets the time interval for next event
b85a3ef4 JL	169	*
	170	* @cycles: Timer interval ticks
	171	* @evt: Address of clock event instance
	172	*
	173	* returns: Always 0 - success
	174	**/
9e09dc5f	175	static int ttc_set_next_event(unsigned long cycles,
b85a3ef4 JL	176	struct clock_event_device *evt)
b85a3ef4 JL	177	{
9e09dc5f MS	178	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	179	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4	180
9e09dc5f	181	ttc_set_interval(timer, cycles);
b85a3ef4 JL	182	return 0;
	183	}
	184
	185	/**
5c0a4bbe	186	* ttc_set_{shutdown\|oneshot\|periodic} - Sets the state of timer
b85a3ef4	187	*
b85a3ef4 JL	188	* @evt: Address of clock event instance
b85a3ef4 JL	189	**/
5c0a4bbe	190	static int ttc_shutdown(struct clock_event_device *evt)
b85a3ef4	191	{
9e09dc5f MS	192	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	193	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	194	u32 ctrl_reg;
b85a3ef4 JL	195
5c0a4bbe VK	196	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	197	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
	198	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	199	return 0;
	200	}
	201
	202	static int ttc_set_periodic(struct clock_event_device *evt)
	203	{
	204	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	205	struct ttc_timer *timer = &ttce->ttc;
	206
	207	ttc_set_interval(timer,
	208	DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
	209	return 0;
	210	}
	211
	212	static int ttc_resume(struct clock_event_device *evt)
	213	{
	214	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	215	struct ttc_timer *timer = &ttce->ttc;
	216	u32 ctrl_reg;
	217
	218	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	219	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	220	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	221	return 0;
b85a3ef4 JL	222	}
b85a3ef4 JL	223
9e09dc5f	224	static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
e932900a MS	225	unsigned long event, void *data)
	226	{
	227	struct clk_notifier_data *ndata = data;
9e09dc5f MS	228	struct ttc_timer *ttc = to_ttc_timer(nb);
	229	struct ttc_timer_clocksource *ttccs = container_of(ttc,
	230	struct ttc_timer_clocksource, ttc);
e932900a MS	231
e932900a MS	232	switch (event) {
b3e90722 SB	233	case PRE_RATE_CHANGE:
	234	{
	235	u32 psv;
	236	unsigned long factor, rate_low, rate_high;
	237
	238	if (ndata->new_rate > ndata->old_rate) {
	239	factor = DIV_ROUND_CLOSEST(ndata->new_rate,
	240	ndata->old_rate);
	241	rate_low = ndata->old_rate;
	242	rate_high = ndata->new_rate;
	243	} else {
	244	factor = DIV_ROUND_CLOSEST(ndata->old_rate,
	245	ndata->new_rate);
	246	rate_low = ndata->new_rate;
	247	rate_high = ndata->old_rate;
	248	}
	249
	250	if (!is_power_of_2(factor))
	251	return NOTIFY_BAD;
	252
	253	if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
	254	return NOTIFY_BAD;
	255
	256	factor = __ilog2_u32(factor);
	257
e932900a	258	/*
b3e90722 SB	259	* store timer clock ctrl register so we can restore it in case
b3e90722 SB	260	* of an abort.
e932900a	261	*/
b3e90722	262	ttccs->scale_clk_ctrl_reg_old =
87ab4361 MS	263	readl_relaxed(ttccs->ttc.base_addr +
87ab4361 MS	264	TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	265
	266	psv = (ttccs->scale_clk_ctrl_reg_old &
	267	TTC_CLK_CNTRL_PSV_MASK) >>
	268	TTC_CLK_CNTRL_PSV_SHIFT;
	269	if (ndata->new_rate < ndata->old_rate)
	270	psv -= factor;
	271	else
	272	psv += factor;
	273
	274	/* prescaler within legal range? */
	275	if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
	276	return NOTIFY_BAD;
	277
	278	ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
	279	~TTC_CLK_CNTRL_PSV_MASK;
	280	ttccs->scale_clk_ctrl_reg_new \|= psv << TTC_CLK_CNTRL_PSV_SHIFT;
	281
	282
	283	/* scale down: adjust divider in post-change notification */
	284	if (ndata->new_rate < ndata->old_rate)
	285	return NOTIFY_DONE;
	286
	287	/* scale up: adjust divider now - before frequency change */
87ab4361 MS	288	writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
87ab4361 MS	289	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	290	break;
	291	}
	292	case POST_RATE_CHANGE:
	293	/* scale up: pre-change notification did the adjustment */
	294	if (ndata->new_rate > ndata->old_rate)
	295	return NOTIFY_OK;
	296
	297	/* scale down: adjust divider now - after frequency change */
87ab4361 MS	298	writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
87ab4361 MS	299	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	300	break;
b3e90722 SB	301
e932900a	302	case ABORT_RATE_CHANGE:
b3e90722 SB	303	/* we have to undo the adjustment in case we scale up */
	304	if (ndata->new_rate < ndata->old_rate)
	305	return NOTIFY_OK;
	306
	307	/* restore original register value */
87ab4361 MS	308	writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
87ab4361 MS	309	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
b3e90722	310	/* fall through */
e932900a MS	311	default:
	312	return NOTIFY_DONE;
	313	}
b3e90722 SB	314
b3e90722 SB	315	return NOTIFY_DONE;
e932900a MS	316	}
e932900a MS	317
70504f31	318	static int __init ttc_setup_clocksource(struct clk clk, void __iomem base,
4e2bec0c	319	u32 timer_width)
91dc985c	320	{
9e09dc5f	321	struct ttc_timer_clocksource *ttccs;
91dc985c	322	int err;
91dc985c JC	323
91dc985c JC	324	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
70504f31 DL	325	if (!ttccs)
70504f31 DL	326	return -ENOMEM;
91dc985c	327
9e09dc5f	328	ttccs->ttc.clk = clk;
91dc985c	329
9e09dc5f	330	err = clk_prepare_enable(ttccs->ttc.clk);
70504f31	331	if (err) {
c5263bb8	332	kfree(ttccs);
70504f31	333	return err;
c5263bb8	334	}
91dc985c	335
c1dcc927 SB	336	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
c1dcc927 SB	337
9e09dc5f MS	338	ttccs->ttc.clk_rate_change_nb.notifier_call =
	339	ttc_rate_change_clocksource_cb;
	340	ttccs->ttc.clk_rate_change_nb.next = NULL;
70504f31 DL	341
	342	err = clk_notifier_register(ttccs->ttc.clk,
	343	&ttccs->ttc.clk_rate_change_nb);
	344	if (err)
e932900a	345	pr_warn("Unable to register clock notifier.\n");
91dc985c	346
9e09dc5f MS	347	ttccs->ttc.base_addr = base;
9e09dc5f MS	348	ttccs->cs.name = "ttc_clocksource";
91dc985c	349	ttccs->cs.rating = 200;
9e09dc5f	350	ttccs->cs.read = __ttc_clocksource_read;
4e2bec0c	351	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
91dc985c JC	352	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
91dc985c JC	353
e932900a MS	354	/*
	355	* Setup the clock source counter to be an incrementing counter
	356	* with no interrupt and it rolls over at 0xFFFF. Pre-scale
	357	* it by 32 also. Let it start running now.
	358	*/
87ab4361 MS	359	writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
87ab4361 MS	360	writel_relaxed(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f	361	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
87ab4361	362	writel_relaxed(CNT_CNTRL_RESET,
9e09dc5f	363	ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
91dc985c	364
c1dcc927	365	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
70504f31	366	if (err) {
c5263bb8	367	kfree(ttccs);
70504f31	368	return err;
c5263bb8	369	}
3d77b30e SB	370
3d77b30e SB	371	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
4e2bec0c MS	372	sched_clock_register(ttc_sched_clock_read, timer_width,
4e2bec0c MS	373	ttccs->ttc.freq / PRESCALE);
70504f31 DL	374
70504f31 DL	375	return 0;
91dc985c JC	376	}
91dc985c JC	377
9e09dc5f	378	static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
e932900a MS	379	unsigned long event, void *data)
	380	{
	381	struct clk_notifier_data *ndata = data;
9e09dc5f MS	382	struct ttc_timer *ttc = to_ttc_timer(nb);
	383	struct ttc_timer_clockevent *ttcce = container_of(ttc,
	384	struct ttc_timer_clockevent, ttc);
e932900a MS	385
	386	switch (event) {
	387	case POST_RATE_CHANGE:
c1dcc927 SB	388	/* update cached frequency */
	389	ttc->freq = ndata->new_rate;
	390
5f0ba3b4 SB	391	clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
5f0ba3b4 SB	392
e932900a	393	/* fall through */
e932900a MS	394	case PRE_RATE_CHANGE:
	395	case ABORT_RATE_CHANGE:
	396	default:
	397	return NOTIFY_DONE;
	398	}
	399	}
	400
70504f31 DL	401	static int __init ttc_setup_clockevent(struct clk *clk,
70504f31 DL	402	void __iomem *base, u32 irq)
91dc985c	403	{
9e09dc5f	404	struct ttc_timer_clockevent *ttcce;
e932900a	405	int err;
91dc985c JC	406
91dc985c JC	407	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
70504f31 DL	408	if (!ttcce)
70504f31 DL	409	return -ENOMEM;
91dc985c	410
9e09dc5f	411	ttcce->ttc.clk = clk;
91dc985c	412
9e09dc5f	413	err = clk_prepare_enable(ttcce->ttc.clk);
70504f31	414	if (err) {
c5263bb8	415	kfree(ttcce);
70504f31	416	return err;
c5263bb8	417	}
91dc985c	418
9e09dc5f MS	419	ttcce->ttc.clk_rate_change_nb.notifier_call =
	420	ttc_rate_change_clockevent_cb;
	421	ttcce->ttc.clk_rate_change_nb.next = NULL;
70504f31 DL	422
	423	err = clk_notifier_register(ttcce->ttc.clk,
	424	&ttcce->ttc.clk_rate_change_nb);
	425	if (err) {
e932900a	426	pr_warn("Unable to register clock notifier.\n");
70504f31 DL	427	return err;
	428	}
	429
c1dcc927	430	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
91dc985c	431
9e09dc5f MS	432	ttcce->ttc.base_addr = base;
9e09dc5f MS	433	ttcce->ce.name = "ttc_clockevent";
91dc985c	434	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
9e09dc5f	435	ttcce->ce.set_next_event = ttc_set_next_event;
5c0a4bbe VK	436	ttcce->ce.set_state_shutdown = ttc_shutdown;
	437	ttcce->ce.set_state_periodic = ttc_set_periodic;
	438	ttcce->ce.set_state_oneshot = ttc_shutdown;
	439	ttcce->ce.tick_resume = ttc_resume;
91dc985c JC	440	ttcce->ce.rating = 200;
91dc985c JC	441	ttcce->ce.irq = irq;
87e4ee75	442	ttcce->ce.cpumask = cpu_possible_mask;
91dc985c	443
e932900a MS	444	/*
	445	* Setup the clock event timer to be an interval timer which
	446	* is prescaled by 32 using the interval interrupt. Leave it
	447	* disabled for now.
	448	*/
87ab4361 MS	449	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
87ab4361 MS	450	writel_relaxed(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f	451	ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
87ab4361	452	writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
91dc985c	453
9e09dc5f	454	err = request_irq(irq, ttc_clock_event_interrupt,
38c30a84	455	IRQF_TIMER, ttcce->ce.name, ttcce);
70504f31	456	if (err) {
c5263bb8	457	kfree(ttcce);
70504f31	458	return err;
c5263bb8	459	}
91dc985c JC	460
91dc985c JC	461	clockevents_config_and_register(&ttcce->ce,
c1dcc927	462	ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
70504f31 DL	463
70504f31 DL	464	return 0;
91dc985c JC	465	}
91dc985c JC	466
b85a3ef4	467	/**
9e09dc5f	468	* ttc_timer_init - Initialize the timer
b85a3ef4 JL	469	*
	470	* Initializes the timer hardware and register the clock source and clock event
	471	* timers with Linux kernal timer framework
e932900a	472	*/
70504f31	473	static int __init ttc_timer_init(struct device_node *timer)
e932900a MS	474	{
	475	unsigned int irq;
	476	void __iomem *timer_baseaddr;
30e1e285	477	struct clk clk_cs, clk_ce;
c5263bb8	478	static int initialized;
70504f31	479	int clksel, ret;
4e2bec0c	480	u32 timer_width = 16;
c5263bb8 MS	481
c5263bb8 MS	482	if (initialized)
70504f31	483	return 0;
c5263bb8 MS	484
c5263bb8 MS	485	initialized = 1;
e932900a MS	486
	487	/*
	488	* Get the 1st Triple Timer Counter (TTC) block from the device tree
	489	* and use it. Note that the event timer uses the interrupt and it's the
	490	* 2nd TTC hence the irq_of_parse_and_map(,1)
	491	*/
	492	timer_baseaddr = of_iomap(timer, 0);
	493	if (!timer_baseaddr) {
	494	pr_err("ERROR: invalid timer base address\n");
70504f31	495	return -ENXIO;
e932900a MS	496	}
	497
	498	irq = irq_of_parse_and_map(timer, 1);
	499	if (irq <= 0) {
	500	pr_err("ERROR: invalid interrupt number\n");
70504f31	501	return -EINVAL;
e932900a MS	502	}
e932900a MS	503
4e2bec0c MS	504	of_property_read_u32(timer, "timer-width", &timer_width);
4e2bec0c MS	505
87ab4361	506	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
30e1e285 SB	507	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	508	clk_cs = of_clk_get(timer, clksel);
	509	if (IS_ERR(clk_cs)) {
	510	pr_err("ERROR: timer input clock not found\n");
70504f31	511	return PTR_ERR(clk_cs);
30e1e285 SB	512	}
30e1e285 SB	513
87ab4361	514	clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
30e1e285 SB	515	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	516	clk_ce = of_clk_get(timer, clksel);
	517	if (IS_ERR(clk_ce)) {
e932900a	518	pr_err("ERROR: timer input clock not found\n");
34c720a9	519	return PTR_ERR(clk_ce);
e932900a MS	520	}
e932900a MS	521
70504f31 DL	522	ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
	523	if (ret)
	524	return ret;
	525
	526	ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
	527	if (ret)
	528	return ret;
e932900a	529
2a4849d2	530	pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
70504f31 DL	531
70504f31 DL	532	return 0;
e932900a MS	533	}
e932900a MS	534
17273395	535	TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);