[linux-block.git] / drivers / clocksource / timer-cadence-ttc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * This file contains driver for the Cadence Triple Timer Counter Rev 06
 *
 *  Copyright (C) 2011-2013 Xilinx
 *
 * based on arch/mips/kernel/time.c timer driver
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>
#include <linux/module.h>
#include <linux/of_platform.h>

/*
 * This driver configures the 2 16/32-bit count-up timers as follows:
 *
 * T1: Timer 1, clocksource for generic timekeeping
 * T2: Timer 2, clockevent source for hrtimers
 * T3: Timer 3, <unused>
 *
 * The input frequency to the timer module for emulation is 2.5MHz which is
 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
 * the timers are clocked at 78.125KHz (12.8 us resolution).

 * The input frequency to the timer module in silicon is configurable and
 * obtained from device tree. The pre-scaler of 32 is used.
 */

/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
#define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
#define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
#define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
#define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */

#define TTC_CNT_CNTRL_DISABLE_MASK	0x1

#define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */
#define TTC_CLK_CNTRL_PSV_MASK		0x1e
#define TTC_CLK_CNTRL_PSV_SHIFT		1

/*
 * Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
#define CNT_CNTRL_RESET		(1 << 4)

#define MAX_F_ERR 50

/**
 * struct ttc_timer - This definition defines local timer structure
 *
 * @base_addr:	Base address of timer
 * @freq:	Timer input clock frequency
 * @clk:	Associated clock source
 * @clk_rate_change_nb	Notifier block for clock rate changes
 */
struct ttc_timer {
	void __iomem *base_addr;
	unsigned long freq;
	struct clk *clk;
	struct notifier_block clk_rate_change_nb;
};

#define to_ttc_timer(x) \
		container_of(x, struct ttc_timer, clk_rate_change_nb)

struct ttc_timer_clocksource {
	u32			scale_clk_ctrl_reg_old;
	u32			scale_clk_ctrl_reg_new;
	struct ttc_timer	ttc;
	struct clocksource	cs;
};

#define to_ttc_timer_clksrc(x) \
		container_of(x, struct ttc_timer_clocksource, cs)

struct ttc_timer_clockevent {
	struct ttc_timer		ttc;
	struct clock_event_device	ce;
};

#define to_ttc_timer_clkevent(x) \
		container_of(x, struct ttc_timer_clockevent, ce)

static void __iomem *ttc_sched_clock_val_reg;

/**
 * ttc_set_interval - Set the timer interval value
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
static void ttc_set_interval(struct ttc_timer *timer,
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);

	/*
	 * Reset the counter (0x10) so that it starts from 0, one-shot
	 * mode makes this needed for timing to be right.
	 */
	ctrl_reg |= CNT_CNTRL_RESET;
	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
}

/**
 * ttc_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the ttc_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
{
	struct ttc_timer_clockevent *ttce = dev_id;
	struct ttc_timer *timer = &ttce->ttc;

	/* Acknowledge the interrupt and call event handler */
	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);

	ttce->ce.event_handler(&ttce->ce);

	return IRQ_HANDLED;
}

/**
 * __ttc_clocksource_read - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
static u64 __ttc_clocksource_read(struct clocksource *cs)
{
	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;

	return (u64)readl_relaxed(timer->base_addr +
				TTC_COUNT_VAL_OFFSET);
}

static u64 notrace ttc_sched_clock_read(void)
{
	return readl_relaxed(ttc_sched_clock_val_reg);
}

/**
 * ttc_set_next_event - Sets the time interval for next event
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
static int ttc_set_next_event(unsigned long cycles,
					struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;

	ttc_set_interval(timer, cycles);
	return 0;
}

/**
 * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
 *
 * @evt:	Address of clock event instance
 **/
static int ttc_shutdown(struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
	u32 ctrl_reg;

	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	return 0;
}

static int ttc_set_periodic(struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;

	ttc_set_interval(timer,
			 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
	return 0;
}

static int ttc_resume(struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
	u32 ctrl_reg;

	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	return 0;
}

static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clocksource *ttccs = container_of(ttc,
			struct ttc_timer_clocksource, ttc);

	switch (event) {
	case PRE_RATE_CHANGE:
	{
		u32 psv;
		unsigned long factor, rate_low, rate_high;

		if (ndata->new_rate > ndata->old_rate) {
			factor = DIV_ROUND_CLOSEST(ndata->new_rate,
					ndata->old_rate);
			rate_low = ndata->old_rate;
			rate_high = ndata->new_rate;
		} else {
			factor = DIV_ROUND_CLOSEST(ndata->old_rate,
					ndata->new_rate);
			rate_low = ndata->new_rate;
			rate_high = ndata->old_rate;
		}

		if (!is_power_of_2(factor))
				return NOTIFY_BAD;

		if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
			return NOTIFY_BAD;

		factor = __ilog2_u32(factor);

		/*
		 * store timer clock ctrl register so we can restore it in case
		 * of an abort.
		 */
		ttccs->scale_clk_ctrl_reg_old =
			readl_relaxed(ttccs->ttc.base_addr +
			TTC_CLK_CNTRL_OFFSET);

		psv = (ttccs->scale_clk_ctrl_reg_old &
				TTC_CLK_CNTRL_PSV_MASK) >>
				TTC_CLK_CNTRL_PSV_SHIFT;
		if (ndata->new_rate < ndata->old_rate)
			psv -= factor;
		else
			psv += factor;

		/* prescaler within legal range? */
		if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
			return NOTIFY_BAD;

		ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
			~TTC_CLK_CNTRL_PSV_MASK;
		ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;


		/* scale down: adjust divider in post-change notification */
		if (ndata->new_rate < ndata->old_rate)
			return NOTIFY_DONE;

		/* scale up: adjust divider now - before frequency change */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		break;
	}
	case POST_RATE_CHANGE:
		/* scale up: pre-change notification did the adjustment */
		if (ndata->new_rate > ndata->old_rate)
			return NOTIFY_OK;

		/* scale down: adjust divider now - after frequency change */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		break;

	case ABORT_RATE_CHANGE:
		/* we have to undo the adjustment in case we scale up */
		if (ndata->new_rate < ndata->old_rate)
			return NOTIFY_OK;

		/* restore original register value */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		fallthrough;
	default:
		return NOTIFY_DONE;
	}

	return NOTIFY_DONE;
}

static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
					 u32 timer_width)
{
	struct ttc_timer_clocksource *ttccs;
	int err;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (!ttccs)
		return -ENOMEM;

	ttccs->ttc.clk = clk;

	err = clk_prepare_enable(ttccs->ttc.clk);
	if (err) {
		kfree(ttccs);
		return err;
	}

	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);

	ttccs->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clocksource_cb;
	ttccs->ttc.clk_rate_change_nb.next = NULL;

	err = clk_notifier_register(ttccs->ttc.clk,
				    &ttccs->ttc.clk_rate_change_nb);
	if (err)
		pr_warn("Unable to register clock notifier.\n");

	ttccs->ttc.base_addr = base;
	ttccs->cs.name = "ttc_clocksource";
	ttccs->cs.rating = 200;
	ttccs->cs.read = __ttc_clocksource_read;
	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	/*
	 * Setup the clock source counter to be an incrementing counter
	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
	 * it by 32 also. Let it start running now.
	 */
	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	writel_relaxed(CNT_CNTRL_RESET,
		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);

	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
	if (err) {
		kfree(ttccs);
		return err;
	}

	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
	sched_clock_register(ttc_sched_clock_read, timer_width,
			     ttccs->ttc.freq / PRESCALE);

	return 0;
}

static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clockevent *ttcce = container_of(ttc,
			struct ttc_timer_clockevent, ttc);

	switch (event) {
	case POST_RATE_CHANGE:
		/* update cached frequency */
		ttc->freq = ndata->new_rate;

		clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);

		fallthrough;
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

static int __init ttc_setup_clockevent(struct clk *clk,
				       void __iomem *base, u32 irq)
{
	struct ttc_timer_clockevent *ttcce;
	int err;

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (!ttcce)
		return -ENOMEM;

	ttcce->ttc.clk = clk;

	err = clk_prepare_enable(ttcce->ttc.clk);
	if (err)
		goto out_kfree;

	ttcce->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clockevent_cb;
	ttcce->ttc.clk_rate_change_nb.next = NULL;

	err = clk_notifier_register(ttcce->ttc.clk,
				    &ttcce->ttc.clk_rate_change_nb);
	if (err) {
		pr_warn("Unable to register clock notifier.\n");
		goto out_kfree;
	}

	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);

	ttcce->ttc.base_addr = base;
	ttcce->ce.name = "ttc_clockevent";
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ttcce->ce.set_next_event = ttc_set_next_event;
	ttcce->ce.set_state_shutdown = ttc_shutdown;
	ttcce->ce.set_state_periodic = ttc_set_periodic;
	ttcce->ce.set_state_oneshot = ttc_shutdown;
	ttcce->ce.tick_resume = ttc_resume;
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;
	ttcce->ce.cpumask = cpu_possible_mask;

	/*
	 * Setup the clock event timer to be an interval timer which
	 * is prescaled by 32 using the interval interrupt. Leave it
	 * disabled for now.
	 */
	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);

	err = request_irq(irq, ttc_clock_event_interrupt,
			  IRQF_TIMER, ttcce->ce.name, ttcce);
	if (err)
		goto out_kfree;

	clockevents_config_and_register(&ttcce->ce,
			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);

	return 0;

out_kfree:
	kfree(ttcce);
	return err;
}

static int __init ttc_timer_probe(struct platform_device *pdev)
{
	unsigned int irq;
	void __iomem *timer_baseaddr;
	struct clk *clk_cs, *clk_ce;
	static int initialized;
	int clksel, ret;
	u32 timer_width = 16;
	struct device_node *timer = pdev->dev.of_node;

	if (initialized)
		return 0;

	initialized = 1;

	/*
	 * Get the 1st Triple Timer Counter (TTC) block from the device tree
	 * and use it. Note that the event timer uses the interrupt and it's the
	 * 2nd TTC hence the irq_of_parse_and_map(,1)
	 */
	timer_baseaddr = of_iomap(timer, 0);
	if (!timer_baseaddr) {
		pr_err("ERROR: invalid timer base address\n");
		return -ENXIO;
	}

	irq = irq_of_parse_and_map(timer, 1);
	if (irq <= 0) {
		pr_err("ERROR: invalid interrupt number\n");
		return -EINVAL;
	}

	of_property_read_u32(timer, "timer-width", &timer_width);

	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_cs = of_clk_get(timer, clksel);
	if (IS_ERR(clk_cs)) {
		pr_err("ERROR: timer input clock not found\n");
		return PTR_ERR(clk_cs);
	}

	clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_ce = of_clk_get(timer, clksel);
	if (IS_ERR(clk_ce)) {
		pr_err("ERROR: timer input clock not found\n");
		return PTR_ERR(clk_ce);
	}

	ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
	if (ret)
		return ret;

	ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
	if (ret)
		return ret;

	pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);

	return 0;
}

static const struct of_device_id ttc_timer_of_match[] = {
	{.compatible = "cdns,ttc"},
	{},
};

MODULE_DEVICE_TABLE(of, ttc_timer_of_match);

static struct platform_driver ttc_timer_driver = {
	.driver = {
		.name	= "cdns_ttc_timer",
		.of_match_table = ttc_timer_of_match,
	},
};
builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
b85a3ef4	2	/*
9e09dc5f	3	* This file contains driver for the Cadence Triple Timer Counter Rev 06
b85a3ef4	4	*
e932900a	5	* Copyright (C) 2011-2013 Xilinx
b85a3ef4 JL	6	*
b85a3ef4 JL	7	* based on arch/mips/kernel/time.c timer driver
b85a3ef4 JL	8	*/
b85a3ef4 JL	9
e932900a	10	#include <linux/clk.h>
b85a3ef4	11	#include <linux/interrupt.h>
b85a3ef4	12	#include <linux/clockchips.h>
459fa246	13	#include <linux/clocksource.h>
91dc985c JC	14	#include <linux/of_address.h>
	15	#include <linux/of_irq.h>
	16	#include <linux/slab.h>
3d77b30e	17	#include <linux/sched_clock.h>
f5ac896b RV	18	#include <linux/module.h>
f5ac896b RV	19	#include <linux/of_platform.h>
b85a3ef4	20
e932900a	21	/*
4e2bec0c	22	* This driver configures the 2 16/32-bit count-up timers as follows:
e932900a MS	23	*
	24	* T1: Timer 1, clocksource for generic timekeeping
	25	* T2: Timer 2, clockevent source for hrtimers
	26	* T3: Timer 3, <unused>
	27	*
	28	* The input frequency to the timer module for emulation is 2.5MHz which is
	29	* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
	30	* the timers are clocked at 78.125KHz (12.8 us resolution).
	31
	32	* The input frequency to the timer module in silicon is configurable and
	33	* obtained from device tree. The pre-scaler of 32 is used.
	34	*/
	35
b85a3ef4 JL	36	/*
	37	* Timer Register Offset Definitions of Timer 1, Increment base address by 4
	38	* and use same offsets for Timer 2
	39	*/
9e09dc5f MS	40	#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
	41	#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
	42	#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
	43	#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
	44	#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
	45	#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
f184c5ca	46
9e09dc5f	47	#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
b85a3ef4	48
30e1e285	49	#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
b3e90722 SB	50	#define TTC_CLK_CNTRL_PSV_MASK 0x1e
b3e90722 SB	51	#define TTC_CLK_CNTRL_PSV_SHIFT 1
30e1e285	52
03377e58 SB	53	/*
03377e58 SB	54	* Setup the timers to use pre-scaling, using a fixed value for now that will
91dc985c JC	55	* work across most input frequency, but it may need to be more dynamic
	56	*/
	57	#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
	58	#define PRESCALE 2048 /* The exponent must match this */
	59	#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
	60	#define CLK_CNTRL_PRESCALE_EN 1
e932900a	61	#define CNT_CNTRL_RESET (1 << 4)
b85a3ef4	62
b3e90722 SB	63	#define MAX_F_ERR 50
b3e90722 SB	64
b85a3ef4	65	/**
9e09dc5f	66	* struct ttc_timer - This definition defines local timer structure
b85a3ef4 JL	67	*
b85a3ef4 JL	68	* @base_addr: Base address of timer
c1dcc927	69	* @freq: Timer input clock frequency
e932900a MS	70	* @clk: Associated clock source
	71	* @clk_rate_change_nb Notifier block for clock rate changes
	72	*/
9e09dc5f	73	struct ttc_timer {
e932900a	74	void __iomem *base_addr;
c1dcc927	75	unsigned long freq;
e932900a MS	76	struct clk *clk;
e932900a MS	77	struct notifier_block clk_rate_change_nb;
91dc985c JC	78	};
91dc985c JC	79
9e09dc5f MS	80	#define to_ttc_timer(x) \
9e09dc5f MS	81	container_of(x, struct ttc_timer, clk_rate_change_nb)
e932900a	82
9e09dc5f	83	struct ttc_timer_clocksource {
b3e90722 SB	84	u32 scale_clk_ctrl_reg_old;
b3e90722 SB	85	u32 scale_clk_ctrl_reg_new;
9e09dc5f	86	struct ttc_timer ttc;
91dc985c	87	struct clocksource cs;
b85a3ef4 JL	88	};
b85a3ef4 JL	89
9e09dc5f MS	90	#define to_ttc_timer_clksrc(x) \
9e09dc5f MS	91	container_of(x, struct ttc_timer_clocksource, cs)
91dc985c	92
9e09dc5f MS	93	struct ttc_timer_clockevent {
9e09dc5f MS	94	struct ttc_timer ttc;
91dc985c	95	struct clock_event_device ce;
91dc985c JC	96	};
91dc985c JC	97
9e09dc5f MS	98	#define to_ttc_timer_clkevent(x) \
9e09dc5f MS	99	container_of(x, struct ttc_timer_clockevent, ce)
b85a3ef4	100
3d77b30e SB	101	static void __iomem *ttc_sched_clock_val_reg;
3d77b30e SB	102
b85a3ef4	103	/**
9e09dc5f	104	* ttc_set_interval - Set the timer interval value
b85a3ef4 JL	105	*
	106	* @timer: Pointer to the timer instance
	107	* @cycles: Timer interval ticks
	108	**/
9e09dc5f	109	static void ttc_set_interval(struct ttc_timer *timer,
b85a3ef4 JL	110	unsigned long cycles)
	111	{
	112	u32 ctrl_reg;
	113
	114	/* Disable the counter, set the counter value and re-enable counter */
87ab4361	115	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
9e09dc5f	116	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
87ab4361	117	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4	118
87ab4361	119	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
b85a3ef4	120
03377e58 SB	121	/*
	122	* Reset the counter (0x10) so that it starts from 0, one-shot
	123	* mode makes this needed for timing to be right.
	124	*/
91dc985c	125	ctrl_reg \|= CNT_CNTRL_RESET;
9e09dc5f	126	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
87ab4361	127	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	128	}
	129
	130	/**
9e09dc5f	131	* ttc_clock_event_interrupt - Clock event timer interrupt handler
b85a3ef4 JL	132	*
b85a3ef4 JL	133	* @irq: IRQ number of the Timer
9e09dc5f	134	* @dev_id: void pointer to the ttc_timer instance
b85a3ef4 JL	135	*
	136	* returns: Always IRQ_HANDLED - success
	137	**/
9e09dc5f	138	static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
b85a3ef4	139	{
9e09dc5f MS	140	struct ttc_timer_clockevent *ttce = dev_id;
9e09dc5f MS	141	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	142
b85a3ef4 JL	143	/* Acknowledge the interrupt and call event handler */
87ab4361	144	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
b85a3ef4	145
9e09dc5f	146	ttce->ce.event_handler(&ttce->ce);
b85a3ef4 JL	147
	148	return IRQ_HANDLED;
	149	}
	150
b85a3ef4	151	/**
9e09dc5f	152	* __ttc_clocksource_read - Reads the timer counter register
b85a3ef4 JL	153	*
	154	* returns: Current timer counter register value
	155	**/
a5a1d1c2	156	static u64 __ttc_clocksource_read(struct clocksource *cs)
b85a3ef4	157	{
9e09dc5f	158	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
b85a3ef4	159
a5a1d1c2	160	return (u64)readl_relaxed(timer->base_addr +
9e09dc5f	161	TTC_COUNT_VAL_OFFSET);
b85a3ef4 JL	162	}
b85a3ef4 JL	163
dfded009	164	static u64 notrace ttc_sched_clock_read(void)
3d77b30e	165	{
87ab4361	166	return readl_relaxed(ttc_sched_clock_val_reg);
3d77b30e SB	167	}
3d77b30e SB	168
b85a3ef4	169	/**
9e09dc5f	170	* ttc_set_next_event - Sets the time interval for next event
b85a3ef4 JL	171	*
	172	* @cycles: Timer interval ticks
	173	* @evt: Address of clock event instance
	174	*
	175	* returns: Always 0 - success
	176	**/
9e09dc5f	177	static int ttc_set_next_event(unsigned long cycles,
b85a3ef4 JL	178	struct clock_event_device *evt)
b85a3ef4 JL	179	{
9e09dc5f MS	180	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	181	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4	182
9e09dc5f	183	ttc_set_interval(timer, cycles);
b85a3ef4 JL	184	return 0;
	185	}
	186
	187	/**
5c0a4bbe	188	* ttc_set_{shutdown\|oneshot\|periodic} - Sets the state of timer
b85a3ef4	189	*
b85a3ef4 JL	190	* @evt: Address of clock event instance
b85a3ef4 JL	191	**/
5c0a4bbe	192	static int ttc_shutdown(struct clock_event_device *evt)
b85a3ef4	193	{
9e09dc5f MS	194	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	195	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	196	u32 ctrl_reg;
b85a3ef4 JL	197
5c0a4bbe VK	198	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	199	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
	200	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	201	return 0;
	202	}
	203
	204	static int ttc_set_periodic(struct clock_event_device *evt)
	205	{
	206	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	207	struct ttc_timer *timer = &ttce->ttc;
	208
	209	ttc_set_interval(timer,
	210	DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
	211	return 0;
	212	}
	213
	214	static int ttc_resume(struct clock_event_device *evt)
	215	{
	216	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	217	struct ttc_timer *timer = &ttce->ttc;
	218	u32 ctrl_reg;
	219
	220	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	221	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	222	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	223	return 0;
b85a3ef4 JL	224	}
b85a3ef4 JL	225
9e09dc5f	226	static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
e932900a MS	227	unsigned long event, void *data)
	228	{
	229	struct clk_notifier_data *ndata = data;
9e09dc5f MS	230	struct ttc_timer *ttc = to_ttc_timer(nb);
	231	struct ttc_timer_clocksource *ttccs = container_of(ttc,
	232	struct ttc_timer_clocksource, ttc);
e932900a MS	233
e932900a MS	234	switch (event) {
b3e90722 SB	235	case PRE_RATE_CHANGE:
	236	{
	237	u32 psv;
	238	unsigned long factor, rate_low, rate_high;
	239
	240	if (ndata->new_rate > ndata->old_rate) {
	241	factor = DIV_ROUND_CLOSEST(ndata->new_rate,
	242	ndata->old_rate);
	243	rate_low = ndata->old_rate;
	244	rate_high = ndata->new_rate;
	245	} else {
	246	factor = DIV_ROUND_CLOSEST(ndata->old_rate,
	247	ndata->new_rate);
	248	rate_low = ndata->new_rate;
	249	rate_high = ndata->old_rate;
	250	}
	251
	252	if (!is_power_of_2(factor))
	253	return NOTIFY_BAD;
	254
	255	if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
	256	return NOTIFY_BAD;
	257
	258	factor = __ilog2_u32(factor);
	259
e932900a	260	/*
b3e90722 SB	261	* store timer clock ctrl register so we can restore it in case
b3e90722 SB	262	* of an abort.
e932900a	263	*/
b3e90722	264	ttccs->scale_clk_ctrl_reg_old =
87ab4361 MS	265	readl_relaxed(ttccs->ttc.base_addr +
87ab4361 MS	266	TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	267
	268	psv = (ttccs->scale_clk_ctrl_reg_old &
	269	TTC_CLK_CNTRL_PSV_MASK) >>
	270	TTC_CLK_CNTRL_PSV_SHIFT;
	271	if (ndata->new_rate < ndata->old_rate)
	272	psv -= factor;
	273	else
	274	psv += factor;
	275
	276	/* prescaler within legal range? */
	277	if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
	278	return NOTIFY_BAD;
	279
	280	ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
	281	~TTC_CLK_CNTRL_PSV_MASK;
	282	ttccs->scale_clk_ctrl_reg_new \|= psv << TTC_CLK_CNTRL_PSV_SHIFT;
	283
	284
	285	/* scale down: adjust divider in post-change notification */
	286	if (ndata->new_rate < ndata->old_rate)
	287	return NOTIFY_DONE;
	288
	289	/* scale up: adjust divider now - before frequency change */
87ab4361 MS	290	writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
87ab4361 MS	291	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	292	break;
	293	}
	294	case POST_RATE_CHANGE:
	295	/* scale up: pre-change notification did the adjustment */
	296	if (ndata->new_rate > ndata->old_rate)
	297	return NOTIFY_OK;
	298
	299	/* scale down: adjust divider now - after frequency change */
87ab4361 MS	300	writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
87ab4361 MS	301	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	302	break;
b3e90722 SB	303
e932900a	304	case ABORT_RATE_CHANGE:
b3e90722 SB	305	/* we have to undo the adjustment in case we scale up */
	306	if (ndata->new_rate < ndata->old_rate)
	307	return NOTIFY_OK;
	308
	309	/* restore original register value */
87ab4361 MS	310	writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
87ab4361 MS	311	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
df561f66	312	fallthrough;
e932900a MS	313	default:
	314	return NOTIFY_DONE;
	315	}
b3e90722 SB	316
b3e90722 SB	317	return NOTIFY_DONE;
e932900a MS	318	}
e932900a MS	319
70504f31	320	static int __init ttc_setup_clocksource(struct clk clk, void __iomem base,
4e2bec0c	321	u32 timer_width)
91dc985c	322	{
9e09dc5f	323	struct ttc_timer_clocksource *ttccs;
91dc985c	324	int err;
91dc985c JC	325
91dc985c JC	326	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
70504f31 DL	327	if (!ttccs)
70504f31 DL	328	return -ENOMEM;
91dc985c	329
9e09dc5f	330	ttccs->ttc.clk = clk;
91dc985c	331
9e09dc5f	332	err = clk_prepare_enable(ttccs->ttc.clk);
70504f31	333	if (err) {
c5263bb8	334	kfree(ttccs);
70504f31	335	return err;
c5263bb8	336	}
91dc985c	337
c1dcc927 SB	338	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
c1dcc927 SB	339
9e09dc5f MS	340	ttccs->ttc.clk_rate_change_nb.notifier_call =
	341	ttc_rate_change_clocksource_cb;
	342	ttccs->ttc.clk_rate_change_nb.next = NULL;
70504f31 DL	343
	344	err = clk_notifier_register(ttccs->ttc.clk,
	345	&ttccs->ttc.clk_rate_change_nb);
	346	if (err)
e932900a	347	pr_warn("Unable to register clock notifier.\n");
91dc985c	348
9e09dc5f MS	349	ttccs->ttc.base_addr = base;
9e09dc5f MS	350	ttccs->cs.name = "ttc_clocksource";
91dc985c	351	ttccs->cs.rating = 200;
9e09dc5f	352	ttccs->cs.read = __ttc_clocksource_read;
4e2bec0c	353	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
91dc985c JC	354	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
91dc985c JC	355
e932900a MS	356	/*
	357	* Setup the clock source counter to be an incrementing counter
	358	* with no interrupt and it rolls over at 0xFFFF. Pre-scale
	359	* it by 32 also. Let it start running now.
	360	*/
87ab4361 MS	361	writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
87ab4361 MS	362	writel_relaxed(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f	363	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
87ab4361	364	writel_relaxed(CNT_CNTRL_RESET,
9e09dc5f	365	ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
91dc985c	366
c1dcc927	367	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
70504f31	368	if (err) {
c5263bb8	369	kfree(ttccs);
70504f31	370	return err;
c5263bb8	371	}
3d77b30e SB	372
3d77b30e SB	373	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
4e2bec0c MS	374	sched_clock_register(ttc_sched_clock_read, timer_width,
4e2bec0c MS	375	ttccs->ttc.freq / PRESCALE);
70504f31 DL	376
70504f31 DL	377	return 0;
91dc985c JC	378	}
91dc985c JC	379
9e09dc5f	380	static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
e932900a MS	381	unsigned long event, void *data)
	382	{
	383	struct clk_notifier_data *ndata = data;
9e09dc5f MS	384	struct ttc_timer *ttc = to_ttc_timer(nb);
	385	struct ttc_timer_clockevent *ttcce = container_of(ttc,
	386	struct ttc_timer_clockevent, ttc);
e932900a MS	387
	388	switch (event) {
	389	case POST_RATE_CHANGE:
c1dcc927 SB	390	/* update cached frequency */
	391	ttc->freq = ndata->new_rate;
	392
5f0ba3b4 SB	393	clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
5f0ba3b4 SB	394
df561f66	395	fallthrough;
e932900a MS	396	case PRE_RATE_CHANGE:
	397	case ABORT_RATE_CHANGE:
	398	default:
	399	return NOTIFY_DONE;
	400	}
	401	}
	402
70504f31 DL	403	static int __init ttc_setup_clockevent(struct clk *clk,
70504f31 DL	404	void __iomem *base, u32 irq)
91dc985c	405	{
9e09dc5f	406	struct ttc_timer_clockevent *ttcce;
e932900a	407	int err;
91dc985c JC	408
91dc985c JC	409	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
70504f31 DL	410	if (!ttcce)
70504f31 DL	411	return -ENOMEM;
91dc985c	412
9e09dc5f	413	ttcce->ttc.clk = clk;
91dc985c	414
9e09dc5f	415	err = clk_prepare_enable(ttcce->ttc.clk);
eee422c4 YK	416	if (err)
eee422c4 YK	417	goto out_kfree;
91dc985c	418
9e09dc5f MS	419	ttcce->ttc.clk_rate_change_nb.notifier_call =
	420	ttc_rate_change_clockevent_cb;
	421	ttcce->ttc.clk_rate_change_nb.next = NULL;
70504f31 DL	422
	423	err = clk_notifier_register(ttcce->ttc.clk,
	424	&ttcce->ttc.clk_rate_change_nb);
	425	if (err) {
e932900a	426	pr_warn("Unable to register clock notifier.\n");
eee422c4	427	goto out_kfree;
70504f31 DL	428	}
70504f31 DL	429
c1dcc927	430	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
91dc985c	431
9e09dc5f MS	432	ttcce->ttc.base_addr = base;
9e09dc5f MS	433	ttcce->ce.name = "ttc_clockevent";
91dc985c	434	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
9e09dc5f	435	ttcce->ce.set_next_event = ttc_set_next_event;
5c0a4bbe VK	436	ttcce->ce.set_state_shutdown = ttc_shutdown;
	437	ttcce->ce.set_state_periodic = ttc_set_periodic;
	438	ttcce->ce.set_state_oneshot = ttc_shutdown;
	439	ttcce->ce.tick_resume = ttc_resume;
91dc985c JC	440	ttcce->ce.rating = 200;
91dc985c JC	441	ttcce->ce.irq = irq;
87e4ee75	442	ttcce->ce.cpumask = cpu_possible_mask;
91dc985c	443
e932900a MS	444	/*
	445	* Setup the clock event timer to be an interval timer which
	446	* is prescaled by 32 using the interval interrupt. Leave it
	447	* disabled for now.
	448	*/
87ab4361 MS	449	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
87ab4361 MS	450	writel_relaxed(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f	451	ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
87ab4361	452	writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
91dc985c	453
9e09dc5f	454	err = request_irq(irq, ttc_clock_event_interrupt,
38c30a84	455	IRQF_TIMER, ttcce->ce.name, ttcce);
eee422c4 YK	456	if (err)
eee422c4 YK	457	goto out_kfree;
91dc985c JC	458
91dc985c JC	459	clockevents_config_and_register(&ttcce->ce,
c1dcc927	460	ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
70504f31 DL	461
70504f31 DL	462	return 0;
eee422c4 YK	463
	464	out_kfree:
	465	kfree(ttcce);
	466	return err;
91dc985c JC	467	}
91dc985c JC	468
f5ac896b	469	static int __init ttc_timer_probe(struct platform_device *pdev)
e932900a MS	470	{
	471	unsigned int irq;
	472	void __iomem *timer_baseaddr;
30e1e285	473	struct clk clk_cs, clk_ce;
c5263bb8	474	static int initialized;
70504f31	475	int clksel, ret;
4e2bec0c	476	u32 timer_width = 16;
f5ac896b	477	struct device_node *timer = pdev->dev.of_node;
c5263bb8 MS	478
c5263bb8 MS	479	if (initialized)
70504f31	480	return 0;
c5263bb8 MS	481
c5263bb8 MS	482	initialized = 1;
e932900a MS	483
	484	/*
	485	* Get the 1st Triple Timer Counter (TTC) block from the device tree
	486	* and use it. Note that the event timer uses the interrupt and it's the
	487	* 2nd TTC hence the irq_of_parse_and_map(,1)
	488	*/
	489	timer_baseaddr = of_iomap(timer, 0);
	490	if (!timer_baseaddr) {
	491	pr_err("ERROR: invalid timer base address\n");
70504f31	492	return -ENXIO;
e932900a MS	493	}
	494
	495	irq = irq_of_parse_and_map(timer, 1);
	496	if (irq <= 0) {
	497	pr_err("ERROR: invalid interrupt number\n");
70504f31	498	return -EINVAL;
e932900a MS	499	}
e932900a MS	500
4e2bec0c MS	501	of_property_read_u32(timer, "timer-width", &timer_width);
4e2bec0c MS	502
87ab4361	503	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
30e1e285 SB	504	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	505	clk_cs = of_clk_get(timer, clksel);
	506	if (IS_ERR(clk_cs)) {
	507	pr_err("ERROR: timer input clock not found\n");
70504f31	508	return PTR_ERR(clk_cs);
30e1e285 SB	509	}
30e1e285 SB	510
87ab4361	511	clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
30e1e285 SB	512	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	513	clk_ce = of_clk_get(timer, clksel);
	514	if (IS_ERR(clk_ce)) {
e932900a	515	pr_err("ERROR: timer input clock not found\n");
34c720a9	516	return PTR_ERR(clk_ce);
e932900a MS	517	}
e932900a MS	518
70504f31 DL	519	ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
	520	if (ret)
	521	return ret;
	522
	523	ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
	524	if (ret)
	525	return ret;
e932900a	526
2a4849d2	527	pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
70504f31 DL	528
70504f31 DL	529	return 0;
e932900a MS	530	}
e932900a MS	531
f5ac896b RV	532	static const struct of_device_id ttc_timer_of_match[] = {
	533	{.compatible = "cdns,ttc"},
	534	{},
	535	};
	536
	537	MODULE_DEVICE_TABLE(of, ttc_timer_of_match);
	538
	539	static struct platform_driver ttc_timer_driver = {
	540	.driver = {
	541	.name = "cdns_ttc_timer",
	542	.of_match_table = ttc_timer_of_match,
	543	},
	544	};
	545	builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);