[linux-2.6-block.git] / drivers / clocksource / timer-atmel-tcb.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/syscore_ops.h>
#include <soc/at91/atmel_tcb.h>


/*
 * We're configured to use a specific TC block, one that's not hooked
 * up to external hardware, to provide a time solution:
 *
 *   - Two channels combine to create a free-running 32 bit counter
 *     with a base rate of 5+ MHz, packaged as a clocksource (with
 *     resolution better than 200 nsec).
 *   - Some chips support 32 bit counter. A single channel is used for
 *     this 32 bit free-running counter. the second channel is not used.
 *
 *   - The third channel may be used to provide a 16-bit clockevent
 *     source, used in either periodic or oneshot mode.  This runs
 *     at 32 KiHZ, and can handle delays of up to two seconds.
 *
 * REVISIT behavior during system suspend states... we should disable
 * all clocks and save the power.  Easily done for clockevent devices,
 * but clocksources won't necessarily get the needed notifications.
 * For deeper system sleep states, this will be mandatory...
 */

static void __iomem *tcaddr;
static struct
{
	u32 cmr;
	u32 imr;
	u32 rc;
	bool clken;
} tcb_cache[3];
static u32 bmr_cache;

static u64 tc_get_cycles(struct clocksource *cs)
{
	unsigned long	flags;
	u32		lower, upper;

	raw_local_irq_save(flags);
	do {
		upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
		lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));

	raw_local_irq_restore(flags);
	return (upper << 16) | lower;
}

static u64 tc_get_cycles32(struct clocksource *cs)
{
	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
}

static void tc_clksrc_suspend(struct clocksource *cs)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
		tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
		tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
		tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
		tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
					ATMEL_TC_CLKSTA);
	}

	bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
}

static void tc_clksrc_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
		/* Restore registers for the channel, RA and RB are not used  */
		writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
		writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
		writel(0, tcaddr + ATMEL_TC_REG(i, RA));
		writel(0, tcaddr + ATMEL_TC_REG(i, RB));
		/* Disable all the interrupts */
		writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
		/* Reenable interrupts that were enabled before suspending */
		writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
		/* Start the clock if it was used */
		if (tcb_cache[i].clken)
			writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
	}

	/* Dual channel, chain channels */
	writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
	/* Finally, trigger all the channels*/
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static struct clocksource clksrc = {
	.rating         = 200,
	.read           = tc_get_cycles,
	.mask           = CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.suspend	= tc_clksrc_suspend,
	.resume		= tc_clksrc_resume,
};

static u64 notrace tc_sched_clock_read(void)
{
	return tc_get_cycles(&clksrc);
}

static u64 notrace tc_sched_clock_read32(void)
{
	return tc_get_cycles32(&clksrc);
}

#ifdef CONFIG_GENERIC_CLOCKEVENTS

struct tc_clkevt_device {
	struct clock_event_device	clkevt;
	struct clk			*clk;
	void __iomem			*regs;
};

static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
{
	return container_of(clkevt, struct tc_clkevt_device, clkevt);
}

/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
 * because using one of the divided clocks would usually mean the
 * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
 *
 * A divided clock could be good for high resolution timers, since
 * 30.5 usec resolution can seem "low".
 */
static u32 timer_clock;

static int tc_shutdown(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	writel(0xff, regs + ATMEL_TC_REG(2, IDR));
	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
	if (!clockevent_state_detached(d))
		clk_disable(tcd->clk);

	return 0;
}

static int tc_set_oneshot(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
		tc_shutdown(d);

	clk_enable(tcd->clk);

	/* slow clock, count up to RC, then irq and stop */
	writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
		     ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));

	/* set_next_event() configures and starts the timer */
	return 0;
}

static int tc_set_periodic(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
		tc_shutdown(d);

	/* By not making the gentime core emulate periodic mode on top
	 * of oneshot, we get lower overhead and improved accuracy.
	 */
	clk_enable(tcd->clk);

	/* slow clock, count up to RC, then irq and restart */
	writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
		     regs + ATMEL_TC_REG(2, CMR));
	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));

	/* Enable clock and interrupts on RC compare */
	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));

	/* go go gadget! */
	writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
		     ATMEL_TC_REG(2, CCR));
	return 0;
}

static int tc_next_event(unsigned long delta, struct clock_event_device *d)
{
	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));

	/* go go gadget! */
	writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
			tcaddr + ATMEL_TC_REG(2, CCR));
	return 0;
}

static struct tc_clkevt_device clkevt = {
	.clkevt	= {
		.features		= CLOCK_EVT_FEAT_PERIODIC |
					  CLOCK_EVT_FEAT_ONESHOT,
		/* Should be lower than at91rm9200's system timer */
		.rating			= 125,
		.set_next_event		= tc_next_event,
		.set_state_shutdown	= tc_shutdown,
		.set_state_periodic	= tc_set_periodic,
		.set_state_oneshot	= tc_set_oneshot,
	},
};

static irqreturn_t ch2_irq(int irq, void *handle)
{
	struct tc_clkevt_device	*dev = handle;
	unsigned int		sr;

	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
	if (sr & ATMEL_TC_CPCS) {
		dev->clkevt.event_handler(&dev->clkevt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
{
	int ret;
	struct clk *t2_clk = tc->clk[2];
	int irq = tc->irq[2];

	ret = clk_prepare_enable(tc->slow_clk);
	if (ret)
		return ret;

	/* try to enable t2 clk to avoid future errors in mode change */
	ret = clk_prepare_enable(t2_clk);
	if (ret) {
		clk_disable_unprepare(tc->slow_clk);
		return ret;
	}

	clk_disable(t2_clk);

	clkevt.regs = tc->regs;
	clkevt.clk = t2_clk;

	timer_clock = clk32k_divisor_idx;

	clkevt.clkevt.cpumask = cpumask_of(0);

	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
	if (ret) {
		clk_unprepare(t2_clk);
		clk_disable_unprepare(tc->slow_clk);
		return ret;
	}

	clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);

	return ret;
}

#else /* !CONFIG_GENERIC_CLOCKEVENTS */

static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
{
	/* NOTHING */
	return 0;
}

#endif

static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
{
	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
	writel(mck_divisor_idx			/* likely divide-by-8 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP		/* free-run */
			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
			tcaddr + ATMEL_TC_REG(0, CMR));
	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));

	/* channel 1:  waveform mode, input TIOA0 */
	writel(ATMEL_TC_XC1			/* input: TIOA0 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP,		/* free-run */
			tcaddr + ATMEL_TC_REG(1, CMR));
	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));

	/* chain channel 0 to channel 1*/
	writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
	/* then reset all the timers */
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
{
	/* channel 0:  waveform mode, input mclk/8 */
	writel(mck_divisor_idx			/* likely divide-by-8 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP,		/* free-run */
			tcaddr + ATMEL_TC_REG(0, CMR));
	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));

	/* then reset all the timers */
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };

static const struct of_device_id atmel_tcb_of_match[] = {
	{ .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
	{ .compatible = "atmel,at91sam9x5-tcb", .data = (void *)32, },
	{ /* sentinel */ }
};

static int __init tcb_clksrc_init(struct device_node *node)
{
	struct atmel_tc tc;
	struct clk *t0_clk;
	const struct of_device_id *match;
	u64 (*tc_sched_clock)(void);
	u32 rate, divided_rate = 0;
	int best_divisor_idx = -1;
	int clk32k_divisor_idx = -1;
	int bits;
	int i;
	int ret;

	/* Protect against multiple calls */
	if (tcaddr)
		return 0;

	tc.regs = of_iomap(node->parent, 0);
	if (!tc.regs)
		return -ENXIO;

	t0_clk = of_clk_get_by_name(node->parent, "t0_clk");
	if (IS_ERR(t0_clk))
		return PTR_ERR(t0_clk);

	tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
	if (IS_ERR(tc.slow_clk))
		return PTR_ERR(tc.slow_clk);

	tc.clk[0] = t0_clk;
	tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");
	if (IS_ERR(tc.clk[1]))
		tc.clk[1] = t0_clk;
	tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");
	if (IS_ERR(tc.clk[2]))
		tc.clk[2] = t0_clk;

	tc.irq[2] = of_irq_get(node->parent, 2);
	if (tc.irq[2] <= 0) {
		tc.irq[2] = of_irq_get(node->parent, 0);
		if (tc.irq[2] <= 0)
			return -EINVAL;
	}

	match = of_match_node(atmel_tcb_of_match, node->parent);
	bits = (uintptr_t)match->data;

	for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
		writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));

	ret = clk_prepare_enable(t0_clk);
	if (ret) {
		pr_debug("can't enable T0 clk\n");
		return ret;
	}

	/* How fast will we be counting?  Pick something over 5 MHz.  */
	rate = (u32) clk_get_rate(t0_clk);
	for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
		unsigned divisor = atmel_tcb_divisors[i];
		unsigned tmp;

		/* remember 32 KiHz clock for later */
		if (!divisor) {
			clk32k_divisor_idx = i;
			continue;
		}

		tmp = rate / divisor;
		pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
		if (best_divisor_idx > 0) {
			if (tmp < 5 * 1000 * 1000)
				continue;
		}
		divided_rate = tmp;
		best_divisor_idx = i;
	}

	clksrc.name = kbasename(node->parent->full_name);
	clkevt.clkevt.name = kbasename(node->parent->full_name);
	pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
			((divided_rate % 1000000) + 500) / 1000);

	tcaddr = tc.regs;

	if (bits == 32) {
		/* use apropriate function to read 32 bit counter */
		clksrc.read = tc_get_cycles32;
		/* setup ony channel 0 */
		tcb_setup_single_chan(&tc, best_divisor_idx);
		tc_sched_clock = tc_sched_clock_read32;
	} else {
		/* we have three clocks no matter what the
		 * underlying platform supports.
		 */
		ret = clk_prepare_enable(tc.clk[1]);
		if (ret) {
			pr_debug("can't enable T1 clk\n");
			goto err_disable_t0;
		}
		/* setup both channel 0 & 1 */
		tcb_setup_dual_chan(&tc, best_divisor_idx);
		tc_sched_clock = tc_sched_clock_read;
	}

	/* and away we go! */
	ret = clocksource_register_hz(&clksrc, divided_rate);
	if (ret)
		goto err_disable_t1;

	/* channel 2:  periodic and oneshot timer support */
	ret = setup_clkevents(&tc, clk32k_divisor_idx);
	if (ret)
		goto err_unregister_clksrc;

	sched_clock_register(tc_sched_clock, 32, divided_rate);

	return 0;

err_unregister_clksrc:
	clocksource_unregister(&clksrc);

err_disable_t1:
	if (bits != 32)
		clk_disable_unprepare(tc.clk[1]);

err_disable_t0:
	clk_disable_unprepare(t0_clk);

	tcaddr = NULL;

	return ret;
}
TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
4d243f92 DB	2	#include <linux/init.h>
	3	#include <linux/clocksource.h>
	4	#include <linux/clockchips.h>
	5	#include <linux/interrupt.h>
	6	#include <linux/irq.h>
	7
	8	#include <linux/clk.h>
	9	#include <linux/err.h>
	10	#include <linux/ioport.h>
	11	#include <linux/io.h>
86232bfd AB	12	#include <linux/of_address.h>
86232bfd AB	13	#include <linux/of_irq.h>
f712a1e8	14	#include <linux/sched_clock.h>
2a515e5d	15	#include <linux/syscore_ops.h>
c2c9136b	16	#include <soc/at91/atmel_tcb.h>
4d243f92 DB	17
	18
	19	/*
	20	* We're configured to use a specific TC block, one that's not hooked
	21	* up to external hardware, to provide a time solution:
	22	*
	23	* - Two channels combine to create a free-running 32 bit counter
	24	* with a base rate of 5+ MHz, packaged as a clocksource (with
	25	* resolution better than 200 nsec).
8e315a7b NF	26	* - Some chips support 32 bit counter. A single channel is used for
8e315a7b NF	27	* this 32 bit free-running counter. the second channel is not used.
4d243f92 DB	28	*
	29	* - The third channel may be used to provide a 16-bit clockevent
	30	* source, used in either periodic or oneshot mode. This runs
	31	* at 32 KiHZ, and can handle delays of up to two seconds.
	32	*
4d243f92 DB	33	* REVISIT behavior during system suspend states... we should disable
	34	* all clocks and save the power. Easily done for clockevent devices,
	35	* but clocksources won't necessarily get the needed notifications.
	36	* For deeper system sleep states, this will be mandatory...
	37	*/
	38
	39	static void __iomem *tcaddr;
2a515e5d AB	40	static struct
	41	{
	42	u32 cmr;
	43	u32 imr;
	44	u32 rc;
	45	bool clken;
	46	} tcb_cache[3];
	47	static u32 bmr_cache;
4d243f92	48
a5a1d1c2	49	static u64 tc_get_cycles(struct clocksource *cs)
4d243f92 DB	50	{
	51	unsigned long flags;
	52	u32 lower, upper;
	53
	54	raw_local_irq_save(flags);
	55	do {
6ec8be25 AB	56	upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
	57	lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
	58	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));
4d243f92 DB	59
	60	raw_local_irq_restore(flags);
	61	return (upper << 16) \| lower;
	62	}
	63
7b9f1d16 DE	64	static u64 tc_get_cycles32(struct clocksource *cs)
7b9f1d16 DE	65	{
6ec8be25	66	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
7b9f1d16 DE	67	}
7b9f1d16 DE	68
7ebe6810	69	static void tc_clksrc_suspend(struct clocksource *cs)
2a515e5d AB	70	{
	71	int i;
	72
	73	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
	74	tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
	75	tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
	76	tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
	77	tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
	78	ATMEL_TC_CLKSTA);
	79	}
	80
	81	bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
	82	}
	83
7ebe6810	84	static void tc_clksrc_resume(struct clocksource *cs)
2a515e5d AB	85	{
	86	int i;
	87
	88	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
	89	/* Restore registers for the channel, RA and RB are not used */
	90	writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
	91	writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
	92	writel(0, tcaddr + ATMEL_TC_REG(i, RA));
	93	writel(0, tcaddr + ATMEL_TC_REG(i, RB));
	94	/* Disable all the interrupts */
	95	writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
	96	/* Reenable interrupts that were enabled before suspending */
	97	writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
	98	/* Start the clock if it was used */
	99	if (tcb_cache[i].clken)
	100	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
	101	}
	102
	103	/* Dual channel, chain channels */
	104	writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
	105	/* Finally, trigger all the channels*/
	106	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
	107	}
	108
4d243f92	109	static struct clocksource clksrc = {
4d243f92 DB	110	.rating = 200,
	111	.read = tc_get_cycles,
	112	.mask = CLOCKSOURCE_MASK(32),
4d243f92	113	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
2a515e5d AB	114	.suspend = tc_clksrc_suspend,
2a515e5d AB	115	.resume = tc_clksrc_resume,
4d243f92 DB	116	};
4d243f92 DB	117
f712a1e8 AB	118	static u64 notrace tc_sched_clock_read(void)
	119	{
	120	return tc_get_cycles(&clksrc);
	121	}
	122
	123	static u64 notrace tc_sched_clock_read32(void)
	124	{
	125	return tc_get_cycles32(&clksrc);
	126	}
	127
4d243f92 DB	128	#ifdef CONFIG_GENERIC_CLOCKEVENTS
	129
	130	struct tc_clkevt_device {
	131	struct clock_event_device clkevt;
	132	struct clk *clk;
	133	void __iomem *regs;
	134	};
	135
	136	static struct tc_clkevt_device to_tc_clkevt(struct clock_event_device clkevt)
	137	{
	138	return container_of(clkevt, struct tc_clkevt_device, clkevt);
	139	}
	140
	141	/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
	142	* because using one of the divided clocks would usually mean the
	143	* tick rate can never be less than several dozen Hz (vs 0.5 Hz).
	144	*
	145	* A divided clock could be good for high resolution timers, since
	146	* 30.5 usec resolution can seem "low".
	147	*/
	148	static u32 timer_clock;
	149
cf4541c1	150	static int tc_shutdown(struct clock_event_device *d)
4d243f92 DB	151	{
	152	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	153	void __iomem *regs = tcd->regs;
	154
6ec8be25 AB	155	writel(0xff, regs + ATMEL_TC_REG(2, IDR));
6ec8be25 AB	156	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
f02b4b72 AB	157	if (!clockevent_state_detached(d))
f02b4b72 AB	158	clk_disable(tcd->clk);
4d243f92	159
cf4541c1 VK	160	return 0;
cf4541c1 VK	161	}
4d243f92	162
cf4541c1 VK	163	static int tc_set_oneshot(struct clock_event_device *d)
	164	{
	165	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	166	void __iomem *regs = tcd->regs;
4d243f92	167
cf4541c1 VK	168	if (clockevent_state_oneshot(d) \|\| clockevent_state_periodic(d))
cf4541c1 VK	169	tc_shutdown(d);
4d243f92	170
cf4541c1	171	clk_enable(tcd->clk);
4d243f92	172
cf4541c1	173	/* slow clock, count up to RC, then irq and stop */
6ec8be25	174	writel(timer_clock \| ATMEL_TC_CPCSTOP \| ATMEL_TC_WAVE \|
cf4541c1	175	ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
6ec8be25	176	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
4d243f92	177
cf4541c1 VK	178	/* set_next_event() configures and starts the timer */
	179	return 0;
	180	}
4d243f92	181
cf4541c1 VK	182	static int tc_set_periodic(struct clock_event_device *d)
	183	{
	184	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	185	void __iomem *regs = tcd->regs;
4d243f92	186
cf4541c1 VK	187	if (clockevent_state_oneshot(d) \|\| clockevent_state_periodic(d))
cf4541c1 VK	188	tc_shutdown(d);
4d243f92	189
cf4541c1 VK	190	/* By not making the gentime core emulate periodic mode on top
	191	* of oneshot, we get lower overhead and improved accuracy.
	192	*/
	193	clk_enable(tcd->clk);
	194
	195	/* slow clock, count up to RC, then irq and restart */
6ec8be25	196	writel(timer_clock \| ATMEL_TC_WAVE \| ATMEL_TC_WAVESEL_UP_AUTO,
cf4541c1	197	regs + ATMEL_TC_REG(2, CMR));
6ec8be25	198	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
cf4541c1 VK	199
cf4541c1 VK	200	/* Enable clock and interrupts on RC compare */
6ec8be25	201	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
cf4541c1 VK	202
cf4541c1 VK	203	/* go go gadget! */
6ec8be25	204	writel(ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG, regs +
cf4541c1 VK	205	ATMEL_TC_REG(2, CCR));
cf4541c1 VK	206	return 0;
4d243f92 DB	207	}
	208
	209	static int tc_next_event(unsigned long delta, struct clock_event_device *d)
	210	{
6ec8be25	211	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
4d243f92 DB	212
4d243f92 DB	213	/* go go gadget! */
6ec8be25	214	writel_relaxed(ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG,
4d243f92 DB	215	tcaddr + ATMEL_TC_REG(2, CCR));
	216	return 0;
	217	}
	218
	219	static struct tc_clkevt_device clkevt = {
	220	.clkevt = {
cf4541c1 VK	221	.features = CLOCK_EVT_FEAT_PERIODIC \|
cf4541c1 VK	222	CLOCK_EVT_FEAT_ONESHOT,
4d243f92	223	/* Should be lower than at91rm9200's system timer */
cf4541c1 VK	224	.rating = 125,
	225	.set_next_event = tc_next_event,
	226	.set_state_shutdown = tc_shutdown,
	227	.set_state_periodic = tc_set_periodic,
	228	.set_state_oneshot = tc_set_oneshot,
4d243f92 DB	229	},
	230	};
	231
	232	static irqreturn_t ch2_irq(int irq, void *handle)
	233	{
	234	struct tc_clkevt_device *dev = handle;
	235	unsigned int sr;
	236
6ec8be25	237	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
4d243f92 DB	238	if (sr & ATMEL_TC_CPCS) {
	239	dev->clkevt.event_handler(&dev->clkevt);
	240	return IRQ_HANDLED;
	241	}
	242
	243	return IRQ_NONE;
	244	}
	245
5b3c11da	246	static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
4d243f92	247	{
5b3c11da	248	int ret;
4d243f92 DB	249	struct clk *t2_clk = tc->clk[2];
	250	int irq = tc->irq[2];
	251
7d8d05d1 BB	252	ret = clk_prepare_enable(tc->slow_clk);
	253	if (ret)
	254	return ret;
	255
5b3c11da BB	256	/* try to enable t2 clk to avoid future errors in mode change */
5b3c11da BB	257	ret = clk_prepare_enable(t2_clk);
7d8d05d1 BB	258	if (ret) {
7d8d05d1 BB	259	clk_disable_unprepare(tc->slow_clk);
5b3c11da	260	return ret;
7d8d05d1 BB	261	}
7d8d05d1 BB	262
acbf6d21	263	clk_disable(t2_clk);
5b3c11da	264
4d243f92 DB	265	clkevt.regs = tc->regs;
4d243f92 DB	266	clkevt.clk = t2_clk;
4d243f92 DB	267
	268	timer_clock = clk32k_divisor_idx;
	269
320ab2b0	270	clkevt.clkevt.cpumask = cpumask_of(0);
4d243f92	271
d07a1ecd GP	272	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
d07a1ecd GP	273	if (ret) {
eed9fb9d	274	clk_unprepare(t2_clk);
7d8d05d1	275	clk_disable_unprepare(tc->slow_clk);
5b3c11da	276	return ret;
d07a1ecd	277	}
5b3c11da	278
77cc982f	279	clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
1817dc03	280
5b3c11da	281	return ret;
4d243f92 DB	282	}
	283
	284	#else /* !CONFIG_GENERIC_CLOCKEVENTS */
	285
5b3c11da	286	static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
4d243f92 DB	287	{
4d243f92 DB	288	/* NOTHING */
5b3c11da	289	return 0;
4d243f92 DB	290	}
	291
	292	#endif
	293
8e315a7b NF	294	static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
	295	{
	296	/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
6ec8be25	297	writel(mck_divisor_idx /* likely divide-by-8 */
8e315a7b NF	298	\| ATMEL_TC_WAVE
	299	\| ATMEL_TC_WAVESEL_UP /* free-run */
	300	\| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
	301	\| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
	302	tcaddr + ATMEL_TC_REG(0, CMR));
6ec8be25 AB	303	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
	304	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
	305	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
	306	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
8e315a7b NF	307
8e315a7b NF	308	/* channel 1: waveform mode, input TIOA0 */
6ec8be25	309	writel(ATMEL_TC_XC1 /* input: TIOA0 */
8e315a7b NF	310	\| ATMEL_TC_WAVE
	311	\| ATMEL_TC_WAVESEL_UP, /* free-run */
	312	tcaddr + ATMEL_TC_REG(1, CMR));
6ec8be25 AB	313	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
6ec8be25 AB	314	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
8e315a7b NF	315
8e315a7b NF	316	/* chain channel 0 to channel 1*/
6ec8be25	317	writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
8e315a7b	318	/* then reset all the timers */
6ec8be25	319	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
8e315a7b NF	320	}
	321
	322	static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
	323	{
	324	/* channel 0: waveform mode, input mclk/8 */
6ec8be25	325	writel(mck_divisor_idx /* likely divide-by-8 */
8e315a7b NF	326	\| ATMEL_TC_WAVE
	327	\| ATMEL_TC_WAVESEL_UP, /* free-run */
	328	tcaddr + ATMEL_TC_REG(0, CMR));
6ec8be25 AB	329	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
6ec8be25 AB	330	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
8e315a7b NF	331
8e315a7b NF	332	/* then reset all the timers */
6ec8be25	333	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
8e315a7b NF	334	}
8e315a7b NF	335
86232bfd AB	336	static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };
	337
	338	static const struct of_device_id atmel_tcb_of_match[] = {
	339	{ .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
	340	{ .compatible = "atmel,at91sam9x5-tcb", .data = (void *)32, },
	341	{ /* sentinel */ }
	342	};
4d243f92	343
86232bfd AB	344	static int __init tcb_clksrc_init(struct device_node *node)
	345	{
	346	struct atmel_tc tc;
3ee08aea	347	struct clk *t0_clk;
86232bfd	348	const struct of_device_id *match;
f712a1e8	349	u64 (*tc_sched_clock)(void);
4d243f92 DB	350	u32 rate, divided_rate = 0;
	351	int best_divisor_idx = -1;
	352	int clk32k_divisor_idx = -1;
86232bfd	353	int bits;
4d243f92	354	int i;
0e746ec5	355	int ret;
4d243f92	356
86232bfd AB	357	/* Protect against multiple calls */
	358	if (tcaddr)
	359	return 0;
	360
	361	tc.regs = of_iomap(node->parent, 0);
	362	if (!tc.regs)
	363	return -ENXIO;
	364
	365	t0_clk = of_clk_get_by_name(node->parent, "t0_clk");
	366	if (IS_ERR(t0_clk))
	367	return PTR_ERR(t0_clk);
	368
	369	tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
	370	if (IS_ERR(tc.slow_clk))
	371	return PTR_ERR(tc.slow_clk);
	372
	373	tc.clk[0] = t0_clk;
	374	tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");
	375	if (IS_ERR(tc.clk[1]))
	376	tc.clk[1] = t0_clk;
	377	tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");
	378	if (IS_ERR(tc.clk[2]))
	379	tc.clk[2] = t0_clk;
	380
	381	tc.irq[2] = of_irq_get(node->parent, 2);
	382	if (tc.irq[2] <= 0) {
	383	tc.irq[2] = of_irq_get(node->parent, 0);
	384	if (tc.irq[2] <= 0)
	385	return -EINVAL;
4d243f92	386	}
4d243f92	387
86232bfd AB	388	match = of_match_node(atmel_tcb_of_match, node->parent);
	389	bits = (uintptr_t)match->data;
	390
	391	for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
	392	writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
	393
0e746ec5 BB	394	ret = clk_prepare_enable(t0_clk);
	395	if (ret) {
	396	pr_debug("can't enable T0 clk\n");
86232bfd	397	return ret;
0e746ec5	398	}
4d243f92 DB	399
	400	/* How fast will we be counting? Pick something over 5 MHz. */
	401	rate = (u32) clk_get_rate(t0_clk);
86232bfd AB	402	for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
86232bfd AB	403	unsigned divisor = atmel_tcb_divisors[i];
4d243f92 DB	404	unsigned tmp;
	405
	406	/* remember 32 KiHz clock for later */
	407	if (!divisor) {
	408	clk32k_divisor_idx = i;
	409	continue;
	410	}
	411
	412	tmp = rate / divisor;
	413	pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
	414	if (best_divisor_idx > 0) {
	415	if (tmp < 5 * 1000 * 1000)
	416	continue;
	417	}
	418	divided_rate = tmp;
	419	best_divisor_idx = i;
	420	}
	421
86232bfd AB	422	clksrc.name = kbasename(node->parent->full_name);
	423	clkevt.clkevt.name = kbasename(node->parent->full_name);
	424	pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
542f8246	425	((divided_rate % 1000000) + 500) / 1000);
4d243f92	426
86232bfd AB	427	tcaddr = tc.regs;
	428
	429	if (bits == 32) {
8e315a7b NF	430	/* use apropriate function to read 32 bit counter */
	431	clksrc.read = tc_get_cycles32;
	432	/* setup ony channel 0 */
86232bfd	433	tcb_setup_single_chan(&tc, best_divisor_idx);
f712a1e8	434	tc_sched_clock = tc_sched_clock_read32;
8e315a7b	435	} else {
86232bfd	436	/* we have three clocks no matter what the
8e315a7b NF	437	* underlying platform supports.
8e315a7b NF	438	*/
86232bfd	439	ret = clk_prepare_enable(tc.clk[1]);
0e746ec5 BB	440	if (ret) {
	441	pr_debug("can't enable T1 clk\n");
	442	goto err_disable_t0;
	443	}
8e315a7b	444	/* setup both channel 0 & 1 */
86232bfd	445	tcb_setup_dual_chan(&tc, best_divisor_idx);
f712a1e8	446	tc_sched_clock = tc_sched_clock_read;
8e315a7b	447	}
4d243f92 DB	448
4d243f92 DB	449	/* and away we go! */
5b3c11da BB	450	ret = clocksource_register_hz(&clksrc, divided_rate);
	451	if (ret)
	452	goto err_disable_t1;
4d243f92 DB	453
4d243f92 DB	454	/* channel 2: periodic and oneshot timer support */
86232bfd	455	ret = setup_clkevents(&tc, clk32k_divisor_idx);
5b3c11da BB	456	if (ret)
5b3c11da BB	457	goto err_unregister_clksrc;
4d243f92	458
f712a1e8 AB	459	sched_clock_register(tc_sched_clock, 32, divided_rate);
f712a1e8 AB	460
4d243f92	461	return 0;
0e746ec5	462
5b3c11da BB	463	err_unregister_clksrc:
	464	clocksource_unregister(&clksrc);
	465
	466	err_disable_t1:
86232bfd AB	467	if (bits != 32)
86232bfd AB	468	clk_disable_unprepare(tc.clk[1]);
5b3c11da	469
0e746ec5 BB	470	err_disable_t0:
	471	clk_disable_unprepare(t0_clk);
	472
86232bfd AB	473	tcaddr = NULL;
86232bfd AB	474
0e746ec5	475	return ret;
4d243f92	476	}
86232bfd	477	TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);