[linux-block.git] / drivers / clocksource / timer-atmel-pit.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
 *
 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
 * Revision	 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
 * Converted to ClockSource/ClockEvents by David Brownell.
 */

#define pr_fmt(fmt)	"AT91: PIT: " fmt

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>

#define AT91_PIT_MR		0x00			/* Mode Register */
#define AT91_PIT_PITIEN			BIT(25)			/* Timer Interrupt Enable */
#define AT91_PIT_PITEN			BIT(24)			/* Timer Enabled */
#define AT91_PIT_PIV			GENMASK(19, 0)		/* Periodic Interval Value */

#define AT91_PIT_SR		0x04			/* Status Register */
#define AT91_PIT_PITS			BIT(0)			/* Timer Status */

#define AT91_PIT_PIVR		0x08			/* Periodic Interval Value Register */
#define AT91_PIT_PIIR		0x0c			/* Periodic Interval Image Register */
#define AT91_PIT_PICNT			GENMASK(31, 20)		/* Interval Counter */
#define AT91_PIT_CPIV			GENMASK(19, 0)		/* Inverval Value */

#define PIT_CPIV(x)	((x) & AT91_PIT_CPIV)
#define PIT_PICNT(x)	(((x) & AT91_PIT_PICNT) >> 20)

struct pit_data {
	struct clock_event_device	clkevt;
	struct clocksource		clksrc;

	void __iomem	*base;
	u32		cycle;
	u32		cnt;
	unsigned int	irq;
	struct clk	*mck;
};

static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc)
{
	return container_of(clksrc, struct pit_data, clksrc);
}

static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt)
{
	return container_of(clkevt, struct pit_data, clkevt);
}

static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
{
	return readl_relaxed(base + reg_offset);
}

static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
{
	writel_relaxed(value, base + reg_offset);
}

/*
 * Clocksource:  just a monotonic counter of MCK/16 cycles.
 * We don't care whether or not PIT irqs are enabled.
 */
static u64 read_pit_clk(struct clocksource *cs)
{
	struct pit_data *data = clksrc_to_pit_data(cs);
	unsigned long flags;
	u32 elapsed;
	u32 t;

	raw_local_irq_save(flags);
	elapsed = data->cnt;
	t = pit_read(data->base, AT91_PIT_PIIR);
	raw_local_irq_restore(flags);

	elapsed += PIT_PICNT(t) * data->cycle;
	elapsed += PIT_CPIV(t);
	return elapsed;
}

static int pit_clkevt_shutdown(struct clock_event_device *dev)
{
	struct pit_data *data = clkevt_to_pit_data(dev);

	/* disable irq, leaving the clocksource active */
	pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN);
	return 0;
}

/*
 * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
 */
static int pit_clkevt_set_periodic(struct clock_event_device *dev)
{
	struct pit_data *data = clkevt_to_pit_data(dev);

	/* update clocksource counter */
	data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
	pit_write(data->base, AT91_PIT_MR,
		  (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN);
	return 0;
}

static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
{
	struct pit_data *data = clkevt_to_pit_data(cedev);

	/* Disable timer */
	pit_write(data->base, AT91_PIT_MR, 0);
}

static void at91sam926x_pit_reset(struct pit_data *data)
{
	/* Disable timer and irqs */
	pit_write(data->base, AT91_PIT_MR, 0);

	/* Clear any pending interrupts, wait for PIT to stop counting */
	while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
		cpu_relax();

	/* Start PIT but don't enable IRQ */
	pit_write(data->base, AT91_PIT_MR,
		  (data->cycle - 1) | AT91_PIT_PITEN);
}

static void at91sam926x_pit_resume(struct clock_event_device *cedev)
{
	struct pit_data *data = clkevt_to_pit_data(cedev);

	at91sam926x_pit_reset(data);
}

/*
 * IRQ handler for the timer.
 */
static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
{
	struct pit_data *data = dev_id;

	/* The PIT interrupt may be disabled, and is shared */
	if (clockevent_state_periodic(&data->clkevt) &&
	    (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
		/* Get number of ticks performed before irq, and ack it */
		data->cnt += data->cycle * PIT_PICNT(pit_read(data->base,
							      AT91_PIT_PIVR));
		data->clkevt.event_handler(&data->clkevt);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

/*
 * Set up both clocksource and clockevent support.
 */
static int __init at91sam926x_pit_dt_init(struct device_node *node)
{
	unsigned long   pit_rate;
	unsigned        bits;
	int             ret;
	struct pit_data *data;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->base = of_iomap(node, 0);
	if (!data->base) {
		pr_err("Could not map PIT address\n");
		ret = -ENXIO;
		goto exit;
	}

	data->mck = of_clk_get(node, 0);
	if (IS_ERR(data->mck)) {
		pr_err("Unable to get mck clk\n");
		ret = PTR_ERR(data->mck);
		goto exit;
	}

	ret = clk_prepare_enable(data->mck);
	if (ret) {
		pr_err("Unable to enable mck\n");
		goto exit;
	}

	/* Get the interrupts property */
	data->irq = irq_of_parse_and_map(node, 0);
	if (!data->irq) {
		pr_err("Unable to get IRQ from DT\n");
		ret = -EINVAL;
		goto exit;
	}

	/*
	 * Use our actual MCK to figure out how many MCK/16 ticks per
	 * 1/HZ period (instead of a compile-time constant LATCH).
	 */
	pit_rate = clk_get_rate(data->mck) / 16;
	data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
	WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);

	/* Initialize and enable the timer */
	at91sam926x_pit_reset(data);

	/*
	 * Register clocksource.  The high order bits of PIV are unused,
	 * so this isn't a 32-bit counter unless we get clockevent irqs.
	 */
	bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */;
	data->clksrc.mask = CLOCKSOURCE_MASK(bits);
	data->clksrc.name = "pit";
	data->clksrc.rating = 175;
	data->clksrc.read = read_pit_clk;
	data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	
	ret = clocksource_register_hz(&data->clksrc, pit_rate);
	if (ret) {
		pr_err("Failed to register clocksource\n");
		goto exit;
	}

	/* Set up irq handler */
	ret = request_irq(data->irq, at91sam926x_pit_interrupt,
			  IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
			  "at91_tick", data);
	if (ret) {
		pr_err("Unable to setup IRQ\n");
		clocksource_unregister(&data->clksrc);
		goto exit;
	}

	/* Set up and register clockevents */
	data->clkevt.name = "pit";
	data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
	data->clkevt.shift = 32;
	data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
	data->clkevt.rating = 100;
	data->clkevt.cpumask = cpumask_of(0);

	data->clkevt.set_state_shutdown = pit_clkevt_shutdown;
	data->clkevt.set_state_periodic = pit_clkevt_set_periodic;
	data->clkevt.resume = at91sam926x_pit_resume;
	data->clkevt.suspend = at91sam926x_pit_suspend;
	clockevents_register_device(&data->clkevt);

	return 0;

exit:
	kfree(data);
	return ret;
}
TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
		       at91sam926x_pit_dt_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1a0ed732	2	/*
ad48ce74	3	* at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
1a0ed732 AV	4	*
	5	* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
	6	* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
ad48ce74	7	* Converted to ClockSource/ClockEvents by David Brownell.
1a0ed732	8	*/
52c3ffb0	9
cffbfe63 MR	10	#define pr_fmt(fmt) "AT91: PIT: " fmt
cffbfe63 MR	11
52c3ffb0 MR	12	#include <linux/clk.h>
52c3ffb0 MR	13	#include <linux/clockchips.h>
1a0ed732 AV	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/kernel.h>
23fa648f JCPV	17	#include <linux/of.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of_irq.h>
64568d1d	20	#include <linux/slab.h>
1a0ed732	21
ffe5cd8e	22	#define AT91_PIT_MR 0x00 /* Mode Register */
52c3ffb0 MR	23	#define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */
	24	#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
	25	#define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */
ffe5cd8e JCPV	26
ffe5cd8e JCPV	27	#define AT91_PIT_SR 0x04 /* Status Register */
52c3ffb0	28	#define AT91_PIT_PITS BIT(0) /* Timer Status */
ffe5cd8e JCPV	29
	30	#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
	31	#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
52c3ffb0 MR	32	#define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */
52c3ffb0 MR	33	#define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */
1a0ed732 AV	34
	35	#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
	36	#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
	37
64568d1d MR	38	struct pit_data {
	39	struct clock_event_device clkevt;
	40	struct clocksource clksrc;
ad48ce74	41
64568d1d MR	42	void __iomem *base;
	43	u32 cycle;
	44	u32 cnt;
	45	unsigned int irq;
	46	struct clk *mck;
	47	};
	48
	49	static inline struct pit_data clksrc_to_pit_data(struct clocksource clksrc)
4ab0c599	50	{
64568d1d	51	return container_of(clksrc, struct pit_data, clksrc);
4ab0c599 JCPV	52	}
4ab0c599 JCPV	53
64568d1d	54	static inline struct pit_data clkevt_to_pit_data(struct clock_event_device clkevt)
4ab0c599	55	{
64568d1d MR	56	return container_of(clkevt, struct pit_data, clkevt);
	57	}
	58
	59	static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
	60	{
4806c87f	61	return readl_relaxed(base + reg_offset);
64568d1d MR	62	}
	63
	64	static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
	65	{
4806c87f	66	writel_relaxed(value, base + reg_offset);
4ab0c599	67	}
ad48ce74	68
1a0ed732	69	/*
ad48ce74 AV	70	* Clocksource: just a monotonic counter of MCK/16 cycles.
ad48ce74 AV	71	* We don't care whether or not PIT irqs are enabled.
1a0ed732	72	*/
a5a1d1c2	73	static u64 read_pit_clk(struct clocksource *cs)
1a0ed732	74	{
64568d1d	75	struct pit_data *data = clksrc_to_pit_data(cs);
ad48ce74 AV	76	unsigned long flags;
	77	u32 elapsed;
	78	u32 t;
	79
	80	raw_local_irq_save(flags);
64568d1d MR	81	elapsed = data->cnt;
64568d1d MR	82	t = pit_read(data->base, AT91_PIT_PIIR);
ad48ce74 AV	83	raw_local_irq_restore(flags);
ad48ce74 AV	84
64568d1d	85	elapsed += PIT_PICNT(t) * data->cycle;
ad48ce74 AV	86	elapsed += PIT_CPIV(t);
	87	return elapsed;
	88	}
	89
85250fb8 VK	90	static int pit_clkevt_shutdown(struct clock_event_device *dev)
	91	{
	92	struct pit_data *data = clkevt_to_pit_data(dev);
	93
	94	/* disable irq, leaving the clocksource active */
	95	pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) \| AT91_PIT_PITEN);
	96	return 0;
	97	}
	98
ad48ce74 AV	99	/*
	100	* Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
	101	*/
85250fb8	102	static int pit_clkevt_set_periodic(struct clock_event_device *dev)
ad48ce74	103	{
64568d1d MR	104	struct pit_data *data = clkevt_to_pit_data(dev);
64568d1d MR	105
85250fb8 VK	106	/* update clocksource counter */
	107	data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
	108	pit_write(data->base, AT91_PIT_MR,
	109	(data->cycle - 1) \| AT91_PIT_PITEN \| AT91_PIT_PITIEN);
	110	return 0;
1a0ed732 AV	111	}
1a0ed732 AV	112
49356ae9 SW	113	static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
49356ae9 SW	114	{
64568d1d MR	115	struct pit_data *data = clkevt_to_pit_data(cedev);
64568d1d MR	116
49356ae9	117	/* Disable timer */
64568d1d	118	pit_write(data->base, AT91_PIT_MR, 0);
49356ae9 SW	119	}
49356ae9 SW	120
64568d1d	121	static void at91sam926x_pit_reset(struct pit_data *data)
49356ae9 SW	122	{
49356ae9 SW	123	/* Disable timer and irqs */
64568d1d	124	pit_write(data->base, AT91_PIT_MR, 0);
49356ae9 SW	125
49356ae9 SW	126	/* Clear any pending interrupts, wait for PIT to stop counting */
64568d1d	127	while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
49356ae9 SW	128	cpu_relax();
	129
	130	/* Start PIT but don't enable IRQ */
64568d1d MR	131	pit_write(data->base, AT91_PIT_MR,
64568d1d MR	132	(data->cycle - 1) \| AT91_PIT_PITEN);
49356ae9 SW	133	}
	134
	135	static void at91sam926x_pit_resume(struct clock_event_device *cedev)
	136	{
64568d1d	137	struct pit_data *data = clkevt_to_pit_data(cedev);
ad48ce74	138
64568d1d MR	139	at91sam926x_pit_reset(data);
64568d1d MR	140	}
ad48ce74	141
1a0ed732 AV	142	/*
	143	* IRQ handler for the timer.
	144	*/
ad48ce74	145	static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
1a0ed732	146	{
64568d1d MR	147	struct pit_data *data = dev_id;
64568d1d MR	148
ad48ce74	149	/* The PIT interrupt may be disabled, and is shared */
85250fb8	150	if (clockevent_state_periodic(&data->clkevt) &&
64568d1d	151	(pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
ad48ce74	152	/* Get number of ticks performed before irq, and ack it */
2783e5d6 AB	153	data->cnt += data->cycle * PIT_PICNT(pit_read(data->base,
	154	AT91_PIT_PIVR));
	155	data->clkevt.event_handler(&data->clkevt);
1a0ed732	156
1a0ed732	157	return IRQ_HANDLED;
ad48ce74 AV	158	}
	159
	160	return IRQ_NONE;
1a0ed732 AV	161	}
1a0ed732 AV	162
1a0ed732	163	/*
ad48ce74	164	* Set up both clocksource and clockevent support.
1a0ed732	165	*/
a17686c4	166	static int __init at91sam926x_pit_dt_init(struct device_node *node)
1a0ed732	167	{
a17686c4 AB	168	unsigned long pit_rate;
	169	unsigned bits;
	170	int ret;
	171	struct pit_data *data;
	172
	173	data = kzalloc(sizeof(*data), GFP_KERNEL);
	174	if (!data)
	175	return -ENOMEM;
	176
	177	data->base = of_iomap(node, 0);
	178	if (!data->base) {
	179	pr_err("Could not map PIT address\n");
52bf4a90 AB	180	ret = -ENXIO;
52bf4a90 AB	181	goto exit;
a17686c4 AB	182	}
	183
	184	data->mck = of_clk_get(node, 0);
	185	if (IS_ERR(data->mck)) {
	186	pr_err("Unable to get mck clk\n");
52bf4a90 AB	187	ret = PTR_ERR(data->mck);
52bf4a90 AB	188	goto exit;
a17686c4 AB	189	}
	190
	191	ret = clk_prepare_enable(data->mck);
	192	if (ret) {
	193	pr_err("Unable to enable mck\n");
52bf4a90	194	goto exit;
a17686c4 AB	195	}
	196
	197	/* Get the interrupts property */
	198	data->irq = irq_of_parse_and_map(node, 0);
	199	if (!data->irq) {
	200	pr_err("Unable to get IRQ from DT\n");
52bf4a90 AB	201	ret = -EINVAL;
52bf4a90 AB	202	goto exit;
a17686c4	203	}
ad48ce74 AV	204
	205	/*
	206	* Use our actual MCK to figure out how many MCK/16 ticks per
	207	* 1/HZ period (instead of a compile-time constant LATCH).
	208	*/
64568d1d MR	209	pit_rate = clk_get_rate(data->mck) / 16;
	210	data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
	211	WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);
1a0ed732	212
ad48ce74	213	/* Initialize and enable the timer */
64568d1d	214	at91sam926x_pit_reset(data);
ad48ce74 AV	215
	216	/*
	217	* Register clocksource. The high order bits of PIV are unused,
	218	* so this isn't a 32-bit counter unless we get clockevent irqs.
	219	*/
64568d1d MR	220	bits = 12 /* PICNT / + ilog2(data->cycle) / PIV */;
	221	data->clksrc.mask = CLOCKSOURCE_MASK(bits);
	222	data->clksrc.name = "pit";
	223	data->clksrc.rating = 175;
005e5627 DL	224	data->clksrc.read = read_pit_clk;
005e5627 DL	225	data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
504f34c9 DL	226
	227	ret = clocksource_register_hz(&data->clksrc, pit_rate);
	228	if (ret) {
ac9ce6d1	229	pr_err("Failed to register clocksource\n");
52bf4a90	230	goto exit;
504f34c9	231	}
ad48ce74 AV	232
ad48ce74 AV	233	/* Set up irq handler */
64568d1d	234	ret = request_irq(data->irq, at91sam926x_pit_interrupt,
7f282e01	235	IRQF_SHARED \| IRQF_TIMER \| IRQF_IRQPOLL,
64568d1d	236	"at91_tick", data);
504f34c9 DL	237	if (ret) {
504f34c9 DL	238	pr_err("Unable to setup IRQ\n");
52bf4a90 AB	239	clocksource_unregister(&data->clksrc);
52bf4a90 AB	240	goto exit;
504f34c9	241	}
ad48ce74 AV	242
ad48ce74 AV	243	/* Set up and register clockevents */
64568d1d MR	244	data->clkevt.name = "pit";
	245	data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
	246	data->clkevt.shift = 32;
	247	data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
	248	data->clkevt.rating = 100;
	249	data->clkevt.cpumask = cpumask_of(0);
	250
85250fb8 VK	251	data->clkevt.set_state_shutdown = pit_clkevt_shutdown;
85250fb8 VK	252	data->clkevt.set_state_periodic = pit_clkevt_set_periodic;
64568d1d MR	253	data->clkevt.resume = at91sam926x_pit_resume;
	254	data->clkevt.suspend = at91sam926x_pit_suspend;
	255	clockevents_register_device(&data->clkevt);
504f34c9 DL	256
504f34c9 DL	257	return 0;
52bf4a90 AB	258
	259	exit:
	260	kfree(data);
	261	return ret;
1a0ed732	262	}
17273395	263	TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
f807a89c	264	at91sam926x_pit_dt_init);