[linux-2.6-block.git] / drivers / clocksource / timer-atlas7.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * System timer for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/sched_clock.h>

#define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
#define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
#define SIRFSOC_TIMER_MATCH_0				0x0018
#define SIRFSOC_TIMER_MATCH_1				0x001c
#define SIRFSOC_TIMER_COUNTER_0				0x0048
#define SIRFSOC_TIMER_COUNTER_1				0x004c
#define SIRFSOC_TIMER_INTR_STATUS			0x0060
#define SIRFSOC_TIMER_WATCHDOG_EN			0x0064
#define SIRFSOC_TIMER_64COUNTER_CTRL			0x0068
#define SIRFSOC_TIMER_64COUNTER_LO			0x006c
#define SIRFSOC_TIMER_64COUNTER_HI			0x0070
#define SIRFSOC_TIMER_64COUNTER_LOAD_LO			0x0074
#define SIRFSOC_TIMER_64COUNTER_LOAD_HI			0x0078
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO		0x007c
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI		0x0080

#define SIRFSOC_TIMER_REG_CNT 6

static unsigned long atlas7_timer_rate;

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	SIRFSOC_TIMER_WATCHDOG_EN,
	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	SIRFSOC_TIMER_64COUNTER_CTRL,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
};

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

static void __iomem *sirfsoc_timer_base;

/* disable count and interrupt */
static inline void sirfsoc_timer_count_disable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* enable count and interrupt */
static inline void sirfsoc_timer_count_enable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* timer interrupt handler */
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;
	int cpu = smp_processor_id();

	/* clear timer interrupt */
	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	if (clockevent_state_oneshot(ce))
		sirfsoc_timer_count_disable(cpu);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

/* read 64-bit timer counter */
static u64 sirfsoc_timer_read(struct clocksource *cs)
{
	u64 cycles;

	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);

	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);

	return cycles;
}

static int sirfsoc_timer_set_next_event(unsigned long delta,
	struct clock_event_device *ce)
{
	int cpu = smp_processor_id();

	/* disable timer first, then modify the related registers */
	sirfsoc_timer_count_disable(cpu);

	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
		4 * cpu);
	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
		4 * cpu);

	/* enable the tick */
	sirfsoc_timer_count_enable(cpu);

	return 0;
}

/* Oneshot is enabled in set_next_event */
static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
{
	sirfsoc_timer_count_disable(smp_processor_id());
	return 0;
}

static void sirfsoc_clocksource_suspend(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
}

static void sirfsoc_clocksource_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);

	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
}

static struct clock_event_device __percpu *sirfsoc_clockevent;

static struct clocksource sirfsoc_clocksource = {
	.name = "sirfsoc_clocksource",
	.rating = 200,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.read = sirfsoc_timer_read,
	.suspend = sirfsoc_clocksource_suspend,
	.resume = sirfsoc_clocksource_resume,
};

static struct irqaction sirfsoc_timer_irq = {
	.name = "sirfsoc_timer0",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static struct irqaction sirfsoc_timer1_irq = {
	.name = "sirfsoc_timer1",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static int sirfsoc_local_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
	struct irqaction *action;

	if (cpu == 0)
		action = &sirfsoc_timer_irq;
	else
		action = &sirfsoc_timer1_irq;

	ce->irq = action->irq;
	ce->name = "local_timer";
	ce->features = CLOCK_EVT_FEAT_ONESHOT;
	ce->rating = 200;
	ce->set_state_shutdown = sirfsoc_timer_shutdown;
	ce->set_state_oneshot = sirfsoc_timer_shutdown;
	ce->tick_resume = sirfsoc_timer_shutdown;
	ce->set_next_event = sirfsoc_timer_set_next_event;
	clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
	ce->max_delta_ticks = (unsigned long)-2;
	ce->min_delta_ns = clockevent_delta2ns(2, ce);
	ce->min_delta_ticks = 2;
	ce->cpumask = cpumask_of(cpu);

	action->dev_id = ce;
	BUG_ON(setup_irq(ce->irq, action));
	irq_force_affinity(action->irq, cpumask_of(cpu));

	clockevents_register_device(ce);
	return 0;
}

static int sirfsoc_local_timer_dying_cpu(unsigned int cpu)
{
	sirfsoc_timer_count_disable(1);

	if (cpu == 0)
		remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	else
		remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
	return 0;
}

static int __init sirfsoc_clockevent_init(void)
{
	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	BUG_ON(!sirfsoc_clockevent);

	/* Install and invoke hotplug callbacks */
	return cpuhp_setup_state(CPUHP_AP_MARCO_TIMER_STARTING,
				 "clockevents/marco:starting",
				 sirfsoc_local_timer_starting_cpu,
				 sirfsoc_local_timer_dying_cpu);
}

/* initialize the kernel jiffy timer source */
static int __init sirfsoc_atlas7_timer_init(struct device_node *np)
{
	struct clk *clk;

	clk = of_clk_get(np, 0);
	BUG_ON(IS_ERR(clk));

	BUG_ON(clk_prepare_enable(clk));

	atlas7_timer_rate = clk_get_rate(clk);

	/* timer dividers: 0, not divided */
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);

	/* Initialize timer counters to 0 */
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);

	/* Clear all interrupts */
	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));

	return sirfsoc_clockevent_init();
}

static int __init sirfsoc_of_timer_init(struct device_node *np)
{
	sirfsoc_timer_base = of_iomap(np, 0);
	if (!sirfsoc_timer_base) {
		pr_err("unable to map timer cpu registers\n");
		return -ENXIO;
	}

	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
	if (!sirfsoc_timer_irq.irq) {
		pr_err("No irq passed for timer0 via DT\n");
		return -EINVAL;
	}

	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
	if (!sirfsoc_timer1_irq.irq) {
		pr_err("No irq passed for timer1 via DT\n");
		return -EINVAL;
	}

	return sirfsoc_atlas7_timer_init(np);
}
TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);
Commit	Line	Data
a636cd6c	1	// SPDX-License-Identifier: GPL-2.0-or-later
4898de3d BS	2	/*
	3	* System timer for CSR SiRFprimaII
	4	*
	5	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
4898de3d BS	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/clockchips.h>
	11	#include <linux/clocksource.h>
05a65485	12	#include <linux/cpu.h>
4898de3d BS	13	#include <linux/bitops.h>
	14	#include <linux/irq.h>
	15	#include <linux/clk.h>
	16	#include <linux/slab.h>
	17	#include <linux/of.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/of_address.h>
38ff87f7	20	#include <linux/sched_clock.h>
980c51ab	21
4898de3d BS	22	#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
	23	#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
	24	#define SIRFSOC_TIMER_MATCH_0 0x0018
	25	#define SIRFSOC_TIMER_MATCH_1 0x001c
	26	#define SIRFSOC_TIMER_COUNTER_0 0x0048
	27	#define SIRFSOC_TIMER_COUNTER_1 0x004c
	28	#define SIRFSOC_TIMER_INTR_STATUS 0x0060
	29	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
	30	#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
	31	#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
	32	#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
	33	#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
	34	#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
	35	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
	36	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
	37
	38	#define SIRFSOC_TIMER_REG_CNT 6
	39
5833ac98	40	static unsigned long atlas7_timer_rate;
ef89af1f	41
4898de3d BS	42	static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	43	SIRFSOC_TIMER_WATCHDOG_EN,
	44	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	45	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	46	SIRFSOC_TIMER_64COUNTER_CTRL,
	47	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	48	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
	49	};
	50
	51	static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
	52
	53	static void __iomem *sirfsoc_timer_base;
4898de3d BS	54
	55	/* disable count and interrupt */
	56	static inline void sirfsoc_timer_count_disable(int idx)
	57	{
	58	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
	59	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	60	}
	61
	62	/* enable count and interrupt */
	63	static inline void sirfsoc_timer_count_enable(int idx)
	64	{
28cf3567	65	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) \| 0x3,
4898de3d BS	66	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	67	}
	68
	69	/* timer interrupt handler */
	70	static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
	71	{
	72	struct clock_event_device *ce = dev_id;
	73	int cpu = smp_processor_id();
	74
	75	/* clear timer interrupt */
	76	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	77
1e729d37	78	if (clockevent_state_oneshot(ce))
4898de3d BS	79	sirfsoc_timer_count_disable(cpu);
	80
	81	ce->event_handler(ce);
	82
	83	return IRQ_HANDLED;
	84	}
	85
	86	/* read 64-bit timer counter */
a5a1d1c2	87	static u64 sirfsoc_timer_read(struct clocksource *cs)
4898de3d BS	88	{
	89	u64 cycles;
	90
	91	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	92	BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	93
	94	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	95	cycles = (cycles << 32) \| readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
	96
	97	return cycles;
	98	}
	99
	100	static int sirfsoc_timer_set_next_event(unsigned long delta,
	101	struct clock_event_device *ce)
	102	{
	103	int cpu = smp_processor_id();
	104
28cf3567 HL	105	/* disable timer first, then modify the related registers */
	106	sirfsoc_timer_count_disable(cpu);
	107
4898de3d BS	108	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
	109	4 * cpu);
	110	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
	111	4 * cpu);
	112
	113	/* enable the tick */
	114	sirfsoc_timer_count_enable(cpu);
	115
	116	return 0;
	117	}
	118
1e729d37 VK	119	/* Oneshot is enabled in set_next_event */
1e729d37 VK	120	static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
4898de3d	121	{
4898de3d	122	sirfsoc_timer_count_disable(smp_processor_id());
1e729d37	123	return 0;
4898de3d BS	124	}
	125
	126	static void sirfsoc_clocksource_suspend(struct clocksource *cs)
	127	{
	128	int i;
	129
	130	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
	131	sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
	132	}
	133
	134	static void sirfsoc_clocksource_resume(struct clocksource *cs)
	135	{
	136	int i;
	137
	138	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
	139	writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
	140
	141	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
	142	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	143	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
	144	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	145
	146	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	147	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	148	}
	149
05a65485	150	static struct clock_event_device __percpu *sirfsoc_clockevent;
4898de3d BS	151
	152	static struct clocksource sirfsoc_clocksource = {
	153	.name = "sirfsoc_clocksource",
	154	.rating = 200,
	155	.mask = CLOCKSOURCE_MASK(64),
	156	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	157	.read = sirfsoc_timer_read,
	158	.suspend = sirfsoc_clocksource_suspend,
	159	.resume = sirfsoc_clocksource_resume,
	160	};
	161
	162	static struct irqaction sirfsoc_timer_irq = {
	163	.name = "sirfsoc_timer0",
	164	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	165	.handler = sirfsoc_timer_interrupt,
4898de3d BS	166	};
4898de3d BS	167
4898de3d BS	168	static struct irqaction sirfsoc_timer1_irq = {
	169	.name = "sirfsoc_timer1",
	170	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	171	.handler = sirfsoc_timer_interrupt,
	172	};
	173
eb0a9d8c	174	static int sirfsoc_local_timer_starting_cpu(unsigned int cpu)
4898de3d	175	{
eb0a9d8c	176	struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
05a65485 SB	177	struct irqaction *action;
	178
	179	if (cpu == 0)
	180	action = &sirfsoc_timer_irq;
	181	else
	182	action = &sirfsoc_timer1_irq;
4898de3d	183
05a65485	184	ce->irq = action->irq;
4898de3d	185	ce->name = "local_timer";
05a65485 SB	186	ce->features = CLOCK_EVT_FEAT_ONESHOT;
05a65485 SB	187	ce->rating = 200;
1e729d37 VK	188	ce->set_state_shutdown = sirfsoc_timer_shutdown;
	189	ce->set_state_oneshot = sirfsoc_timer_shutdown;
	190	ce->tick_resume = sirfsoc_timer_shutdown;
4898de3d	191	ce->set_next_event = sirfsoc_timer_set_next_event;
5833ac98	192	clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
05a65485	193	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
547733c5	194	ce->max_delta_ticks = (unsigned long)-2;
05a65485	195	ce->min_delta_ns = clockevent_delta2ns(2, ce);
547733c5	196	ce->min_delta_ticks = 2;
05a65485	197	ce->cpumask = cpumask_of(cpu);
4898de3d	198
05a65485 SB	199	action->dev_id = ce;
05a65485 SB	200	BUG_ON(setup_irq(ce->irq, action));
f214be50	201	irq_force_affinity(action->irq, cpumask_of(cpu));
4898de3d BS	202
	203	clockevents_register_device(ce);
	204	return 0;
	205	}
	206
eb0a9d8c	207	static int sirfsoc_local_timer_dying_cpu(unsigned int cpu)
4898de3d BS	208	{
	209	sirfsoc_timer_count_disable(1);
	210
05a65485 SB	211	if (cpu == 0)
	212	remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	213	else
	214	remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
eb0a9d8c	215	return 0;
4898de3d BS	216	}
4898de3d BS	217
c41c96dd	218	static int __init sirfsoc_clockevent_init(void)
4898de3d	219	{
05a65485 SB	220	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	221	BUG_ON(!sirfsoc_clockevent);
	222
eb0a9d8c RC	223	/* Install and invoke hotplug callbacks */
eb0a9d8c RC	224	return cpuhp_setup_state(CPUHP_AP_MARCO_TIMER_STARTING,
73c1b41e	225	"clockevents/marco:starting",
eb0a9d8c RC	226	sirfsoc_local_timer_starting_cpu,
eb0a9d8c RC	227	sirfsoc_local_timer_dying_cpu);
4898de3d BS	228	}
	229
	230	/* initialize the kernel jiffy timer source */
c41c96dd	231	static int __init sirfsoc_atlas7_timer_init(struct device_node *np)
4898de3d	232	{
4898de3d BS	233	struct clk *clk;
4898de3d BS	234
c7cff54d	235	clk = of_clk_get(np, 0);
4898de3d	236	BUG_ON(IS_ERR(clk));
38941522 ZS	237
	238	BUG_ON(clk_prepare_enable(clk));
	239
5833ac98	240	atlas7_timer_rate = clk_get_rate(clk);
4898de3d	241
ef89af1f YL	242	/* timer dividers: 0, not divided */
	243	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	244	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	245	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
4898de3d BS	246
	247	/* Initialize timer counters to 0 */
	248	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	249	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	250	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	251	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	252	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	253	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
	254
	255	/* Clear all interrupts */
	256	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	257
5833ac98	258	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));
4898de3d	259
c41c96dd	260	return sirfsoc_clockevent_init();
4898de3d BS	261	}
4898de3d BS	262
c41c96dd	263	static int __init sirfsoc_of_timer_init(struct device_node *np)
4898de3d	264	{
4898de3d	265	sirfsoc_timer_base = of_iomap(np, 0);
c41c96dd DL	266	if (!sirfsoc_timer_base) {
	267	pr_err("unable to map timer cpu registers\n");
	268	return -ENXIO;
	269	}
4898de3d BS	270
4898de3d BS	271	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
c41c96dd DL	272	if (!sirfsoc_timer_irq.irq) {
	273	pr_err("No irq passed for timer0 via DT\n");
	274	return -EINVAL;
	275	}
4898de3d	276
4898de3d	277	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
c41c96dd DL	278	if (!sirfsoc_timer1_irq.irq) {
	279	pr_err("No irq passed for timer1 via DT\n");
	280	return -EINVAL;
	281	}
4898de3d	282
c41c96dd	283	return sirfsoc_atlas7_timer_init(np);
4898de3d	284	}
17273395	285	TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);