[linux-block.git] / drivers / clocksource / timer-armada-370-xp.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Marvell Armada 370/XP SoC timer handling.
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Timer 0 is used as free-running clocksource, while timer 1 is
 * used as clock_event_device.
 *
 * ---
 * Clocksource driver for Armada 370 and Armada XP SoC.
 * This driver implements one compatible string for each SoC, given
 * each has its own characteristics:
 *
 *   * Armada 370 has no 25 MHz fixed timer.
 *
 *   * Armada XP cannot work properly without such 25 MHz fixed timer as
 *     doing otherwise leads to using a clocksource whose frequency varies
 *     when doing cpufreq frequency changes.
 *
 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/timer.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/sched_clock.h>
#include <linux/percpu.h>
#include <linux/syscore_ops.h>

#include <asm/delay.h>

/*
 * Timer block registers.
 */
#define TIMER_CTRL_OFF		0x0000
#define  TIMER0_EN		 BIT(0)
#define  TIMER0_RELOAD_EN	 BIT(1)
#define  TIMER0_25MHZ            BIT(11)
#define  TIMER0_DIV(div)         ((div) << 19)
#define  TIMER1_EN		 BIT(2)
#define  TIMER1_RELOAD_EN	 BIT(3)
#define  TIMER1_25MHZ            BIT(12)
#define  TIMER1_DIV(div)         ((div) << 22)
#define TIMER_EVENTS_STATUS	0x0004
#define  TIMER0_CLR_MASK         (~0x1)
#define  TIMER1_CLR_MASK         (~0x100)
#define TIMER0_RELOAD_OFF	0x0010
#define TIMER0_VAL_OFF		0x0014
#define TIMER1_RELOAD_OFF	0x0018
#define TIMER1_VAL_OFF		0x001c

#define LCL_TIMER_EVENTS_STATUS	0x0028
/* Global timers are connected to the coherency fabric clock, and the
   below divider reduces their incrementing frequency. */
#define TIMER_DIVIDER_SHIFT     5
#define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)

/*
 * SoC-specific data.
 */
static void __iomem *timer_base, *local_base;
static unsigned int timer_clk;
static bool timer25Mhz = true;
static u32 enable_mask;

/*
 * Number of timer ticks per jiffy.
 */
static u32 ticks_per_jiffy;

static struct clock_event_device __percpu *armada_370_xp_evt;

static void local_timer_ctrl_clrset(u32 clr, u32 set)
{
	writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
		local_base + TIMER_CTRL_OFF);
}

static u64 notrace armada_370_xp_read_sched_clock(void)
{
	return ~readl(timer_base + TIMER0_VAL_OFF);
}

/*
 * Clockevent handling.
 */
static int
armada_370_xp_clkevt_next_event(unsigned long delta,
				struct clock_event_device *dev)
{
	/*
	 * Clear clockevent timer interrupt.
	 */
	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);

	/*
	 * Setup new clockevent timer value.
	 */
	writel(delta, local_base + TIMER0_VAL_OFF);

	/*
	 * Enable the timer.
	 */
	local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
	return 0;
}

static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
{
	/*
	 * Disable timer.
	 */
	local_timer_ctrl_clrset(TIMER0_EN, 0);

	/*
	 * ACK pending timer interrupt.
	 */
	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
	return 0;
}

static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
{
	/*
	 * Setup timer to fire at 1/HZ intervals.
	 */
	writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
	writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);

	/*
	 * Enable timer.
	 */
	local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
	return 0;
}

static int armada_370_xp_clkevt_irq;

static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
{
	/*
	 * ACK timer interrupt and call event handler.
	 */
	struct clock_event_device *evt = dev_id;

	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

/*
 * Setup the local clock events for a CPU.
 */
static int armada_370_xp_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
	u32 clr = 0, set = 0;

	if (timer25Mhz)
		set = TIMER0_25MHZ;
	else
		clr = TIMER0_25MHZ;
	local_timer_ctrl_clrset(clr, set);

	evt->name		= "armada_370_xp_per_cpu_tick";
	evt->features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_PERIODIC;
	evt->shift		= 32;
	evt->rating		= 300;
	evt->set_next_event	= armada_370_xp_clkevt_next_event;
	evt->set_state_shutdown	= armada_370_xp_clkevt_shutdown;
	evt->set_state_periodic	= armada_370_xp_clkevt_set_periodic;
	evt->set_state_oneshot	= armada_370_xp_clkevt_shutdown;
	evt->tick_resume	= armada_370_xp_clkevt_shutdown;
	evt->irq		= armada_370_xp_clkevt_irq;
	evt->cpumask		= cpumask_of(cpu);

	clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
	enable_percpu_irq(evt->irq, 0);

	return 0;
}

static int armada_370_xp_timer_dying_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);

	evt->set_state_shutdown(evt);
	disable_percpu_irq(evt->irq);
	return 0;
}

static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;

static int armada_370_xp_timer_suspend(void)
{
	timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
	timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
	return 0;
}

static void armada_370_xp_timer_resume(void)
{
	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
	writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
	writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
}

static struct syscore_ops armada_370_xp_timer_syscore_ops = {
	.suspend	= armada_370_xp_timer_suspend,
	.resume		= armada_370_xp_timer_resume,
};

static unsigned long armada_370_delay_timer_read(void)
{
	return ~readl(timer_base + TIMER0_VAL_OFF);
}

static struct delay_timer armada_370_delay_timer = {
	.read_current_timer = armada_370_delay_timer_read,
};

static int __init armada_370_xp_timer_common_init(struct device_node *np)
{
	u32 clr = 0, set = 0;
	int res;

	timer_base = of_iomap(np, 0);
	if (!timer_base) {
		pr_err("Failed to iomap\n");
		return -ENXIO;
	}

	local_base = of_iomap(np, 1);
	if (!local_base) {
		pr_err("Failed to iomap\n");
		return -ENXIO;
	}

	if (timer25Mhz) {
		set = TIMER0_25MHZ;		
		enable_mask = TIMER0_EN;
	} else {
		clr = TIMER0_25MHZ;
		enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
	}
	atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
	local_timer_ctrl_clrset(clr, set);

	/*
	 * We use timer 0 as clocksource, and private(local) timer 0
	 * for clockevents
	 */
	armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);

	ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;

	/*
	 * Setup free-running clocksource timer (interrupts
	 * disabled).
	 */
	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);

	atomic_io_modify(timer_base + TIMER_CTRL_OFF,
		TIMER0_RELOAD_EN | enable_mask,
		TIMER0_RELOAD_EN | enable_mask);

	armada_370_delay_timer.freq = timer_clk;
	register_current_timer_delay(&armada_370_delay_timer);

	/*
	 * Set scale and timer for sched_clock.
	 */
	sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);

	res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
				    "armada_370_xp_clocksource",
				    timer_clk, 300, 32, clocksource_mmio_readl_down);
	if (res) {
		pr_err("Failed to initialize clocksource mmio\n");
		return res;
	}

	armada_370_xp_evt = alloc_percpu(struct clock_event_device);
	if (!armada_370_xp_evt)
		return -ENOMEM;

	/*
	 * Setup clockevent timer (interrupt-driven).
	 */
	res = request_percpu_irq(armada_370_xp_clkevt_irq,
				armada_370_xp_timer_interrupt,
				"armada_370_xp_per_cpu_tick",
				armada_370_xp_evt);
	/* Immediately configure the timer on the boot CPU */
	if (res) {
		pr_err("Failed to request percpu irq\n");
		return res;
	}

	res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
				"clockevents/armada:starting",
				armada_370_xp_timer_starting_cpu,
				armada_370_xp_timer_dying_cpu);
	if (res) {
		pr_err("Failed to setup hotplug state and timer\n");
		return res;
	}

	register_syscore_ops(&armada_370_xp_timer_syscore_ops);
	
	return 0;
}

static int __init armada_xp_timer_init(struct device_node *np)
{
	struct clk *clk = of_clk_get_by_name(np, "fixed");
	int ret;

	if (IS_ERR(clk)) {
		pr_err("Failed to get clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	timer_clk = clk_get_rate(clk);

	return armada_370_xp_timer_common_init(np);
}
TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
		       armada_xp_timer_init);

static int __init armada_375_timer_init(struct device_node *np)
{
	struct clk *clk;
	int ret;

	clk = of_clk_get_by_name(np, "fixed");
	if (!IS_ERR(clk)) {
		ret = clk_prepare_enable(clk);
		if (ret)
			return ret;
		timer_clk = clk_get_rate(clk);
	} else {

		/*
		 * This fallback is required in order to retain proper
		 * devicetree backwards compatibility.
		 */
		clk = of_clk_get(np, 0);

		/* Must have at least a clock */
		if (IS_ERR(clk)) {
			pr_err("Failed to get clock\n");
			return PTR_ERR(clk);
		}

		ret = clk_prepare_enable(clk);
		if (ret)
			return ret;

		timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
		timer25Mhz = false;
	}

	return armada_370_xp_timer_common_init(np);
}
TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",
		       armada_375_timer_init);

static int __init armada_370_timer_init(struct device_node *np)
{
	struct clk *clk;
	int ret;

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
	timer25Mhz = false;

	return armada_370_xp_timer_common_init(np);
}
TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",
		       armada_370_timer_init);
Commit	Line	Data
7160d9c4	1	// SPDX-License-Identifier: GPL-2.0
6fe9cbd1 GC	2	/*
	3	* Marvell Armada 370/XP SoC timer handling.
	4	*
	5	* Copyright (C) 2012 Marvell
	6	*
	7	* Lior Amsalem <alior@marvell.com>
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	10	*
6fe9cbd1 GC	11	* Timer 0 is used as free-running clocksource, while timer 1 is
6fe9cbd1 GC	12	* used as clock_event_device.
7cd6392c EG	13	*
	14	* ---
	15	* Clocksource driver for Armada 370 and Armada XP SoC.
	16	* This driver implements one compatible string for each SoC, given
	17	* each has its own characteristics:
	18	*
	19	* * Armada 370 has no 25 MHz fixed timer.
	20	*
	21	* * Armada XP cannot work properly without such 25 MHz fixed timer as
	22	* doing otherwise leads to using a clocksource whose frequency varies
	23	* when doing cpufreq frequency changes.
	24	*
	25	* See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
6fe9cbd1 GC	26	*/
	27
	28	#include <linux/init.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/kernel.h>
307c2bf4	31	#include <linux/clk.h>
5ddb6d21	32	#include <linux/cpu.h>
6fe9cbd1 GC	33	#include <linux/timer.h>
	34	#include <linux/clockchips.h>
	35	#include <linux/interrupt.h>
	36	#include <linux/of.h>
	37	#include <linux/of_irq.h>
	38	#include <linux/of_address.h>
	39	#include <linux/irq.h>
	40	#include <linux/module.h>
38ff87f7	41	#include <linux/sched_clock.h>
ddd3f69f	42	#include <linux/percpu.h>
f9a49ab5	43	#include <linux/syscore_ops.h>
6fe9cbd1	44
cb0f2538 RK	45	#include <asm/delay.h>
cb0f2538 RK	46
6fe9cbd1 GC	47	/*
	48	* Timer block registers.
	49	*/
	50	#define TIMER_CTRL_OFF 0x0000
ad48bd61 EG	51	#define TIMER0_EN BIT(0)
	52	#define TIMER0_RELOAD_EN BIT(1)
	53	#define TIMER0_25MHZ BIT(11)
6fe9cbd1	54	#define TIMER0_DIV(div) ((div) << 19)
ad48bd61 EG	55	#define TIMER1_EN BIT(2)
	56	#define TIMER1_RELOAD_EN BIT(3)
	57	#define TIMER1_25MHZ BIT(12)
6fe9cbd1 GC	58	#define TIMER1_DIV(div) ((div) << 22)
	59	#define TIMER_EVENTS_STATUS 0x0004
	60	#define TIMER0_CLR_MASK (~0x1)
	61	#define TIMER1_CLR_MASK (~0x100)
	62	#define TIMER0_RELOAD_OFF 0x0010
	63	#define TIMER0_VAL_OFF 0x0014
	64	#define TIMER1_RELOAD_OFF 0x0018
	65	#define TIMER1_VAL_OFF 0x001c
	66
ddd3f69f	67	#define LCL_TIMER_EVENTS_STATUS 0x0028
6fe9cbd1 GC	68	/* Global timers are connected to the coherency fabric clock, and the
	69	below divider reduces their incrementing frequency. */
	70	#define TIMER_DIVIDER_SHIFT 5
	71	#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
	72
	73	/*
	74	* SoC-specific data.
	75	*/
ddd3f69f GC	76	static void __iomem timer_base, local_base;
	77	static unsigned int timer_clk;
	78	static bool timer25Mhz = true;
08cb8e46	79	static u32 enable_mask;
6fe9cbd1 GC	80
	81	/*
	82	* Number of timer ticks per jiffy.
	83	*/
	84	static u32 ticks_per_jiffy;
	85
5ddb6d21	86	static struct clock_event_device __percpu *armada_370_xp_evt;
ddd3f69f	87
3579698e EG	88	static void local_timer_ctrl_clrset(u32 clr, u32 set)
	89	{
	90	writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) \| set,
	91	local_base + TIMER_CTRL_OFF);
	92	}
ddd3f69f	93
d9dbcbe0	94	static u64 notrace armada_370_xp_read_sched_clock(void)
6fe9cbd1 GC	95	{
	96	return ~readl(timer_base + TIMER0_VAL_OFF);
	97	}
	98
	99	/*
	100	* Clockevent handling.
	101	*/
	102	static int
	103	armada_370_xp_clkevt_next_event(unsigned long delta,
	104	struct clock_event_device *dev)
	105	{
6fe9cbd1 GC	106	/*
	107	* Clear clockevent timer interrupt.
	108	*/
ddd3f69f	109	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
6fe9cbd1 GC	110
	111	/*
	112	* Setup new clockevent timer value.
	113	*/
ddd3f69f	114	writel(delta, local_base + TIMER0_VAL_OFF);
6fe9cbd1 GC	115
	116	/*
	117	* Enable the timer.
	118	*/
08cb8e46	119	local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
6fe9cbd1 GC	120	return 0;
	121	}
	122
d96f4412	123	static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
6fe9cbd1	124	{
d96f4412 VK	125	/*
	126	* Disable timer.
	127	*/
	128	local_timer_ctrl_clrset(TIMER0_EN, 0);
	129
	130	/*
	131	* ACK pending timer interrupt.
	132	*/
	133	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
	134	return 0;
	135	}
	136
	137	static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
	138	{
	139	/*
	140	* Setup timer to fire at 1/HZ intervals.
	141	*/
	142	writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
	143	writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
	144
	145	/*
	146	* Enable timer.
	147	*/
	148	local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN \| enable_mask);
	149	return 0;
6fe9cbd1 GC	150	}
6fe9cbd1 GC	151
5ddb6d21	152	static int armada_370_xp_clkevt_irq;
6fe9cbd1 GC	153
	154	static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
	155	{
	156	/*
	157	* ACK timer interrupt and call event handler.
	158	*/
5ddb6d21	159	struct clock_event_device *evt = dev_id;
6fe9cbd1	160
ddd3f69f GC	161	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
ddd3f69f GC	162	evt->event_handler(evt);
6fe9cbd1 GC	163
	164	return IRQ_HANDLED;
	165	}
	166
ddd3f69f GC	167	/*
	168	* Setup the local clock events for a CPU.
	169	*/
2c48fef7	170	static int armada_370_xp_timer_starting_cpu(unsigned int cpu)
ddd3f69f	171	{
2c48fef7	172	struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
3579698e	173	u32 clr = 0, set = 0;
ddd3f69f	174
ddd3f69f	175	if (timer25Mhz)
3579698e	176	set = TIMER0_25MHZ;
ddd3f69f	177	else
3579698e EG	178	clr = TIMER0_25MHZ;
3579698e EG	179	local_timer_ctrl_clrset(clr, set);
ddd3f69f	180
1b80043e	181	evt->name = "armada_370_xp_per_cpu_tick";
5ddb6d21 SB	182	evt->features = CLOCK_EVT_FEAT_ONESHOT \|
5ddb6d21 SB	183	CLOCK_EVT_FEAT_PERIODIC;
1b80043e JL	184	evt->shift = 32;
	185	evt->rating = 300;
	186	evt->set_next_event = armada_370_xp_clkevt_next_event;
d96f4412 VK	187	evt->set_state_shutdown = armada_370_xp_clkevt_shutdown;
	188	evt->set_state_periodic = armada_370_xp_clkevt_set_periodic;
	189	evt->set_state_oneshot = armada_370_xp_clkevt_shutdown;
	190	evt->tick_resume = armada_370_xp_clkevt_shutdown;
5ddb6d21	191	evt->irq = armada_370_xp_clkevt_irq;
ddd3f69f GC	192	evt->cpumask = cpumask_of(cpu);
ddd3f69f GC	193
ddd3f69f GC	194	clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
	195	enable_percpu_irq(evt->irq, 0);
	196
	197	return 0;
	198	}
	199
2c48fef7	200	static int armada_370_xp_timer_dying_cpu(unsigned int cpu)
ddd3f69f	201	{
2c48fef7 RC	202	struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
2c48fef7 RC	203
d96f4412	204	evt->set_state_shutdown(evt);
ddd3f69f	205	disable_percpu_irq(evt->irq);
2c48fef7	206	return 0;
ddd3f69f GC	207	}
ddd3f69f GC	208
f9a49ab5 TP	209	static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
	210
	211	static int armada_370_xp_timer_suspend(void)
	212	{
	213	timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
	214	timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
	215	return 0;
	216	}
	217
	218	static void armada_370_xp_timer_resume(void)
	219	{
	220	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	221	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
	222	writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
	223	writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
	224	}
	225
2c436e46	226	static struct syscore_ops armada_370_xp_timer_syscore_ops = {
f9a49ab5 TP	227	.suspend = armada_370_xp_timer_suspend,
	228	.resume = armada_370_xp_timer_resume,
	229	};
	230
cb0f2538 RK	231	static unsigned long armada_370_delay_timer_read(void)
	232	{
	233	return ~readl(timer_base + TIMER0_VAL_OFF);
	234	}
	235
	236	static struct delay_timer armada_370_delay_timer = {
	237	.read_current_timer = armada_370_delay_timer_read,
	238	};
	239
12549e27	240	static int __init armada_370_xp_timer_common_init(struct device_node *np)
6fe9cbd1	241	{
3579698e	242	u32 clr = 0, set = 0;
ddd3f69f GC	243	int res;
ddd3f69f GC	244
6fe9cbd1	245	timer_base = of_iomap(np, 0);
12549e27	246	if (!timer_base) {
ac9ce6d1	247	pr_err("Failed to iomap\n");
12549e27 DL	248	return -ENXIO;
	249	}
	250
ddd3f69f	251	local_base = of_iomap(np, 1);
12549e27	252	if (!local_base) {
ac9ce6d1	253	pr_err("Failed to iomap\n");
12549e27 DL	254	return -ENXIO;
12549e27 DL	255	}
6fe9cbd1	256
08cb8e46	257	if (timer25Mhz) {
a4ae54f9	258	set = TIMER0_25MHZ;
08cb8e46 EG	259	enable_mask = TIMER0_EN;
08cb8e46 EG	260	} else {
3579698e	261	clr = TIMER0_25MHZ;
08cb8e46 EG	262	enable_mask = TIMER0_EN \| TIMER0_DIV(TIMER_DIVIDER_SHIFT);
08cb8e46 EG	263	}
c8af34b4	264	atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr \| set, set);
3579698e	265	local_timer_ctrl_clrset(clr, set);
6fe9cbd1	266
ddd3f69f GC	267	/*
	268	* We use timer 0 as clocksource, and private(local) timer 0
	269	* for clockevents
	270	*/
5ddb6d21	271	armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
6fe9cbd1 GC	272
	273	ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
	274
6fe9cbd1 GC	275	/*
	276	* Setup free-running clocksource timer (interrupts
	277	* disabled).
	278	*/
	279	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	280	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
	281
c8af34b4 EG	282	atomic_io_modify(timer_base + TIMER_CTRL_OFF,
	283	TIMER0_RELOAD_EN \| enable_mask,
	284	TIMER0_RELOAD_EN \| enable_mask);
6fe9cbd1	285
cb0f2538 RK	286	armada_370_delay_timer.freq = timer_clk;
	287	register_current_timer_delay(&armada_370_delay_timer);
	288
c813eff0 EG	289	/*
	290	* Set scale and timer for sched_clock.
	291	*/
	292	sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
	293
12549e27 DL	294	res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
	295	"armada_370_xp_clocksource",
	296	timer_clk, 300, 32, clocksource_mmio_readl_down);
	297	if (res) {
ac9ce6d1	298	pr_err("Failed to initialize clocksource mmio\n");
12549e27 DL	299	return res;
12549e27 DL	300	}
6fe9cbd1	301
5ddb6d21	302	armada_370_xp_evt = alloc_percpu(struct clock_event_device);
12549e27 DL	303	if (!armada_370_xp_evt)
12549e27 DL	304	return -ENOMEM;
ddd3f69f GC	305
	306	/*
	307	* Setup clockevent timer (interrupt-driven).
	308	*/
5ddb6d21	309	res = request_percpu_irq(armada_370_xp_clkevt_irq,
ddd3f69f	310	armada_370_xp_timer_interrupt,
5ddb6d21 SB	311	"armada_370_xp_per_cpu_tick",
	312	armada_370_xp_evt);
	313	/* Immediately configure the timer on the boot CPU */
12549e27	314	if (res) {
ac9ce6d1	315	pr_err("Failed to request percpu irq\n");
12549e27 DL	316	return res;
	317	}
	318
2c48fef7	319	res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
73c1b41e	320	"clockevents/armada:starting",
2c48fef7 RC	321	armada_370_xp_timer_starting_cpu,
2c48fef7 RC	322	armada_370_xp_timer_dying_cpu);
1d661bf5	323	if (res) {
ac9ce6d1	324	pr_err("Failed to setup hotplug state and timer\n");
12549e27 DL	325	return res;
12549e27 DL	326	}
f9a49ab5 TP	327
f9a49ab5 TP	328	register_syscore_ops(&armada_370_xp_timer_syscore_ops);
12549e27 DL	329
12549e27 DL	330	return 0;
ddd3f69f	331	}
7cd6392c	332
12549e27	333	static int __init armada_xp_timer_init(struct device_node *np)
7cd6392c	334	{
5e9fe6cb	335	struct clk *clk = of_clk_get_by_name(np, "fixed");
12549e27 DL	336	int ret;
12549e27 DL	337
12549e27	338	if (IS_ERR(clk)) {
ac9ce6d1	339	pr_err("Failed to get clock\n");
12549e27 DL	340	return PTR_ERR(clk);
	341	}
	342
	343	ret = clk_prepare_enable(clk);
	344	if (ret)
	345	return ret;
5e9fe6cb	346
5e9fe6cb	347	timer_clk = clk_get_rate(clk);
7cd6392c	348
12549e27	349	return armada_370_xp_timer_common_init(np);
7cd6392c	350	}
17273395	351	TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
7cd6392c EG	352	armada_xp_timer_init);
7cd6392c EG	353
12549e27	354	static int __init armada_375_timer_init(struct device_node *np)
4a22d9c9 EG	355	{
4a22d9c9 EG	356	struct clk *clk;
12549e27	357	int ret;
4a22d9c9 EG	358
	359	clk = of_clk_get_by_name(np, "fixed");
	360	if (!IS_ERR(clk)) {
12549e27 DL	361	ret = clk_prepare_enable(clk);
	362	if (ret)
	363	return ret;
4a22d9c9 EG	364	timer_clk = clk_get_rate(clk);
	365	} else {
	366
	367	/*
	368	* This fallback is required in order to retain proper
	369	* devicetree backwards compatibility.
	370	*/
	371	clk = of_clk_get(np, 0);
	372
	373	/* Must have at least a clock */
12549e27	374	if (IS_ERR(clk)) {
ac9ce6d1	375	pr_err("Failed to get clock\n");
12549e27 DL	376	return PTR_ERR(clk);
	377	}
	378
	379	ret = clk_prepare_enable(clk);
	380	if (ret)
	381	return ret;
	382
4a22d9c9 EG	383	timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
	384	timer25Mhz = false;
	385	}
	386
12549e27	387	return armada_370_xp_timer_common_init(np);
4a22d9c9	388	}
17273395	389	TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",
4a22d9c9 EG	390	armada_375_timer_init);
4a22d9c9 EG	391
12549e27	392	static int __init armada_370_timer_init(struct device_node *np)
7cd6392c	393	{
12549e27 DL	394	struct clk *clk;
	395	int ret;
	396
	397	clk = of_clk_get(np, 0);
	398	if (IS_ERR(clk)) {
ac9ce6d1	399	pr_err("Failed to get clock\n");
12549e27 DL	400	return PTR_ERR(clk);
	401	}
	402
	403	ret = clk_prepare_enable(clk);
	404	if (ret)
	405	return ret;
7cd6392c	406
7cd6392c EG	407	timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
	408	timer25Mhz = false;
	409
12549e27	410	return armada_370_xp_timer_common_init(np);
ddd3f69f	411	}
17273395	412	TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",
7cd6392c	413	armada_370_timer_init);