[linux-2.6-block.git] / drivers / clocksource / time-orion.c

/*
 * Marvell Orion SoC timer handling.
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Timer 0 is used as free-running clocksource, while timer 1 is
 * used as clock_event_device.
 */

#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/spinlock.h>
#include <linux/sched_clock.h>

#define TIMER_CTRL		0x00
#define  TIMER0_EN		BIT(0)
#define  TIMER0_RELOAD_EN	BIT(1)
#define  TIMER1_EN		BIT(2)
#define  TIMER1_RELOAD_EN	BIT(3)
#define TIMER0_RELOAD		0x10
#define TIMER0_VAL		0x14
#define TIMER1_RELOAD		0x18
#define TIMER1_VAL		0x1c

#define ORION_ONESHOT_MIN	1
#define ORION_ONESHOT_MAX	0xfffffffe

static void __iomem *timer_base;

static unsigned long notrace orion_read_timer(void)
{
	return ~readl(timer_base + TIMER0_VAL);
}

static struct delay_timer orion_delay_timer = {
	.read_current_timer = orion_read_timer,
};

static void orion_delay_timer_init(unsigned long rate)
{
	orion_delay_timer.freq = rate;
	register_current_timer_delay(&orion_delay_timer);
}

/*
 * Free-running clocksource handling.
 */
static u64 notrace orion_read_sched_clock(void)
{
	return ~readl(timer_base + TIMER0_VAL);
}

/*
 * Clockevent handling.
 */
static u32 ticks_per_jiffy;

static int orion_clkevt_next_event(unsigned long delta,
				   struct clock_event_device *dev)
{
	/* setup and enable one-shot timer */
	writel(delta, timer_base + TIMER1_VAL);
	atomic_io_modify(timer_base + TIMER_CTRL,
		TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_EN);

	return 0;
}

static int orion_clkevt_shutdown(struct clock_event_device *dev)
{
	/* disable timer */
	atomic_io_modify(timer_base + TIMER_CTRL,
			 TIMER1_RELOAD_EN | TIMER1_EN, 0);
	return 0;
}

static int orion_clkevt_set_periodic(struct clock_event_device *dev)
{
	/* setup and enable periodic timer at 1/HZ intervals */
	writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
	writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
	atomic_io_modify(timer_base + TIMER_CTRL,
			 TIMER1_RELOAD_EN | TIMER1_EN,
			 TIMER1_RELOAD_EN | TIMER1_EN);
	return 0;
}

static struct clock_event_device orion_clkevt = {
	.name			= "orion_event",
	.features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_PERIODIC,
	.shift			= 32,
	.rating			= 300,
	.set_next_event		= orion_clkevt_next_event,
	.set_state_shutdown	= orion_clkevt_shutdown,
	.set_state_periodic	= orion_clkevt_set_periodic,
	.set_state_oneshot	= orion_clkevt_shutdown,
	.tick_resume		= orion_clkevt_shutdown,
};

static irqreturn_t orion_clkevt_irq_handler(int irq, void *dev_id)
{
	orion_clkevt.event_handler(&orion_clkevt);
	return IRQ_HANDLED;
}

static struct irqaction orion_clkevt_irq = {
	.name		= "orion_event",
	.flags		= IRQF_TIMER,
	.handler	= orion_clkevt_irq_handler,
};

static int __init orion_timer_init(struct device_node *np)
{
	unsigned long rate;
	struct clk *clk;
	int irq, ret;

	/* timer registers are shared with watchdog timer */
	timer_base = of_iomap(np, 0);
	if (!timer_base) {
		pr_err("%s: unable to map resource\n", np->name);
		return -ENXIO;
	}

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("%s: unable to get clk\n", np->name);
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("Failed to prepare clock\n");
		return ret;
	}

	/* we are only interested in timer1 irq */
	irq = irq_of_parse_and_map(np, 1);
	if (irq <= 0) {
		pr_err("%s: unable to parse timer1 irq\n", np->name);
		return -EINVAL;
	}

	rate = clk_get_rate(clk);

	/* setup timer0 as free-running clocksource */
	writel(~0, timer_base + TIMER0_VAL);
	writel(~0, timer_base + TIMER0_RELOAD);
	atomic_io_modify(timer_base + TIMER_CTRL,
		TIMER0_RELOAD_EN | TIMER0_EN,
		TIMER0_RELOAD_EN | TIMER0_EN);

	ret = clocksource_mmio_init(timer_base + TIMER0_VAL,
				    "orion_clocksource", rate, 300, 32,
				    clocksource_mmio_readl_down);
	if (ret) {
		pr_err("Failed to initialize mmio timer\n");
		return ret;
	}

	sched_clock_register(orion_read_sched_clock, 32, rate);

	/* setup timer1 as clockevent timer */
	ret = setup_irq(irq, &orion_clkevt_irq);
	if (ret) {
		pr_err("%s: unable to setup irq\n", np->name);
		return ret;
	}

	ticks_per_jiffy = (clk_get_rate(clk) + HZ/2) / HZ;
	orion_clkevt.cpumask = cpumask_of(0);
	orion_clkevt.irq = irq;
	clockevents_config_and_register(&orion_clkevt, rate,
					ORION_ONESHOT_MIN, ORION_ONESHOT_MAX);


	orion_delay_timer_init(rate);

	return 0;
}
CLOCKSOURCE_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);
Commit	Line	Data
0c1dcfd5 SH	1	/*
	2	* Marvell Orion SoC timer handling.
	3	*
	4	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*
	10	* Timer 0 is used as free-running clocksource, while timer 1 is
	11	* used as clock_event_device.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/bitops.h>
	16	#include <linux/clk.h>
	17	#include <linux/clockchips.h>
9a4914ce	18	#include <linux/delay.h>
0c1dcfd5 SH	19	#include <linux/interrupt.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/spinlock.h>
19b0a1e5	23	#include <linux/sched_clock.h>
0c1dcfd5 SH	24
	25	#define TIMER_CTRL 0x00
	26	#define TIMER0_EN BIT(0)
	27	#define TIMER0_RELOAD_EN BIT(1)
	28	#define TIMER1_EN BIT(2)
	29	#define TIMER1_RELOAD_EN BIT(3)
	30	#define TIMER0_RELOAD 0x10
	31	#define TIMER0_VAL 0x14
	32	#define TIMER1_RELOAD 0x18
	33	#define TIMER1_VAL 0x1c
	34
	35	#define ORION_ONESHOT_MIN 1
	36	#define ORION_ONESHOT_MAX 0xfffffffe
	37
	38	static void __iomem *timer_base;
0c1dcfd5	39
9a4914ce RK	40	static unsigned long notrace orion_read_timer(void)
	41	{
	42	return ~readl(timer_base + TIMER0_VAL);
	43	}
	44
	45	static struct delay_timer orion_delay_timer = {
	46	.read_current_timer = orion_read_timer,
	47	};
	48
	49	static void orion_delay_timer_init(unsigned long rate)
	50	{
	51	orion_delay_timer.freq = rate;
	52	register_current_timer_delay(&orion_delay_timer);
	53	}
	54
0c1dcfd5 SH	55	/*
	56	* Free-running clocksource handling.
	57	*/
2e8bac53	58	static u64 notrace orion_read_sched_clock(void)
0c1dcfd5 SH	59	{
	60	return ~readl(timer_base + TIMER0_VAL);
	61	}
	62
	63	/*
	64	* Clockevent handling.
	65	*/
	66	static u32 ticks_per_jiffy;
	67
	68	static int orion_clkevt_next_event(unsigned long delta,
	69	struct clock_event_device *dev)
	70	{
	71	/* setup and enable one-shot timer */
	72	writel(delta, timer_base + TIMER1_VAL);
0a54a069 EG	73	atomic_io_modify(timer_base + TIMER_CTRL,
0a54a069 EG	74	TIMER1_RELOAD_EN \| TIMER1_EN, TIMER1_EN);
0c1dcfd5 SH	75
	76	return 0;
	77	}
	78
5dd2482c	79	static int orion_clkevt_shutdown(struct clock_event_device *dev)
0c1dcfd5	80	{
5dd2482c VK	81	/* disable timer */
	82	atomic_io_modify(timer_base + TIMER_CTRL,
	83	TIMER1_RELOAD_EN \| TIMER1_EN, 0);
	84	return 0;
	85	}
	86
	87	static int orion_clkevt_set_periodic(struct clock_event_device *dev)
	88	{
	89	/* setup and enable periodic timer at 1/HZ intervals */
	90	writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
	91	writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
	92	atomic_io_modify(timer_base + TIMER_CTRL,
	93	TIMER1_RELOAD_EN \| TIMER1_EN,
	94	TIMER1_RELOAD_EN \| TIMER1_EN);
	95	return 0;
0c1dcfd5 SH	96	}
	97
	98	static struct clock_event_device orion_clkevt = {
5dd2482c VK	99	.name = "orion_event",
	100	.features = CLOCK_EVT_FEAT_ONESHOT \|
	101	CLOCK_EVT_FEAT_PERIODIC,
	102	.shift = 32,
	103	.rating = 300,
	104	.set_next_event = orion_clkevt_next_event,
	105	.set_state_shutdown = orion_clkevt_shutdown,
	106	.set_state_periodic = orion_clkevt_set_periodic,
	107	.set_state_oneshot = orion_clkevt_shutdown,
	108	.tick_resume = orion_clkevt_shutdown,
0c1dcfd5 SH	109	};
	110
	111	static irqreturn_t orion_clkevt_irq_handler(int irq, void *dev_id)
	112	{
	113	orion_clkevt.event_handler(&orion_clkevt);
	114	return IRQ_HANDLED;
	115	}
	116
	117	static struct irqaction orion_clkevt_irq = {
	118	.name = "orion_event",
	119	.flags = IRQF_TIMER,
	120	.handler = orion_clkevt_irq_handler,
	121	};
	122
fbe4b356	123	static int __init orion_timer_init(struct device_node *np)
0c1dcfd5	124	{
0d9298ea	125	unsigned long rate;
0c1dcfd5	126	struct clk *clk;
fbe4b356	127	int irq, ret;
0c1dcfd5 SH	128
	129	/* timer registers are shared with watchdog timer */
	130	timer_base = of_iomap(np, 0);
fbe4b356 DL	131	if (!timer_base) {
	132	pr_err("%s: unable to map resource\n", np->name);
	133	return -ENXIO;
	134	}
0c1dcfd5 SH	135
0c1dcfd5 SH	136	clk = of_clk_get(np, 0);
fbe4b356 DL	137	if (IS_ERR(clk)) {
	138	pr_err("%s: unable to get clk\n", np->name);
	139	return PTR_ERR(clk);
	140	}
	141
	142	ret = clk_prepare_enable(clk);
	143	if (ret) {
ac9ce6d1	144	pr_err("Failed to prepare clock\n");
fbe4b356 DL	145	return ret;
fbe4b356 DL	146	}
0c1dcfd5 SH	147
	148	/* we are only interested in timer1 irq */
	149	irq = irq_of_parse_and_map(np, 1);
fbe4b356 DL	150	if (irq <= 0) {
	151	pr_err("%s: unable to parse timer1 irq\n", np->name);
	152	return -EINVAL;
	153	}
0c1dcfd5	154
0d9298ea RK	155	rate = clk_get_rate(clk);
0d9298ea RK	156
0c1dcfd5 SH	157	/* setup timer0 as free-running clocksource */
	158	writel(~0, timer_base + TIMER0_VAL);
	159	writel(~0, timer_base + TIMER0_RELOAD);
0a54a069 EG	160	atomic_io_modify(timer_base + TIMER_CTRL,
	161	TIMER0_RELOAD_EN \| TIMER0_EN,
	162	TIMER0_RELOAD_EN \| TIMER0_EN);
fbe4b356	163
0d9298ea RK	164	ret = clocksource_mmio_init(timer_base + TIMER0_VAL,
0d9298ea RK	165	"orion_clocksource", rate, 300, 32,
fbe4b356 DL	166	clocksource_mmio_readl_down);
fbe4b356 DL	167	if (ret) {
ac9ce6d1	168	pr_err("Failed to initialize mmio timer\n");
fbe4b356 DL	169	return ret;
	170	}
	171
0d9298ea	172	sched_clock_register(orion_read_sched_clock, 32, rate);
0c1dcfd5 SH	173
0c1dcfd5 SH	174	/* setup timer1 as clockevent timer */
fbe4b356 DL	175	ret = setup_irq(irq, &orion_clkevt_irq);
	176	if (ret) {
	177	pr_err("%s: unable to setup irq\n", np->name);
	178	return ret;
	179	}
0c1dcfd5 SH	180
	181	ticks_per_jiffy = (clk_get_rate(clk) + HZ/2) / HZ;
	182	orion_clkevt.cpumask = cpumask_of(0);
	183	orion_clkevt.irq = irq;
0d9298ea	184	clockevents_config_and_register(&orion_clkevt, rate,
0c1dcfd5	185	ORION_ONESHOT_MIN, ORION_ONESHOT_MAX);
fbe4b356	186
9a4914ce RK	187
	188	orion_delay_timer_init(rate);
	189
fbe4b356	190	return 0;
0c1dcfd5	191	}
177cf6e5	192	CLOCKSOURCE_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);