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b2ac5d75 MR |
1 | /* |
2 | * Allwinner A1X SoCs timer handling. | |
3 | * | |
4 | * Copyright (C) 2012 Maxime Ripard | |
5 | * | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * Based on code from | |
9 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
10 | * Benn Huang <benn@allwinnertech.com> | |
11 | * | |
12 | * This file is licensed under the terms of the GNU General Public | |
13 | * License version 2. This program is licensed "as is" without any | |
14 | * warranty of any kind, whether express or implied. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/clockchips.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/irqreturn.h> | |
137c6b3c | 22 | #include <linux/sched_clock.h> |
b2ac5d75 MR |
23 | #include <linux/of.h> |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_irq.h> | |
b2ac5d75 | 26 | |
04981731 | 27 | #define TIMER_IRQ_EN_REG 0x00 |
40777645 | 28 | #define TIMER_IRQ_EN(val) BIT(val) |
b2ac5d75 | 29 | #define TIMER_IRQ_ST_REG 0x04 |
04981731 | 30 | #define TIMER_CTL_REG(val) (0x10 * val + 0x10) |
40777645 | 31 | #define TIMER_CTL_ENABLE BIT(0) |
9eded232 | 32 | #define TIMER_CTL_RELOAD BIT(1) |
40777645 | 33 | #define TIMER_CTL_ONESHOT BIT(7) |
bb008b9e MR |
34 | #define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14) |
35 | #define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18) | |
b2ac5d75 MR |
36 | |
37 | #define TIMER_SCAL 16 | |
38 | ||
39 | static void __iomem *timer_base; | |
40 | ||
119fd635 | 41 | static void sun4i_clkevt_mode(enum clock_event_mode mode, |
b2ac5d75 MR |
42 | struct clock_event_device *clk) |
43 | { | |
04981731 | 44 | u32 u = readl(timer_base + TIMER_CTL_REG(0)); |
b2ac5d75 MR |
45 | |
46 | switch (mode) { | |
47 | case CLOCK_EVT_MODE_PERIODIC: | |
04981731 MR |
48 | u &= ~(TIMER_CTL_ONESHOT); |
49 | writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0)); | |
b2ac5d75 MR |
50 | break; |
51 | ||
52 | case CLOCK_EVT_MODE_ONESHOT: | |
04981731 | 53 | writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0)); |
b2ac5d75 MR |
54 | break; |
55 | case CLOCK_EVT_MODE_UNUSED: | |
56 | case CLOCK_EVT_MODE_SHUTDOWN: | |
57 | default: | |
04981731 | 58 | writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0)); |
b2ac5d75 MR |
59 | break; |
60 | } | |
61 | } | |
62 | ||
119fd635 | 63 | static int sun4i_clkevt_next_event(unsigned long evt, |
b2ac5d75 MR |
64 | struct clock_event_device *unused) |
65 | { | |
04981731 MR |
66 | u32 u = readl(timer_base + TIMER_CTL_REG(0)); |
67 | writel(evt, timer_base + TIMER_CNTVAL_REG(0)); | |
68 | writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD, | |
69 | timer_base + TIMER_CTL_REG(0)); | |
b2ac5d75 MR |
70 | |
71 | return 0; | |
72 | } | |
73 | ||
119fd635 MR |
74 | static struct clock_event_device sun4i_clockevent = { |
75 | .name = "sun4i_tick", | |
b2ac5d75 MR |
76 | .rating = 300, |
77 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
119fd635 MR |
78 | .set_mode = sun4i_clkevt_mode, |
79 | .set_next_event = sun4i_clkevt_next_event, | |
b2ac5d75 MR |
80 | }; |
81 | ||
82 | ||
119fd635 | 83 | static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id) |
b2ac5d75 MR |
84 | { |
85 | struct clock_event_device *evt = (struct clock_event_device *)dev_id; | |
86 | ||
87 | writel(0x1, timer_base + TIMER_IRQ_ST_REG); | |
88 | evt->event_handler(evt); | |
89 | ||
90 | return IRQ_HANDLED; | |
91 | } | |
92 | ||
119fd635 MR |
93 | static struct irqaction sun4i_timer_irq = { |
94 | .name = "sun4i_timer0", | |
b2ac5d75 | 95 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
119fd635 MR |
96 | .handler = sun4i_timer_interrupt, |
97 | .dev_id = &sun4i_clockevent, | |
b2ac5d75 MR |
98 | }; |
99 | ||
137c6b3c MR |
100 | static u32 sun4i_timer_sched_read(void) |
101 | { | |
102 | return ~readl(timer_base + TIMER_CNTVAL_REG(1)); | |
103 | } | |
104 | ||
119fd635 | 105 | static void __init sun4i_timer_init(struct device_node *node) |
b2ac5d75 | 106 | { |
b2ac5d75 MR |
107 | unsigned long rate = 0; |
108 | struct clk *clk; | |
109 | int ret, irq; | |
110 | u32 val; | |
111 | ||
b2ac5d75 MR |
112 | timer_base = of_iomap(node, 0); |
113 | if (!timer_base) | |
114 | panic("Can't map registers"); | |
115 | ||
116 | irq = irq_of_parse_and_map(node, 0); | |
117 | if (irq <= 0) | |
118 | panic("Can't parse IRQ"); | |
119 | ||
b2ac5d75 MR |
120 | clk = of_clk_get(node, 0); |
121 | if (IS_ERR(clk)) | |
122 | panic("Can't get timer clock"); | |
8c31bec2 | 123 | clk_prepare_enable(clk); |
b2ac5d75 MR |
124 | |
125 | rate = clk_get_rate(clk); | |
126 | ||
137c6b3c MR |
127 | writel(~0, timer_base + TIMER_INTVAL_REG(1)); |
128 | writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | | |
129 | TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), | |
130 | timer_base + TIMER_CTL_REG(1)); | |
131 | ||
132 | setup_sched_clock(sun4i_timer_sched_read, 32, rate); | |
133 | clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name, | |
134 | rate, 300, 32, clocksource_mmio_readl_down); | |
135 | ||
b2ac5d75 | 136 | writel(rate / (TIMER_SCAL * HZ), |
04981731 | 137 | timer_base + TIMER_INTVAL_REG(0)); |
b2ac5d75 MR |
138 | |
139 | /* set clock source to HOSC, 16 pre-division */ | |
04981731 | 140 | val = readl(timer_base + TIMER_CTL_REG(0)); |
b2ac5d75 MR |
141 | val &= ~(0x07 << 4); |
142 | val &= ~(0x03 << 2); | |
143 | val |= (4 << 4) | (1 << 2); | |
04981731 | 144 | writel(val, timer_base + TIMER_CTL_REG(0)); |
b2ac5d75 MR |
145 | |
146 | /* set mode to auto reload */ | |
04981731 | 147 | val = readl(timer_base + TIMER_CTL_REG(0)); |
9eded232 | 148 | writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0)); |
b2ac5d75 | 149 | |
119fd635 | 150 | ret = setup_irq(irq, &sun4i_timer_irq); |
b2ac5d75 MR |
151 | if (ret) |
152 | pr_warn("failed to setup irq %d\n", irq); | |
153 | ||
154 | /* Enable timer0 interrupt */ | |
04981731 MR |
155 | val = readl(timer_base + TIMER_IRQ_EN_REG); |
156 | writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG); | |
b2ac5d75 | 157 | |
119fd635 | 158 | sun4i_clockevent.cpumask = cpumask_of(0); |
b2ac5d75 | 159 | |
119fd635 | 160 | clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL, |
77cc982f | 161 | 0x1, 0xff); |
b2ac5d75 | 162 | } |
119fd635 MR |
163 | CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer", |
164 | sun4i_timer_init); |