Commit | Line | Data |
---|---|---|
9570ef20 MD |
1 | /* |
2 | * SuperH Timer Support - TMU | |
3 | * | |
4 | * Copyright (C) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/clocksource.h> | |
31 | #include <linux/clockchips.h> | |
46a12f74 | 32 | #include <linux/sh_timer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
7deeab5d | 34 | #include <linux/module.h> |
2ee619f9 | 35 | #include <linux/pm_domain.h> |
eaa49a8c | 36 | #include <linux/pm_runtime.h> |
9570ef20 | 37 | |
0a72aa39 | 38 | struct sh_tmu_device; |
de2d12c7 LP |
39 | |
40 | struct sh_tmu_channel { | |
0a72aa39 | 41 | struct sh_tmu_device *tmu; |
fe68eb80 | 42 | unsigned int index; |
de2d12c7 | 43 | |
de693461 | 44 | void __iomem *base; |
1c56cf6b | 45 | int irq; |
de2d12c7 | 46 | |
9570ef20 MD |
47 | unsigned long rate; |
48 | unsigned long periodic; | |
49 | struct clock_event_device ced; | |
50 | struct clocksource cs; | |
eaa49a8c | 51 | bool cs_enabled; |
61a53bfa | 52 | unsigned int enable_count; |
9570ef20 MD |
53 | }; |
54 | ||
0a72aa39 | 55 | struct sh_tmu_device { |
de2d12c7 LP |
56 | struct platform_device *pdev; |
57 | ||
58 | void __iomem *mapbase; | |
59 | struct clk *clk; | |
60 | ||
a5de49f4 LP |
61 | struct sh_tmu_channel *channels; |
62 | unsigned int num_channels; | |
de2d12c7 LP |
63 | }; |
64 | ||
c2225a57 | 65 | static DEFINE_RAW_SPINLOCK(sh_tmu_lock); |
9570ef20 MD |
66 | |
67 | #define TSTR -1 /* shared register */ | |
68 | #define TCOR 0 /* channel register */ | |
69 | #define TCNT 1 /* channel register */ | |
70 | #define TCR 2 /* channel register */ | |
71 | ||
5cfe2d15 LP |
72 | #define TCR_UNF (1 << 8) |
73 | #define TCR_UNIE (1 << 5) | |
74 | #define TCR_TPSC_CLK4 (0 << 0) | |
75 | #define TCR_TPSC_CLK16 (1 << 0) | |
76 | #define TCR_TPSC_CLK64 (2 << 0) | |
77 | #define TCR_TPSC_CLK256 (3 << 0) | |
78 | #define TCR_TPSC_CLK1024 (4 << 0) | |
79 | #define TCR_TPSC_MASK (7 << 0) | |
80 | ||
de2d12c7 | 81 | static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) |
9570ef20 | 82 | { |
9570ef20 MD |
83 | unsigned long offs; |
84 | ||
85 | if (reg_nr == TSTR) | |
de693461 | 86 | return ioread8(ch->tmu->mapbase); |
9570ef20 MD |
87 | |
88 | offs = reg_nr << 2; | |
89 | ||
90 | if (reg_nr == TCR) | |
de693461 | 91 | return ioread16(ch->base + offs); |
9570ef20 | 92 | else |
de693461 | 93 | return ioread32(ch->base + offs); |
9570ef20 MD |
94 | } |
95 | ||
de2d12c7 | 96 | static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, |
9570ef20 MD |
97 | unsigned long value) |
98 | { | |
9570ef20 MD |
99 | unsigned long offs; |
100 | ||
101 | if (reg_nr == TSTR) { | |
de693461 | 102 | iowrite8(value, ch->tmu->mapbase); |
9570ef20 MD |
103 | return; |
104 | } | |
105 | ||
106 | offs = reg_nr << 2; | |
107 | ||
108 | if (reg_nr == TCR) | |
de693461 | 109 | iowrite16(value, ch->base + offs); |
9570ef20 | 110 | else |
de693461 | 111 | iowrite32(value, ch->base + offs); |
9570ef20 MD |
112 | } |
113 | ||
de2d12c7 | 114 | static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) |
9570ef20 | 115 | { |
9570ef20 MD |
116 | unsigned long flags, value; |
117 | ||
118 | /* start stop register shared by multiple timer channels */ | |
c2225a57 | 119 | raw_spin_lock_irqsave(&sh_tmu_lock, flags); |
de2d12c7 | 120 | value = sh_tmu_read(ch, TSTR); |
9570ef20 MD |
121 | |
122 | if (start) | |
fe68eb80 | 123 | value |= 1 << ch->index; |
9570ef20 | 124 | else |
fe68eb80 | 125 | value &= ~(1 << ch->index); |
9570ef20 | 126 | |
de2d12c7 | 127 | sh_tmu_write(ch, TSTR, value); |
c2225a57 | 128 | raw_spin_unlock_irqrestore(&sh_tmu_lock, flags); |
9570ef20 MD |
129 | } |
130 | ||
de2d12c7 | 131 | static int __sh_tmu_enable(struct sh_tmu_channel *ch) |
9570ef20 | 132 | { |
9570ef20 MD |
133 | int ret; |
134 | ||
d4905ce3 | 135 | /* enable clock */ |
de2d12c7 | 136 | ret = clk_enable(ch->tmu->clk); |
9570ef20 | 137 | if (ret) { |
fe68eb80 LP |
138 | dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", |
139 | ch->index); | |
9570ef20 MD |
140 | return ret; |
141 | } | |
142 | ||
143 | /* make sure channel is disabled */ | |
de2d12c7 | 144 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 MD |
145 | |
146 | /* maximum timeout */ | |
de2d12c7 LP |
147 | sh_tmu_write(ch, TCOR, 0xffffffff); |
148 | sh_tmu_write(ch, TCNT, 0xffffffff); | |
9570ef20 MD |
149 | |
150 | /* configure channel to parent clock / 4, irq off */ | |
de2d12c7 | 151 | ch->rate = clk_get_rate(ch->tmu->clk) / 4; |
5cfe2d15 | 152 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
9570ef20 MD |
153 | |
154 | /* enable channel */ | |
de2d12c7 | 155 | sh_tmu_start_stop_ch(ch, 1); |
9570ef20 MD |
156 | |
157 | return 0; | |
158 | } | |
159 | ||
de2d12c7 | 160 | static int sh_tmu_enable(struct sh_tmu_channel *ch) |
61a53bfa | 161 | { |
de2d12c7 | 162 | if (ch->enable_count++ > 0) |
61a53bfa RW |
163 | return 0; |
164 | ||
de2d12c7 LP |
165 | pm_runtime_get_sync(&ch->tmu->pdev->dev); |
166 | dev_pm_syscore_device(&ch->tmu->pdev->dev, true); | |
61a53bfa | 167 | |
de2d12c7 | 168 | return __sh_tmu_enable(ch); |
61a53bfa RW |
169 | } |
170 | ||
de2d12c7 | 171 | static void __sh_tmu_disable(struct sh_tmu_channel *ch) |
9570ef20 MD |
172 | { |
173 | /* disable channel */ | |
de2d12c7 | 174 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 | 175 | |
be890a1a | 176 | /* disable interrupts in TMU block */ |
5cfe2d15 | 177 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
be890a1a | 178 | |
d4905ce3 | 179 | /* stop clock */ |
de2d12c7 | 180 | clk_disable(ch->tmu->clk); |
9570ef20 MD |
181 | } |
182 | ||
de2d12c7 | 183 | static void sh_tmu_disable(struct sh_tmu_channel *ch) |
61a53bfa | 184 | { |
de2d12c7 | 185 | if (WARN_ON(ch->enable_count == 0)) |
61a53bfa RW |
186 | return; |
187 | ||
de2d12c7 | 188 | if (--ch->enable_count > 0) |
61a53bfa RW |
189 | return; |
190 | ||
de2d12c7 | 191 | __sh_tmu_disable(ch); |
61a53bfa | 192 | |
de2d12c7 LP |
193 | dev_pm_syscore_device(&ch->tmu->pdev->dev, false); |
194 | pm_runtime_put(&ch->tmu->pdev->dev); | |
61a53bfa RW |
195 | } |
196 | ||
de2d12c7 | 197 | static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, |
9570ef20 MD |
198 | int periodic) |
199 | { | |
200 | /* stop timer */ | |
de2d12c7 | 201 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 MD |
202 | |
203 | /* acknowledge interrupt */ | |
de2d12c7 | 204 | sh_tmu_read(ch, TCR); |
9570ef20 MD |
205 | |
206 | /* enable interrupt */ | |
5cfe2d15 | 207 | sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
9570ef20 MD |
208 | |
209 | /* reload delta value in case of periodic timer */ | |
210 | if (periodic) | |
de2d12c7 | 211 | sh_tmu_write(ch, TCOR, delta); |
9570ef20 | 212 | else |
de2d12c7 | 213 | sh_tmu_write(ch, TCOR, 0xffffffff); |
9570ef20 | 214 | |
de2d12c7 | 215 | sh_tmu_write(ch, TCNT, delta); |
9570ef20 MD |
216 | |
217 | /* start timer */ | |
de2d12c7 | 218 | sh_tmu_start_stop_ch(ch, 1); |
9570ef20 MD |
219 | } |
220 | ||
221 | static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) | |
222 | { | |
de2d12c7 | 223 | struct sh_tmu_channel *ch = dev_id; |
9570ef20 MD |
224 | |
225 | /* disable or acknowledge interrupt */ | |
de2d12c7 | 226 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) |
5cfe2d15 | 227 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
9570ef20 | 228 | else |
5cfe2d15 | 229 | sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
9570ef20 MD |
230 | |
231 | /* notify clockevent layer */ | |
de2d12c7 | 232 | ch->ced.event_handler(&ch->ced); |
9570ef20 MD |
233 | return IRQ_HANDLED; |
234 | } | |
235 | ||
de2d12c7 | 236 | static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) |
9570ef20 | 237 | { |
de2d12c7 | 238 | return container_of(cs, struct sh_tmu_channel, cs); |
9570ef20 MD |
239 | } |
240 | ||
241 | static cycle_t sh_tmu_clocksource_read(struct clocksource *cs) | |
242 | { | |
de2d12c7 | 243 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
9570ef20 | 244 | |
de2d12c7 | 245 | return sh_tmu_read(ch, TCNT) ^ 0xffffffff; |
9570ef20 MD |
246 | } |
247 | ||
248 | static int sh_tmu_clocksource_enable(struct clocksource *cs) | |
249 | { | |
de2d12c7 | 250 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
0aeac458 | 251 | int ret; |
9570ef20 | 252 | |
de2d12c7 | 253 | if (WARN_ON(ch->cs_enabled)) |
61a53bfa RW |
254 | return 0; |
255 | ||
de2d12c7 | 256 | ret = sh_tmu_enable(ch); |
eaa49a8c | 257 | if (!ret) { |
de2d12c7 LP |
258 | __clocksource_updatefreq_hz(cs, ch->rate); |
259 | ch->cs_enabled = true; | |
eaa49a8c | 260 | } |
61a53bfa | 261 | |
0aeac458 | 262 | return ret; |
9570ef20 MD |
263 | } |
264 | ||
265 | static void sh_tmu_clocksource_disable(struct clocksource *cs) | |
266 | { | |
de2d12c7 | 267 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 268 | |
de2d12c7 | 269 | if (WARN_ON(!ch->cs_enabled)) |
61a53bfa | 270 | return; |
eaa49a8c | 271 | |
de2d12c7 LP |
272 | sh_tmu_disable(ch); |
273 | ch->cs_enabled = false; | |
eaa49a8c RW |
274 | } |
275 | ||
276 | static void sh_tmu_clocksource_suspend(struct clocksource *cs) | |
277 | { | |
de2d12c7 | 278 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 279 | |
de2d12c7 | 280 | if (!ch->cs_enabled) |
61a53bfa | 281 | return; |
eaa49a8c | 282 | |
de2d12c7 LP |
283 | if (--ch->enable_count == 0) { |
284 | __sh_tmu_disable(ch); | |
285 | pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev); | |
61a53bfa | 286 | } |
eaa49a8c RW |
287 | } |
288 | ||
289 | static void sh_tmu_clocksource_resume(struct clocksource *cs) | |
290 | { | |
de2d12c7 | 291 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 292 | |
de2d12c7 | 293 | if (!ch->cs_enabled) |
61a53bfa RW |
294 | return; |
295 | ||
de2d12c7 LP |
296 | if (ch->enable_count++ == 0) { |
297 | pm_genpd_syscore_poweron(&ch->tmu->pdev->dev); | |
298 | __sh_tmu_enable(ch); | |
61a53bfa | 299 | } |
9570ef20 MD |
300 | } |
301 | ||
de2d12c7 | 302 | static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, |
f1010ed1 | 303 | const char *name) |
9570ef20 | 304 | { |
de2d12c7 | 305 | struct clocksource *cs = &ch->cs; |
9570ef20 MD |
306 | |
307 | cs->name = name; | |
f1010ed1 | 308 | cs->rating = 200; |
9570ef20 MD |
309 | cs->read = sh_tmu_clocksource_read; |
310 | cs->enable = sh_tmu_clocksource_enable; | |
311 | cs->disable = sh_tmu_clocksource_disable; | |
eaa49a8c RW |
312 | cs->suspend = sh_tmu_clocksource_suspend; |
313 | cs->resume = sh_tmu_clocksource_resume; | |
9570ef20 MD |
314 | cs->mask = CLOCKSOURCE_MASK(32); |
315 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
66f49121 | 316 | |
fe68eb80 LP |
317 | dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", |
318 | ch->index); | |
0aeac458 MD |
319 | |
320 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ | |
321 | clocksource_register_hz(cs, 1); | |
9570ef20 MD |
322 | return 0; |
323 | } | |
324 | ||
de2d12c7 | 325 | static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) |
9570ef20 | 326 | { |
de2d12c7 | 327 | return container_of(ced, struct sh_tmu_channel, ced); |
9570ef20 MD |
328 | } |
329 | ||
de2d12c7 | 330 | static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) |
9570ef20 | 331 | { |
de2d12c7 | 332 | struct clock_event_device *ced = &ch->ced; |
9570ef20 | 333 | |
de2d12c7 | 334 | sh_tmu_enable(ch); |
9570ef20 | 335 | |
de2d12c7 | 336 | clockevents_config(ced, ch->rate); |
9570ef20 MD |
337 | |
338 | if (periodic) { | |
de2d12c7 LP |
339 | ch->periodic = (ch->rate + HZ/2) / HZ; |
340 | sh_tmu_set_next(ch, ch->periodic, 1); | |
9570ef20 MD |
341 | } |
342 | } | |
343 | ||
344 | static void sh_tmu_clock_event_mode(enum clock_event_mode mode, | |
345 | struct clock_event_device *ced) | |
346 | { | |
de2d12c7 | 347 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
9570ef20 MD |
348 | int disabled = 0; |
349 | ||
350 | /* deal with old setting first */ | |
351 | switch (ced->mode) { | |
352 | case CLOCK_EVT_MODE_PERIODIC: | |
353 | case CLOCK_EVT_MODE_ONESHOT: | |
de2d12c7 | 354 | sh_tmu_disable(ch); |
9570ef20 MD |
355 | disabled = 1; |
356 | break; | |
357 | default: | |
358 | break; | |
359 | } | |
360 | ||
361 | switch (mode) { | |
362 | case CLOCK_EVT_MODE_PERIODIC: | |
de2d12c7 | 363 | dev_info(&ch->tmu->pdev->dev, |
fe68eb80 | 364 | "ch%u: used for periodic clock events\n", ch->index); |
de2d12c7 | 365 | sh_tmu_clock_event_start(ch, 1); |
9570ef20 MD |
366 | break; |
367 | case CLOCK_EVT_MODE_ONESHOT: | |
de2d12c7 | 368 | dev_info(&ch->tmu->pdev->dev, |
fe68eb80 | 369 | "ch%u: used for oneshot clock events\n", ch->index); |
de2d12c7 | 370 | sh_tmu_clock_event_start(ch, 0); |
9570ef20 MD |
371 | break; |
372 | case CLOCK_EVT_MODE_UNUSED: | |
373 | if (!disabled) | |
de2d12c7 | 374 | sh_tmu_disable(ch); |
9570ef20 MD |
375 | break; |
376 | case CLOCK_EVT_MODE_SHUTDOWN: | |
377 | default: | |
378 | break; | |
379 | } | |
380 | } | |
381 | ||
382 | static int sh_tmu_clock_event_next(unsigned long delta, | |
383 | struct clock_event_device *ced) | |
384 | { | |
de2d12c7 | 385 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
9570ef20 MD |
386 | |
387 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
388 | ||
389 | /* program new delta value */ | |
de2d12c7 | 390 | sh_tmu_set_next(ch, delta, 0); |
9570ef20 MD |
391 | return 0; |
392 | } | |
393 | ||
eaa49a8c RW |
394 | static void sh_tmu_clock_event_suspend(struct clock_event_device *ced) |
395 | { | |
de2d12c7 | 396 | pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
eaa49a8c RW |
397 | } |
398 | ||
399 | static void sh_tmu_clock_event_resume(struct clock_event_device *ced) | |
400 | { | |
de2d12c7 | 401 | pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
eaa49a8c RW |
402 | } |
403 | ||
de2d12c7 | 404 | static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, |
f1010ed1 | 405 | const char *name) |
9570ef20 | 406 | { |
de2d12c7 | 407 | struct clock_event_device *ced = &ch->ced; |
9570ef20 MD |
408 | int ret; |
409 | ||
9570ef20 MD |
410 | ced->name = name; |
411 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
412 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
f1010ed1 | 413 | ced->rating = 200; |
9570ef20 MD |
414 | ced->cpumask = cpumask_of(0); |
415 | ced->set_next_event = sh_tmu_clock_event_next; | |
416 | ced->set_mode = sh_tmu_clock_event_mode; | |
eaa49a8c RW |
417 | ced->suspend = sh_tmu_clock_event_suspend; |
418 | ced->resume = sh_tmu_clock_event_resume; | |
9570ef20 | 419 | |
fe68eb80 LP |
420 | dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", |
421 | ch->index); | |
3977407e PM |
422 | |
423 | clockevents_config_and_register(ced, 1, 0x300, 0xffffffff); | |
da64c2a8 | 424 | |
de2d12c7 | 425 | ret = request_irq(ch->irq, sh_tmu_interrupt, |
1c56cf6b | 426 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, |
de2d12c7 | 427 | dev_name(&ch->tmu->pdev->dev), ch); |
9570ef20 | 428 | if (ret) { |
fe68eb80 LP |
429 | dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", |
430 | ch->index, ch->irq); | |
9570ef20 MD |
431 | return; |
432 | } | |
9570ef20 MD |
433 | } |
434 | ||
84876d05 | 435 | static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, |
f1010ed1 | 436 | bool clockevent, bool clocksource) |
9570ef20 | 437 | { |
f1010ed1 LP |
438 | if (clockevent) |
439 | sh_tmu_register_clockevent(ch, name); | |
440 | else if (clocksource) | |
441 | sh_tmu_register_clocksource(ch, name); | |
9570ef20 MD |
442 | |
443 | return 0; | |
444 | } | |
445 | ||
a94ddaa6 LP |
446 | static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, |
447 | struct sh_tmu_device *tmu) | |
448 | { | |
449 | struct sh_timer_config *cfg = tmu->pdev->dev.platform_data; | |
450 | ||
a94ddaa6 LP |
451 | ch->tmu = tmu; |
452 | ||
fe68eb80 LP |
453 | /* |
454 | * The SH3 variant (SH770x, SH7705, SH7710 and SH7720) maps channel | |
455 | * registers blocks at base + 2 + 12 * index, while all other variants | |
456 | * map them at base + 4 + 12 * index. We can compute the index by just | |
457 | * dividing by 12, the 2 bytes or 4 bytes offset being hidden by the | |
458 | * integer division. | |
459 | */ | |
460 | ch->index = cfg->channel_offset / 12; | |
461 | ||
a94ddaa6 LP |
462 | ch->irq = platform_get_irq(tmu->pdev, 0); |
463 | if (ch->irq < 0) { | |
fe68eb80 LP |
464 | dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n", |
465 | ch->index); | |
a94ddaa6 LP |
466 | return ch->irq; |
467 | } | |
468 | ||
469 | ch->cs_enabled = false; | |
470 | ch->enable_count = 0; | |
471 | ||
84876d05 | 472 | return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), |
f1010ed1 LP |
473 | cfg->clockevent_rating != 0, |
474 | cfg->clocksource_rating != 0); | |
a94ddaa6 LP |
475 | } |
476 | ||
0a72aa39 | 477 | static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) |
9570ef20 | 478 | { |
46a12f74 | 479 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
9570ef20 | 480 | struct resource *res; |
a5de49f4 | 481 | void __iomem *base; |
1c56cf6b | 482 | int ret; |
9570ef20 MD |
483 | ret = -ENXIO; |
484 | ||
0a72aa39 | 485 | tmu->pdev = pdev; |
9570ef20 MD |
486 | |
487 | if (!cfg) { | |
0a72aa39 | 488 | dev_err(&tmu->pdev->dev, "missing platform data\n"); |
9570ef20 MD |
489 | goto err0; |
490 | } | |
491 | ||
0a72aa39 | 492 | platform_set_drvdata(pdev, tmu); |
9570ef20 | 493 | |
0a72aa39 | 494 | res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); |
9570ef20 | 495 | if (!res) { |
0a72aa39 | 496 | dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); |
9570ef20 MD |
497 | goto err0; |
498 | } | |
499 | ||
de693461 | 500 | /* |
a5de49f4 | 501 | * Map memory, let base point to our channel and mapbase to the |
de693461 LP |
502 | * start/stop shared register. |
503 | */ | |
a5de49f4 LP |
504 | base = ioremap_nocache(res->start, resource_size(res)); |
505 | if (base == NULL) { | |
0a72aa39 | 506 | dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); |
9570ef20 MD |
507 | goto err0; |
508 | } | |
509 | ||
a5de49f4 | 510 | tmu->mapbase = base - cfg->channel_offset; |
de693461 | 511 | |
9570ef20 | 512 | /* get hold of clock */ |
0a72aa39 LP |
513 | tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck"); |
514 | if (IS_ERR(tmu->clk)) { | |
515 | dev_err(&tmu->pdev->dev, "cannot get clock\n"); | |
516 | ret = PTR_ERR(tmu->clk); | |
03ff858c | 517 | goto err1; |
9570ef20 | 518 | } |
1c09eb3e | 519 | |
0a72aa39 | 520 | ret = clk_prepare(tmu->clk); |
1c09eb3e LP |
521 | if (ret < 0) |
522 | goto err2; | |
523 | ||
a5de49f4 LP |
524 | tmu->channels = kzalloc(sizeof(*tmu->channels), GFP_KERNEL); |
525 | if (tmu->channels == NULL) { | |
526 | ret = -ENOMEM; | |
527 | goto err3; | |
528 | } | |
529 | ||
530 | tmu->num_channels = 1; | |
531 | ||
532 | tmu->channels[0].base = base; | |
533 | ||
534 | ret = sh_tmu_channel_setup(&tmu->channels[0], tmu); | |
394a4486 | 535 | if (ret < 0) |
1c09eb3e | 536 | goto err3; |
394a4486 LP |
537 | |
538 | return 0; | |
539 | ||
1c09eb3e | 540 | err3: |
a5de49f4 | 541 | kfree(tmu->channels); |
0a72aa39 | 542 | clk_unprepare(tmu->clk); |
394a4486 | 543 | err2: |
0a72aa39 | 544 | clk_put(tmu->clk); |
9570ef20 | 545 | err1: |
a5de49f4 | 546 | iounmap(base); |
9570ef20 MD |
547 | err0: |
548 | return ret; | |
549 | } | |
550 | ||
1850514b | 551 | static int sh_tmu_probe(struct platform_device *pdev) |
9570ef20 | 552 | { |
0a72aa39 | 553 | struct sh_tmu_device *tmu = platform_get_drvdata(pdev); |
61a53bfa | 554 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
9570ef20 MD |
555 | int ret; |
556 | ||
eaa49a8c | 557 | if (!is_early_platform_device(pdev)) { |
61a53bfa RW |
558 | pm_runtime_set_active(&pdev->dev); |
559 | pm_runtime_enable(&pdev->dev); | |
eaa49a8c | 560 | } |
2ee619f9 | 561 | |
0a72aa39 | 562 | if (tmu) { |
214a607a | 563 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
61a53bfa | 564 | goto out; |
9570ef20 MD |
565 | } |
566 | ||
3b77a83e | 567 | tmu = kzalloc(sizeof(*tmu), GFP_KERNEL); |
0a72aa39 | 568 | if (tmu == NULL) { |
9570ef20 MD |
569 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
570 | return -ENOMEM; | |
571 | } | |
572 | ||
0a72aa39 | 573 | ret = sh_tmu_setup(tmu, pdev); |
9570ef20 | 574 | if (ret) { |
0a72aa39 | 575 | kfree(tmu); |
61a53bfa RW |
576 | pm_runtime_idle(&pdev->dev); |
577 | return ret; | |
9570ef20 | 578 | } |
61a53bfa RW |
579 | if (is_early_platform_device(pdev)) |
580 | return 0; | |
581 | ||
582 | out: | |
583 | if (cfg->clockevent_rating || cfg->clocksource_rating) | |
584 | pm_runtime_irq_safe(&pdev->dev); | |
585 | else | |
586 | pm_runtime_idle(&pdev->dev); | |
587 | ||
588 | return 0; | |
9570ef20 MD |
589 | } |
590 | ||
1850514b | 591 | static int sh_tmu_remove(struct platform_device *pdev) |
9570ef20 MD |
592 | { |
593 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
594 | } | |
595 | ||
596 | static struct platform_driver sh_tmu_device_driver = { | |
597 | .probe = sh_tmu_probe, | |
1850514b | 598 | .remove = sh_tmu_remove, |
9570ef20 MD |
599 | .driver = { |
600 | .name = "sh_tmu", | |
601 | } | |
602 | }; | |
603 | ||
604 | static int __init sh_tmu_init(void) | |
605 | { | |
606 | return platform_driver_register(&sh_tmu_device_driver); | |
607 | } | |
608 | ||
609 | static void __exit sh_tmu_exit(void) | |
610 | { | |
611 | platform_driver_unregister(&sh_tmu_device_driver); | |
612 | } | |
613 | ||
614 | early_platform_init("earlytimer", &sh_tmu_device_driver); | |
b9773c3f | 615 | subsys_initcall(sh_tmu_init); |
9570ef20 MD |
616 | module_exit(sh_tmu_exit); |
617 | ||
618 | MODULE_AUTHOR("Magnus Damm"); | |
619 | MODULE_DESCRIPTION("SuperH TMU Timer Driver"); | |
620 | MODULE_LICENSE("GPL v2"); |