[linux-block.git] / drivers / clocksource / sh_tmu.c

/*
 * SuperH Timer Support - TMU
 *
 *  Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

struct sh_tmu_priv {
	void __iomem *mapbase;
	struct clk *clk;
	struct irqaction irqaction;
	struct platform_device *pdev;
	unsigned long rate;
	unsigned long periodic;
	struct clock_event_device ced;
	struct clocksource cs;
	bool cs_enabled;
};

static DEFINE_RAW_SPINLOCK(sh_tmu_lock);

#define TSTR -1 /* shared register */
#define TCOR  0 /* channel register */
#define TCNT 1 /* channel register */
#define TCR 2 /* channel register */

static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == TSTR)
		return ioread8(base - cfg->channel_offset);

	offs = reg_nr << 2;

	if (reg_nr == TCR)
		return ioread16(base + offs);
	else
		return ioread32(base + offs);
}

static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
				unsigned long value)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == TSTR) {
		iowrite8(value, base - cfg->channel_offset);
		return;
	}

	offs = reg_nr << 2;

	if (reg_nr == TCR)
		iowrite16(value, base + offs);
	else
		iowrite32(value, base + offs);
}

static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	raw_spin_lock_irqsave(&sh_tmu_lock, flags);
	value = sh_tmu_read(p, TSTR);

	if (start)
		value |= 1 << cfg->timer_bit;
	else
		value &= ~(1 << cfg->timer_bit);

	sh_tmu_write(p, TSTR, value);
	raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
}

static int sh_tmu_enable(struct sh_tmu_priv *p)
{
	int ret;

	/* enable clock */
	ret = clk_enable(p->clk);
	if (ret) {
		dev_err(&p->pdev->dev, "cannot enable clock\n");
		return ret;
	}

	/* make sure channel is disabled */
	sh_tmu_start_stop_ch(p, 0);

	/* maximum timeout */
	sh_tmu_write(p, TCOR, 0xffffffff);
	sh_tmu_write(p, TCNT, 0xffffffff);

	/* configure channel to parent clock / 4, irq off */
	p->rate = clk_get_rate(p->clk) / 4;
	sh_tmu_write(p, TCR, 0x0000);

	/* enable channel */
	sh_tmu_start_stop_ch(p, 1);

	return 0;
}

static void sh_tmu_disable(struct sh_tmu_priv *p)
{
	/* disable channel */
	sh_tmu_start_stop_ch(p, 0);

	/* disable interrupts in TMU block */
	sh_tmu_write(p, TCR, 0x0000);

	/* stop clock */
	clk_disable(p->clk);
}

static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
			    int periodic)
{
	/* stop timer */
	sh_tmu_start_stop_ch(p, 0);

	/* acknowledge interrupt */
	sh_tmu_read(p, TCR);

	/* enable interrupt */
	sh_tmu_write(p, TCR, 0x0020);

	/* reload delta value in case of periodic timer */
	if (periodic)
		sh_tmu_write(p, TCOR, delta);
	else
		sh_tmu_write(p, TCOR, 0xffffffff);

	sh_tmu_write(p, TCNT, delta);

	/* start timer */
	sh_tmu_start_stop_ch(p, 1);
}

static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
{
	struct sh_tmu_priv *p = dev_id;

	/* disable or acknowledge interrupt */
	if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
		sh_tmu_write(p, TCR, 0x0000);
	else
		sh_tmu_write(p, TCR, 0x0020);

	/* notify clockevent layer */
	p->ced.event_handler(&p->ced);
	return IRQ_HANDLED;
}

static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
{
	return container_of(cs, struct sh_tmu_priv, cs);
}

static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	return sh_tmu_read(p, TCNT) ^ 0xffffffff;
}

static int sh_tmu_clocksource_enable(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	int ret;

	ret = sh_tmu_enable(p);
	if (!ret) {
		__clocksource_updatefreq_hz(cs, p->rate);
		p->cs_enabled = true;
	}
	return ret;
}

static void sh_tmu_clocksource_disable(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	WARN_ON(!p->cs_enabled);

	sh_tmu_disable(p);
	p->cs_enabled = false;
}

static void sh_tmu_clocksource_suspend(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	if (p->cs_enabled)
		sh_tmu_disable(p);

	pm_genpd_syscore_poweroff(&p->pdev->dev);
}

static void sh_tmu_clocksource_resume(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	pm_genpd_syscore_poweron(&p->pdev->dev);
	if (p->cs_enabled)
		sh_tmu_enable(p);
}

static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
				       char *name, unsigned long rating)
{
	struct clocksource *cs = &p->cs;

	cs->name = name;
	cs->rating = rating;
	cs->read = sh_tmu_clocksource_read;
	cs->enable = sh_tmu_clocksource_enable;
	cs->disable = sh_tmu_clocksource_disable;
	cs->suspend = sh_tmu_clocksource_suspend;
	cs->resume = sh_tmu_clocksource_resume;
	cs->mask = CLOCKSOURCE_MASK(32);
	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;

	dev_info(&p->pdev->dev, "used as clock source\n");

	/* Register with dummy 1 Hz value, gets updated in ->enable() */
	clocksource_register_hz(cs, 1);
	return 0;
}

static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
{
	return container_of(ced, struct sh_tmu_priv, ced);
}

static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
{
	struct clock_event_device *ced = &p->ced;

	sh_tmu_enable(p);

	clockevents_config(ced, p->rate);

	if (periodic) {
		p->periodic = (p->rate + HZ/2) / HZ;
		sh_tmu_set_next(p, p->periodic, 1);
	}
}

static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
				    struct clock_event_device *ced)
{
	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	int disabled = 0;

	/* deal with old setting first */
	switch (ced->mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		sh_tmu_disable(p);
		disabled = 1;
		break;
	default:
		break;
	}

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		dev_info(&p->pdev->dev, "used for periodic clock events\n");
		sh_tmu_clock_event_start(p, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		dev_info(&p->pdev->dev, "used for oneshot clock events\n");
		sh_tmu_clock_event_start(p, 0);
		break;
	case CLOCK_EVT_MODE_UNUSED:
		if (!disabled)
			sh_tmu_disable(p);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		break;
	}
}

static int sh_tmu_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);

	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);

	/* program new delta value */
	sh_tmu_set_next(p, delta, 0);
	return 0;
}

static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
{
	pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->pdev->dev);
}

static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
{
	pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->pdev->dev);
}

static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
				       char *name, unsigned long rating)
{
	struct clock_event_device *ced = &p->ced;
	int ret;

	memset(ced, 0, sizeof(*ced));

	ced->name = name;
	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	ced->features |= CLOCK_EVT_FEAT_ONESHOT;
	ced->rating = rating;
	ced->cpumask = cpumask_of(0);
	ced->set_next_event = sh_tmu_clock_event_next;
	ced->set_mode = sh_tmu_clock_event_mode;
	ced->suspend = sh_tmu_clock_event_suspend;
	ced->resume = sh_tmu_clock_event_resume;

	dev_info(&p->pdev->dev, "used for clock events\n");

	clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);

	ret = setup_irq(p->irqaction.irq, &p->irqaction);
	if (ret) {
		dev_err(&p->pdev->dev, "failed to request irq %d\n",
			p->irqaction.irq);
		return;
	}
}

static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
		    unsigned long clockevent_rating,
		    unsigned long clocksource_rating)
{
	if (clockevent_rating)
		sh_tmu_register_clockevent(p, name, clockevent_rating);
	else if (clocksource_rating)
		sh_tmu_register_clocksource(p, name, clocksource_rating);

	return 0;
}

static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
{
	struct sh_timer_config *cfg = pdev->dev.platform_data;
	struct resource *res;
	int irq, ret;
	ret = -ENXIO;

	memset(p, 0, sizeof(*p));
	p->pdev = pdev;

	if (!cfg) {
		dev_err(&p->pdev->dev, "missing platform data\n");
		goto err0;
	}

	platform_set_drvdata(pdev, p);

	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&p->pdev->dev, "failed to get I/O memory\n");
		goto err0;
	}

	irq = platform_get_irq(p->pdev, 0);
	if (irq < 0) {
		dev_err(&p->pdev->dev, "failed to get irq\n");
		goto err0;
	}

	/* map memory, let mapbase point to our channel */
	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	if (p->mapbase == NULL) {
		dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
		goto err0;
	}

	/* setup data for setup_irq() (too early for request_irq()) */
	p->irqaction.name = dev_name(&p->pdev->dev);
	p->irqaction.handler = sh_tmu_interrupt;
	p->irqaction.dev_id = p;
	p->irqaction.irq = irq;
	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
			     IRQF_IRQPOLL  | IRQF_NOBALANCING;

	/* get hold of clock */
	p->clk = clk_get(&p->pdev->dev, "tmu_fck");
	if (IS_ERR(p->clk)) {
		dev_err(&p->pdev->dev, "cannot get clock\n");
		ret = PTR_ERR(p->clk);
		goto err1;
	}

	return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
			       cfg->clockevent_rating,
			       cfg->clocksource_rating);
 err1:
	iounmap(p->mapbase);
 err0:
	return ret;
}

static int __devinit sh_tmu_probe(struct platform_device *pdev)
{
	struct sh_tmu_priv *p = platform_get_drvdata(pdev);
	int ret;

	if (!is_early_platform_device(pdev)) {
		struct sh_timer_config *cfg = pdev->dev.platform_data;

		if (cfg->clocksource_rating || cfg->clockevent_rating)
			dev_pm_syscore_device(&pdev->dev, true);
	}

	if (p) {
		dev_info(&pdev->dev, "kept as earlytimer\n");
		return 0;
	}

	p = kmalloc(sizeof(*p), GFP_KERNEL);
	if (p == NULL) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		return -ENOMEM;
	}

	ret = sh_tmu_setup(p, pdev);
	if (ret) {
		kfree(p);
		platform_set_drvdata(pdev, NULL);
	}
	return ret;
}

static int __devexit sh_tmu_remove(struct platform_device *pdev)
{
	return -EBUSY; /* cannot unregister clockevent and clocksource */
}

static struct platform_driver sh_tmu_device_driver = {
	.probe		= sh_tmu_probe,
	.remove		= __devexit_p(sh_tmu_remove),
	.driver		= {
		.name	= "sh_tmu",
	}
};

static int __init sh_tmu_init(void)
{
	return platform_driver_register(&sh_tmu_device_driver);
}

static void __exit sh_tmu_exit(void)
{
	platform_driver_unregister(&sh_tmu_device_driver);
}

early_platform_init("earlytimer", &sh_tmu_device_driver);
module_init(sh_tmu_init);
module_exit(sh_tmu_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH TMU Timer Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9570ef20 MD	1	/*
	2	* SuperH Timer Support - TMU
	3	*
	4	* Copyright (C) 2009 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/delay.h>
	26	#include <linux/io.h>
	27	#include <linux/clk.h>
	28	#include <linux/irq.h>
	29	#include <linux/err.h>
	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
46a12f74	32	#include <linux/sh_timer.h>
5a0e3ad6	33	#include <linux/slab.h>
7deeab5d	34	#include <linux/module.h>
2ee619f9	35	#include <linux/pm_domain.h>
eaa49a8c	36	#include <linux/pm_runtime.h>
9570ef20 MD	37
	38	struct sh_tmu_priv {
	39	void __iomem *mapbase;
	40	struct clk *clk;
	41	struct irqaction irqaction;
	42	struct platform_device *pdev;
	43	unsigned long rate;
	44	unsigned long periodic;
	45	struct clock_event_device ced;
	46	struct clocksource cs;
eaa49a8c	47	bool cs_enabled;
9570ef20 MD	48	};
9570ef20 MD	49
c2225a57	50	static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
9570ef20 MD	51
	52	#define TSTR -1 /* shared register */
	53	#define TCOR 0 /* channel register */
	54	#define TCNT 1 /* channel register */
	55	#define TCR 2 /* channel register */
	56
	57	static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
	58	{
46a12f74	59	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	60	void __iomem *base = p->mapbase;
	61	unsigned long offs;
	62
	63	if (reg_nr == TSTR)
	64	return ioread8(base - cfg->channel_offset);
	65
	66	offs = reg_nr << 2;
	67
	68	if (reg_nr == TCR)
	69	return ioread16(base + offs);
	70	else
	71	return ioread32(base + offs);
	72	}
	73
	74	static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
	75	unsigned long value)
	76	{
46a12f74	77	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	78	void __iomem *base = p->mapbase;
	79	unsigned long offs;
	80
	81	if (reg_nr == TSTR) {
	82	iowrite8(value, base - cfg->channel_offset);
	83	return;
	84	}
	85
	86	offs = reg_nr << 2;
	87
	88	if (reg_nr == TCR)
	89	iowrite16(value, base + offs);
	90	else
	91	iowrite32(value, base + offs);
	92	}
	93
	94	static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
	95	{
46a12f74	96	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	97	unsigned long flags, value;
	98
	99	/* start stop register shared by multiple timer channels */
c2225a57	100	raw_spin_lock_irqsave(&sh_tmu_lock, flags);
9570ef20 MD	101	value = sh_tmu_read(p, TSTR);
	102
	103	if (start)
	104	value \|= 1 << cfg->timer_bit;
	105	else
	106	value &= ~(1 << cfg->timer_bit);
	107
	108	sh_tmu_write(p, TSTR, value);
c2225a57	109	raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
9570ef20 MD	110	}
	111
	112	static int sh_tmu_enable(struct sh_tmu_priv *p)
	113	{
9570ef20 MD	114	int ret;
9570ef20 MD	115
d4905ce3	116	/* enable clock */
9570ef20 MD	117	ret = clk_enable(p->clk);
9570ef20 MD	118	if (ret) {
214a607a	119	dev_err(&p->pdev->dev, "cannot enable clock\n");
9570ef20 MD	120	return ret;
	121	}
	122
	123	/* make sure channel is disabled */
	124	sh_tmu_start_stop_ch(p, 0);
	125
	126	/* maximum timeout */
	127	sh_tmu_write(p, TCOR, 0xffffffff);
	128	sh_tmu_write(p, TCNT, 0xffffffff);
	129
	130	/* configure channel to parent clock / 4, irq off */
	131	p->rate = clk_get_rate(p->clk) / 4;
	132	sh_tmu_write(p, TCR, 0x0000);
	133
	134	/* enable channel */
	135	sh_tmu_start_stop_ch(p, 1);
	136
	137	return 0;
	138	}
	139
	140	static void sh_tmu_disable(struct sh_tmu_priv *p)
	141	{
	142	/* disable channel */
	143	sh_tmu_start_stop_ch(p, 0);
	144
be890a1a MD	145	/* disable interrupts in TMU block */
	146	sh_tmu_write(p, TCR, 0x0000);
	147
d4905ce3	148	/* stop clock */
9570ef20 MD	149	clk_disable(p->clk);
	150	}
	151
	152	static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
	153	int periodic)
	154	{
	155	/* stop timer */
	156	sh_tmu_start_stop_ch(p, 0);
	157
	158	/* acknowledge interrupt */
	159	sh_tmu_read(p, TCR);
	160
	161	/* enable interrupt */
	162	sh_tmu_write(p, TCR, 0x0020);
	163
	164	/* reload delta value in case of periodic timer */
	165	if (periodic)
	166	sh_tmu_write(p, TCOR, delta);
	167	else
6f4b67b8	168	sh_tmu_write(p, TCOR, 0xffffffff);
9570ef20 MD	169
	170	sh_tmu_write(p, TCNT, delta);
	171
	172	/* start timer */
	173	sh_tmu_start_stop_ch(p, 1);
	174	}
	175
	176	static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
	177	{
	178	struct sh_tmu_priv *p = dev_id;
	179
	180	/* disable or acknowledge interrupt */
	181	if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
	182	sh_tmu_write(p, TCR, 0x0000);
	183	else
	184	sh_tmu_write(p, TCR, 0x0020);
	185
	186	/* notify clockevent layer */
	187	p->ced.event_handler(&p->ced);
	188	return IRQ_HANDLED;
	189	}
	190
	191	static struct sh_tmu_priv cs_to_sh_tmu(struct clocksource cs)
	192	{
	193	return container_of(cs, struct sh_tmu_priv, cs);
	194	}
	195
	196	static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
	197	{
	198	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	199
	200	return sh_tmu_read(p, TCNT) ^ 0xffffffff;
	201	}
	202
	203	static int sh_tmu_clocksource_enable(struct clocksource *cs)
	204	{
	205	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
0aeac458	206	int ret;
9570ef20	207
0aeac458	208	ret = sh_tmu_enable(p);
eaa49a8c	209	if (!ret) {
0aeac458	210	__clocksource_updatefreq_hz(cs, p->rate);
eaa49a8c RW	211	p->cs_enabled = true;
eaa49a8c RW	212	}
0aeac458	213	return ret;
9570ef20 MD	214	}
	215
	216	static void sh_tmu_clocksource_disable(struct clocksource *cs)
	217	{
eaa49a8c RW	218	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	219
	220	WARN_ON(!p->cs_enabled);
	221
	222	sh_tmu_disable(p);
	223	p->cs_enabled = false;
	224	}
	225
	226	static void sh_tmu_clocksource_suspend(struct clocksource *cs)
	227	{
	228	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	229
	230	if (p->cs_enabled)
	231	sh_tmu_disable(p);
	232
	233	pm_genpd_syscore_poweroff(&p->pdev->dev);
	234	}
	235
	236	static void sh_tmu_clocksource_resume(struct clocksource *cs)
	237	{
	238	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	239
	240	pm_genpd_syscore_poweron(&p->pdev->dev);
	241	if (p->cs_enabled)
	242	sh_tmu_enable(p);
9570ef20 MD	243	}
	244
	245	static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
	246	char *name, unsigned long rating)
	247	{
	248	struct clocksource *cs = &p->cs;
	249
	250	cs->name = name;
	251	cs->rating = rating;
	252	cs->read = sh_tmu_clocksource_read;
	253	cs->enable = sh_tmu_clocksource_enable;
	254	cs->disable = sh_tmu_clocksource_disable;
eaa49a8c RW	255	cs->suspend = sh_tmu_clocksource_suspend;
eaa49a8c RW	256	cs->resume = sh_tmu_clocksource_resume;
9570ef20 MD	257	cs->mask = CLOCKSOURCE_MASK(32);
9570ef20 MD	258	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
66f49121	259
214a607a	260	dev_info(&p->pdev->dev, "used as clock source\n");
0aeac458 MD	261
	262	/* Register with dummy 1 Hz value, gets updated in ->enable() */
	263	clocksource_register_hz(cs, 1);
9570ef20 MD	264	return 0;
	265	}
	266
	267	static struct sh_tmu_priv ced_to_sh_tmu(struct clock_event_device ced)
	268	{
	269	return container_of(ced, struct sh_tmu_priv, ced);
	270	}
	271
	272	static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
	273	{
	274	struct clock_event_device *ced = &p->ced;
	275
	276	sh_tmu_enable(p);
	277
3977407e	278	clockevents_config(ced, p->rate);
9570ef20 MD	279
	280	if (periodic) {
	281	p->periodic = (p->rate + HZ/2) / HZ;
	282	sh_tmu_set_next(p, p->periodic, 1);
	283	}
	284	}
	285
	286	static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
	287	struct clock_event_device *ced)
	288	{
	289	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	290	int disabled = 0;
	291
	292	/* deal with old setting first */
	293	switch (ced->mode) {
	294	case CLOCK_EVT_MODE_PERIODIC:
	295	case CLOCK_EVT_MODE_ONESHOT:
	296	sh_tmu_disable(p);
	297	disabled = 1;
	298	break;
	299	default:
	300	break;
	301	}
	302
	303	switch (mode) {
	304	case CLOCK_EVT_MODE_PERIODIC:
214a607a	305	dev_info(&p->pdev->dev, "used for periodic clock events\n");
9570ef20 MD	306	sh_tmu_clock_event_start(p, 1);
	307	break;
	308	case CLOCK_EVT_MODE_ONESHOT:
214a607a	309	dev_info(&p->pdev->dev, "used for oneshot clock events\n");
9570ef20 MD	310	sh_tmu_clock_event_start(p, 0);
	311	break;
	312	case CLOCK_EVT_MODE_UNUSED:
	313	if (!disabled)
	314	sh_tmu_disable(p);
	315	break;
	316	case CLOCK_EVT_MODE_SHUTDOWN:
	317	default:
	318	break;
	319	}
	320	}
	321
	322	static int sh_tmu_clock_event_next(unsigned long delta,
	323	struct clock_event_device *ced)
	324	{
	325	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	326
	327	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
	328
	329	/* program new delta value */
	330	sh_tmu_set_next(p, delta, 0);
	331	return 0;
	332	}
	333
eaa49a8c RW	334	static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
	335	{
	336	pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->pdev->dev);
	337	}
	338
	339	static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
	340	{
	341	pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->pdev->dev);
	342	}
	343
9570ef20 MD	344	static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
	345	char *name, unsigned long rating)
	346	{
	347	struct clock_event_device *ced = &p->ced;
	348	int ret;
	349
	350	memset(ced, 0, sizeof(*ced));
	351
	352	ced->name = name;
	353	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	354	ced->features \|= CLOCK_EVT_FEAT_ONESHOT;
	355	ced->rating = rating;
	356	ced->cpumask = cpumask_of(0);
	357	ced->set_next_event = sh_tmu_clock_event_next;
	358	ced->set_mode = sh_tmu_clock_event_mode;
eaa49a8c RW	359	ced->suspend = sh_tmu_clock_event_suspend;
eaa49a8c RW	360	ced->resume = sh_tmu_clock_event_resume;
9570ef20	361
214a607a	362	dev_info(&p->pdev->dev, "used for clock events\n");
3977407e PM	363
3977407e PM	364	clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
da64c2a8	365
9570ef20 MD	366	ret = setup_irq(p->irqaction.irq, &p->irqaction);
9570ef20 MD	367	if (ret) {
214a607a PM	368	dev_err(&p->pdev->dev, "failed to request irq %d\n",
214a607a PM	369	p->irqaction.irq);
9570ef20 MD	370	return;
9570ef20 MD	371	}
9570ef20 MD	372	}
	373
	374	static int sh_tmu_register(struct sh_tmu_priv p, char name,
	375	unsigned long clockevent_rating,
	376	unsigned long clocksource_rating)
	377	{
	378	if (clockevent_rating)
	379	sh_tmu_register_clockevent(p, name, clockevent_rating);
	380	else if (clocksource_rating)
	381	sh_tmu_register_clocksource(p, name, clocksource_rating);
	382
	383	return 0;
	384	}
	385
	386	static int sh_tmu_setup(struct sh_tmu_priv p, struct platform_device pdev)
	387	{
46a12f74	388	struct sh_timer_config *cfg = pdev->dev.platform_data;
9570ef20 MD	389	struct resource *res;
	390	int irq, ret;
	391	ret = -ENXIO;
	392
	393	memset(p, 0, sizeof(*p));
	394	p->pdev = pdev;
	395
	396	if (!cfg) {
	397	dev_err(&p->pdev->dev, "missing platform data\n");
	398	goto err0;
	399	}
	400
	401	platform_set_drvdata(pdev, p);
	402
	403	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	404	if (!res) {
	405	dev_err(&p->pdev->dev, "failed to get I/O memory\n");
	406	goto err0;
	407	}
	408
	409	irq = platform_get_irq(p->pdev, 0);
	410	if (irq < 0) {
	411	dev_err(&p->pdev->dev, "failed to get irq\n");
	412	goto err0;
	413	}
	414
	415	/* map memory, let mapbase point to our channel */
	416	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	417	if (p->mapbase == NULL) {
214a607a	418	dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
9570ef20 MD	419	goto err0;
	420	}
	421
	422	/* setup data for setup_irq() (too early for request_irq()) */
214a607a	423	p->irqaction.name = dev_name(&p->pdev->dev);
9570ef20 MD	424	p->irqaction.handler = sh_tmu_interrupt;
	425	p->irqaction.dev_id = p;
	426	p->irqaction.irq = irq;
fecf066c PM	427	p->irqaction.flags = IRQF_DISABLED \| IRQF_TIMER \| \
fecf066c PM	428	IRQF_IRQPOLL \| IRQF_NOBALANCING;
9570ef20 MD	429
9570ef20 MD	430	/* get hold of clock */
c2a25e81	431	p->clk = clk_get(&p->pdev->dev, "tmu_fck");
9570ef20	432	if (IS_ERR(p->clk)) {
03ff858c MD	433	dev_err(&p->pdev->dev, "cannot get clock\n");
	434	ret = PTR_ERR(p->clk);
	435	goto err1;
9570ef20 MD	436	}
9570ef20 MD	437
214a607a	438	return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
9570ef20 MD	439	cfg->clockevent_rating,
	440	cfg->clocksource_rating);
	441	err1:
	442	iounmap(p->mapbase);
	443	err0:
	444	return ret;
	445	}
	446
	447	static int __devinit sh_tmu_probe(struct platform_device *pdev)
	448	{
	449	struct sh_tmu_priv *p = platform_get_drvdata(pdev);
9570ef20 MD	450	int ret;
9570ef20 MD	451
eaa49a8c RW	452	if (!is_early_platform_device(pdev)) {
	453	struct sh_timer_config *cfg = pdev->dev.platform_data;
	454
	455	if (cfg->clocksource_rating \|\| cfg->clockevent_rating)
dbf37414	456	dev_pm_syscore_device(&pdev->dev, true);
eaa49a8c	457	}
2ee619f9	458
9570ef20	459	if (p) {
214a607a	460	dev_info(&pdev->dev, "kept as earlytimer\n");
9570ef20 MD	461	return 0;
	462	}
	463
	464	p = kmalloc(sizeof(*p), GFP_KERNEL);
	465	if (p == NULL) {
	466	dev_err(&pdev->dev, "failed to allocate driver data\n");
	467	return -ENOMEM;
	468	}
	469
	470	ret = sh_tmu_setup(p, pdev);
	471	if (ret) {
	472	kfree(p);
	473	platform_set_drvdata(pdev, NULL);
	474	}
	475	return ret;
	476	}
	477
	478	static int __devexit sh_tmu_remove(struct platform_device *pdev)
	479	{
	480	return -EBUSY; /* cannot unregister clockevent and clocksource */
	481	}
	482
	483	static struct platform_driver sh_tmu_device_driver = {
	484	.probe = sh_tmu_probe,
	485	.remove = __devexit_p(sh_tmu_remove),
	486	.driver = {
	487	.name = "sh_tmu",
	488	}
	489	};
	490
	491	static int __init sh_tmu_init(void)
	492	{
	493	return platform_driver_register(&sh_tmu_device_driver);
	494	}
	495
	496	static void __exit sh_tmu_exit(void)
	497	{
	498	platform_driver_unregister(&sh_tmu_device_driver);
	499	}
	500
	501	early_platform_init("earlytimer", &sh_tmu_device_driver);
	502	module_init(sh_tmu_init);
	503	module_exit(sh_tmu_exit);
	504
	505	MODULE_AUTHOR("Magnus Damm");
	506	MODULE_DESCRIPTION("SuperH TMU Timer Driver");
	507	MODULE_LICENSE("GPL v2");