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9570ef20 MD |
1 | /* |
2 | * SuperH Timer Support - TMU | |
3 | * | |
4 | * Copyright (C) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/clocksource.h> | |
31 | #include <linux/clockchips.h> | |
46a12f74 | 32 | #include <linux/sh_timer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
9570ef20 MD |
34 | |
35 | struct sh_tmu_priv { | |
36 | void __iomem *mapbase; | |
37 | struct clk *clk; | |
38 | struct irqaction irqaction; | |
39 | struct platform_device *pdev; | |
40 | unsigned long rate; | |
41 | unsigned long periodic; | |
42 | struct clock_event_device ced; | |
43 | struct clocksource cs; | |
44 | }; | |
45 | ||
46 | static DEFINE_SPINLOCK(sh_tmu_lock); | |
47 | ||
48 | #define TSTR -1 /* shared register */ | |
49 | #define TCOR 0 /* channel register */ | |
50 | #define TCNT 1 /* channel register */ | |
51 | #define TCR 2 /* channel register */ | |
52 | ||
53 | static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr) | |
54 | { | |
46a12f74 | 55 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
9570ef20 MD |
56 | void __iomem *base = p->mapbase; |
57 | unsigned long offs; | |
58 | ||
59 | if (reg_nr == TSTR) | |
60 | return ioread8(base - cfg->channel_offset); | |
61 | ||
62 | offs = reg_nr << 2; | |
63 | ||
64 | if (reg_nr == TCR) | |
65 | return ioread16(base + offs); | |
66 | else | |
67 | return ioread32(base + offs); | |
68 | } | |
69 | ||
70 | static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr, | |
71 | unsigned long value) | |
72 | { | |
46a12f74 | 73 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
9570ef20 MD |
74 | void __iomem *base = p->mapbase; |
75 | unsigned long offs; | |
76 | ||
77 | if (reg_nr == TSTR) { | |
78 | iowrite8(value, base - cfg->channel_offset); | |
79 | return; | |
80 | } | |
81 | ||
82 | offs = reg_nr << 2; | |
83 | ||
84 | if (reg_nr == TCR) | |
85 | iowrite16(value, base + offs); | |
86 | else | |
87 | iowrite32(value, base + offs); | |
88 | } | |
89 | ||
90 | static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start) | |
91 | { | |
46a12f74 | 92 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
9570ef20 MD |
93 | unsigned long flags, value; |
94 | ||
95 | /* start stop register shared by multiple timer channels */ | |
96 | spin_lock_irqsave(&sh_tmu_lock, flags); | |
97 | value = sh_tmu_read(p, TSTR); | |
98 | ||
99 | if (start) | |
100 | value |= 1 << cfg->timer_bit; | |
101 | else | |
102 | value &= ~(1 << cfg->timer_bit); | |
103 | ||
104 | sh_tmu_write(p, TSTR, value); | |
105 | spin_unlock_irqrestore(&sh_tmu_lock, flags); | |
106 | } | |
107 | ||
108 | static int sh_tmu_enable(struct sh_tmu_priv *p) | |
109 | { | |
46a12f74 | 110 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
9570ef20 MD |
111 | int ret; |
112 | ||
113 | /* enable clock */ | |
114 | ret = clk_enable(p->clk); | |
115 | if (ret) { | |
116 | pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk); | |
117 | return ret; | |
118 | } | |
119 | ||
120 | /* make sure channel is disabled */ | |
121 | sh_tmu_start_stop_ch(p, 0); | |
122 | ||
123 | /* maximum timeout */ | |
124 | sh_tmu_write(p, TCOR, 0xffffffff); | |
125 | sh_tmu_write(p, TCNT, 0xffffffff); | |
126 | ||
127 | /* configure channel to parent clock / 4, irq off */ | |
128 | p->rate = clk_get_rate(p->clk) / 4; | |
129 | sh_tmu_write(p, TCR, 0x0000); | |
130 | ||
131 | /* enable channel */ | |
132 | sh_tmu_start_stop_ch(p, 1); | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | static void sh_tmu_disable(struct sh_tmu_priv *p) | |
138 | { | |
139 | /* disable channel */ | |
140 | sh_tmu_start_stop_ch(p, 0); | |
141 | ||
be890a1a MD |
142 | /* disable interrupts in TMU block */ |
143 | sh_tmu_write(p, TCR, 0x0000); | |
144 | ||
9570ef20 MD |
145 | /* stop clock */ |
146 | clk_disable(p->clk); | |
147 | } | |
148 | ||
149 | static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta, | |
150 | int periodic) | |
151 | { | |
152 | /* stop timer */ | |
153 | sh_tmu_start_stop_ch(p, 0); | |
154 | ||
155 | /* acknowledge interrupt */ | |
156 | sh_tmu_read(p, TCR); | |
157 | ||
158 | /* enable interrupt */ | |
159 | sh_tmu_write(p, TCR, 0x0020); | |
160 | ||
161 | /* reload delta value in case of periodic timer */ | |
162 | if (periodic) | |
163 | sh_tmu_write(p, TCOR, delta); | |
164 | else | |
6f4b67b8 | 165 | sh_tmu_write(p, TCOR, 0xffffffff); |
9570ef20 MD |
166 | |
167 | sh_tmu_write(p, TCNT, delta); | |
168 | ||
169 | /* start timer */ | |
170 | sh_tmu_start_stop_ch(p, 1); | |
171 | } | |
172 | ||
173 | static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) | |
174 | { | |
175 | struct sh_tmu_priv *p = dev_id; | |
176 | ||
177 | /* disable or acknowledge interrupt */ | |
178 | if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) | |
179 | sh_tmu_write(p, TCR, 0x0000); | |
180 | else | |
181 | sh_tmu_write(p, TCR, 0x0020); | |
182 | ||
183 | /* notify clockevent layer */ | |
184 | p->ced.event_handler(&p->ced); | |
185 | return IRQ_HANDLED; | |
186 | } | |
187 | ||
188 | static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs) | |
189 | { | |
190 | return container_of(cs, struct sh_tmu_priv, cs); | |
191 | } | |
192 | ||
193 | static cycle_t sh_tmu_clocksource_read(struct clocksource *cs) | |
194 | { | |
195 | struct sh_tmu_priv *p = cs_to_sh_tmu(cs); | |
196 | ||
197 | return sh_tmu_read(p, TCNT) ^ 0xffffffff; | |
198 | } | |
199 | ||
200 | static int sh_tmu_clocksource_enable(struct clocksource *cs) | |
201 | { | |
202 | struct sh_tmu_priv *p = cs_to_sh_tmu(cs); | |
203 | int ret; | |
204 | ||
205 | ret = sh_tmu_enable(p); | |
206 | if (ret) | |
207 | return ret; | |
208 | ||
209 | /* TODO: calculate good shift from rate and counter bit width */ | |
210 | cs->shift = 10; | |
211 | cs->mult = clocksource_hz2mult(p->rate, cs->shift); | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static void sh_tmu_clocksource_disable(struct clocksource *cs) | |
216 | { | |
217 | sh_tmu_disable(cs_to_sh_tmu(cs)); | |
218 | } | |
219 | ||
220 | static int sh_tmu_register_clocksource(struct sh_tmu_priv *p, | |
221 | char *name, unsigned long rating) | |
222 | { | |
223 | struct clocksource *cs = &p->cs; | |
224 | ||
225 | cs->name = name; | |
226 | cs->rating = rating; | |
227 | cs->read = sh_tmu_clocksource_read; | |
228 | cs->enable = sh_tmu_clocksource_enable; | |
229 | cs->disable = sh_tmu_clocksource_disable; | |
230 | cs->mask = CLOCKSOURCE_MASK(32); | |
231 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
232 | pr_info("sh_tmu: %s used as clock source\n", cs->name); | |
233 | clocksource_register(cs); | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced) | |
238 | { | |
239 | return container_of(ced, struct sh_tmu_priv, ced); | |
240 | } | |
241 | ||
242 | static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic) | |
243 | { | |
244 | struct clock_event_device *ced = &p->ced; | |
245 | ||
246 | sh_tmu_enable(p); | |
247 | ||
248 | /* TODO: calculate good shift from rate and counter bit width */ | |
249 | ||
250 | ced->shift = 32; | |
251 | ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift); | |
252 | ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced); | |
253 | ced->min_delta_ns = 5000; | |
254 | ||
255 | if (periodic) { | |
256 | p->periodic = (p->rate + HZ/2) / HZ; | |
257 | sh_tmu_set_next(p, p->periodic, 1); | |
258 | } | |
259 | } | |
260 | ||
261 | static void sh_tmu_clock_event_mode(enum clock_event_mode mode, | |
262 | struct clock_event_device *ced) | |
263 | { | |
264 | struct sh_tmu_priv *p = ced_to_sh_tmu(ced); | |
265 | int disabled = 0; | |
266 | ||
267 | /* deal with old setting first */ | |
268 | switch (ced->mode) { | |
269 | case CLOCK_EVT_MODE_PERIODIC: | |
270 | case CLOCK_EVT_MODE_ONESHOT: | |
271 | sh_tmu_disable(p); | |
272 | disabled = 1; | |
273 | break; | |
274 | default: | |
275 | break; | |
276 | } | |
277 | ||
278 | switch (mode) { | |
279 | case CLOCK_EVT_MODE_PERIODIC: | |
280 | pr_info("sh_tmu: %s used for periodic clock events\n", | |
281 | ced->name); | |
282 | sh_tmu_clock_event_start(p, 1); | |
283 | break; | |
284 | case CLOCK_EVT_MODE_ONESHOT: | |
285 | pr_info("sh_tmu: %s used for oneshot clock events\n", | |
286 | ced->name); | |
287 | sh_tmu_clock_event_start(p, 0); | |
288 | break; | |
289 | case CLOCK_EVT_MODE_UNUSED: | |
290 | if (!disabled) | |
291 | sh_tmu_disable(p); | |
292 | break; | |
293 | case CLOCK_EVT_MODE_SHUTDOWN: | |
294 | default: | |
295 | break; | |
296 | } | |
297 | } | |
298 | ||
299 | static int sh_tmu_clock_event_next(unsigned long delta, | |
300 | struct clock_event_device *ced) | |
301 | { | |
302 | struct sh_tmu_priv *p = ced_to_sh_tmu(ced); | |
303 | ||
304 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
305 | ||
306 | /* program new delta value */ | |
307 | sh_tmu_set_next(p, delta, 0); | |
308 | return 0; | |
309 | } | |
310 | ||
311 | static void sh_tmu_register_clockevent(struct sh_tmu_priv *p, | |
312 | char *name, unsigned long rating) | |
313 | { | |
314 | struct clock_event_device *ced = &p->ced; | |
315 | int ret; | |
316 | ||
317 | memset(ced, 0, sizeof(*ced)); | |
318 | ||
319 | ced->name = name; | |
320 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
321 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
322 | ced->rating = rating; | |
323 | ced->cpumask = cpumask_of(0); | |
324 | ced->set_next_event = sh_tmu_clock_event_next; | |
325 | ced->set_mode = sh_tmu_clock_event_mode; | |
326 | ||
da64c2a8 PM |
327 | pr_info("sh_tmu: %s used for clock events\n", ced->name); |
328 | clockevents_register_device(ced); | |
329 | ||
9570ef20 MD |
330 | ret = setup_irq(p->irqaction.irq, &p->irqaction); |
331 | if (ret) { | |
332 | pr_err("sh_tmu: failed to request irq %d\n", | |
333 | p->irqaction.irq); | |
334 | return; | |
335 | } | |
9570ef20 MD |
336 | } |
337 | ||
338 | static int sh_tmu_register(struct sh_tmu_priv *p, char *name, | |
339 | unsigned long clockevent_rating, | |
340 | unsigned long clocksource_rating) | |
341 | { | |
342 | if (clockevent_rating) | |
343 | sh_tmu_register_clockevent(p, name, clockevent_rating); | |
344 | else if (clocksource_rating) | |
345 | sh_tmu_register_clocksource(p, name, clocksource_rating); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev) | |
351 | { | |
46a12f74 | 352 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
9570ef20 MD |
353 | struct resource *res; |
354 | int irq, ret; | |
355 | ret = -ENXIO; | |
356 | ||
357 | memset(p, 0, sizeof(*p)); | |
358 | p->pdev = pdev; | |
359 | ||
360 | if (!cfg) { | |
361 | dev_err(&p->pdev->dev, "missing platform data\n"); | |
362 | goto err0; | |
363 | } | |
364 | ||
365 | platform_set_drvdata(pdev, p); | |
366 | ||
367 | res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); | |
368 | if (!res) { | |
369 | dev_err(&p->pdev->dev, "failed to get I/O memory\n"); | |
370 | goto err0; | |
371 | } | |
372 | ||
373 | irq = platform_get_irq(p->pdev, 0); | |
374 | if (irq < 0) { | |
375 | dev_err(&p->pdev->dev, "failed to get irq\n"); | |
376 | goto err0; | |
377 | } | |
378 | ||
379 | /* map memory, let mapbase point to our channel */ | |
380 | p->mapbase = ioremap_nocache(res->start, resource_size(res)); | |
381 | if (p->mapbase == NULL) { | |
382 | pr_err("sh_tmu: failed to remap I/O memory\n"); | |
383 | goto err0; | |
384 | } | |
385 | ||
386 | /* setup data for setup_irq() (too early for request_irq()) */ | |
387 | p->irqaction.name = cfg->name; | |
388 | p->irqaction.handler = sh_tmu_interrupt; | |
389 | p->irqaction.dev_id = p; | |
390 | p->irqaction.irq = irq; | |
391 | p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL; | |
9570ef20 MD |
392 | |
393 | /* get hold of clock */ | |
394 | p->clk = clk_get(&p->pdev->dev, cfg->clk); | |
395 | if (IS_ERR(p->clk)) { | |
396 | pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg->clk); | |
397 | ret = PTR_ERR(p->clk); | |
398 | goto err1; | |
399 | } | |
400 | ||
401 | return sh_tmu_register(p, cfg->name, | |
402 | cfg->clockevent_rating, | |
403 | cfg->clocksource_rating); | |
404 | err1: | |
405 | iounmap(p->mapbase); | |
406 | err0: | |
407 | return ret; | |
408 | } | |
409 | ||
410 | static int __devinit sh_tmu_probe(struct platform_device *pdev) | |
411 | { | |
412 | struct sh_tmu_priv *p = platform_get_drvdata(pdev); | |
46a12f74 | 413 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
9570ef20 MD |
414 | int ret; |
415 | ||
416 | if (p) { | |
417 | pr_info("sh_tmu: %s kept as earlytimer\n", cfg->name); | |
418 | return 0; | |
419 | } | |
420 | ||
421 | p = kmalloc(sizeof(*p), GFP_KERNEL); | |
422 | if (p == NULL) { | |
423 | dev_err(&pdev->dev, "failed to allocate driver data\n"); | |
424 | return -ENOMEM; | |
425 | } | |
426 | ||
427 | ret = sh_tmu_setup(p, pdev); | |
428 | if (ret) { | |
429 | kfree(p); | |
430 | platform_set_drvdata(pdev, NULL); | |
431 | } | |
432 | return ret; | |
433 | } | |
434 | ||
435 | static int __devexit sh_tmu_remove(struct platform_device *pdev) | |
436 | { | |
437 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
438 | } | |
439 | ||
440 | static struct platform_driver sh_tmu_device_driver = { | |
441 | .probe = sh_tmu_probe, | |
442 | .remove = __devexit_p(sh_tmu_remove), | |
443 | .driver = { | |
444 | .name = "sh_tmu", | |
445 | } | |
446 | }; | |
447 | ||
448 | static int __init sh_tmu_init(void) | |
449 | { | |
450 | return platform_driver_register(&sh_tmu_device_driver); | |
451 | } | |
452 | ||
453 | static void __exit sh_tmu_exit(void) | |
454 | { | |
455 | platform_driver_unregister(&sh_tmu_device_driver); | |
456 | } | |
457 | ||
458 | early_platform_init("earlytimer", &sh_tmu_device_driver); | |
459 | module_init(sh_tmu_init); | |
460 | module_exit(sh_tmu_exit); | |
461 | ||
462 | MODULE_AUTHOR("Magnus Damm"); | |
463 | MODULE_DESCRIPTION("SuperH TMU Timer Driver"); | |
464 | MODULE_LICENSE("GPL v2"); |