x86/mpx: Trace entry to bounds exception paths
[linux-2.6-block.git] / drivers / clocksource / sh_tmu.c
CommitLineData
9570ef20
MD
1/*
2 * SuperH Timer Support - TMU
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
9570ef20
MD
14 */
15
13931f80
LP
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/delay.h>
20#include <linux/err.h>
9570ef20 21#include <linux/init.h>
9570ef20 22#include <linux/interrupt.h>
9570ef20 23#include <linux/io.h>
13931f80 24#include <linux/ioport.h>
9570ef20 25#include <linux/irq.h>
7deeab5d 26#include <linux/module.h>
3e29b554 27#include <linux/of.h>
13931f80 28#include <linux/platform_device.h>
2ee619f9 29#include <linux/pm_domain.h>
eaa49a8c 30#include <linux/pm_runtime.h>
13931f80
LP
31#include <linux/sh_timer.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
9570ef20 34
8c7f21e6 35enum sh_tmu_model {
8c7f21e6
LP
36 SH_TMU,
37 SH_TMU_SH3,
38};
39
0a72aa39 40struct sh_tmu_device;
de2d12c7
LP
41
42struct sh_tmu_channel {
0a72aa39 43 struct sh_tmu_device *tmu;
fe68eb80 44 unsigned int index;
de2d12c7 45
de693461 46 void __iomem *base;
1c56cf6b 47 int irq;
de2d12c7 48
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MD
49 unsigned long rate;
50 unsigned long periodic;
51 struct clock_event_device ced;
52 struct clocksource cs;
eaa49a8c 53 bool cs_enabled;
61a53bfa 54 unsigned int enable_count;
9570ef20
MD
55};
56
0a72aa39 57struct sh_tmu_device {
de2d12c7
LP
58 struct platform_device *pdev;
59
60 void __iomem *mapbase;
61 struct clk *clk;
62
8c7f21e6
LP
63 enum sh_tmu_model model;
64
2b027f1f
LP
65 raw_spinlock_t lock; /* Protect the shared start/stop register */
66
a5de49f4
LP
67 struct sh_tmu_channel *channels;
68 unsigned int num_channels;
8c7f21e6
LP
69
70 bool has_clockevent;
71 bool has_clocksource;
de2d12c7
LP
72};
73
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MD
74#define TSTR -1 /* shared register */
75#define TCOR 0 /* channel register */
76#define TCNT 1 /* channel register */
77#define TCR 2 /* channel register */
78
5cfe2d15
LP
79#define TCR_UNF (1 << 8)
80#define TCR_UNIE (1 << 5)
81#define TCR_TPSC_CLK4 (0 << 0)
82#define TCR_TPSC_CLK16 (1 << 0)
83#define TCR_TPSC_CLK64 (2 << 0)
84#define TCR_TPSC_CLK256 (3 << 0)
85#define TCR_TPSC_CLK1024 (4 << 0)
86#define TCR_TPSC_MASK (7 << 0)
87
de2d12c7 88static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
9570ef20 89{
9570ef20
MD
90 unsigned long offs;
91
8c7f21e6
LP
92 if (reg_nr == TSTR) {
93 switch (ch->tmu->model) {
8c7f21e6
LP
94 case SH_TMU_SH3:
95 return ioread8(ch->tmu->mapbase + 2);
96 case SH_TMU:
97 return ioread8(ch->tmu->mapbase + 4);
98 }
99 }
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MD
100
101 offs = reg_nr << 2;
102
103 if (reg_nr == TCR)
de693461 104 return ioread16(ch->base + offs);
9570ef20 105 else
de693461 106 return ioread32(ch->base + offs);
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MD
107}
108
de2d12c7 109static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
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MD
110 unsigned long value)
111{
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MD
112 unsigned long offs;
113
114 if (reg_nr == TSTR) {
8c7f21e6 115 switch (ch->tmu->model) {
8c7f21e6
LP
116 case SH_TMU_SH3:
117 return iowrite8(value, ch->tmu->mapbase + 2);
118 case SH_TMU:
119 return iowrite8(value, ch->tmu->mapbase + 4);
120 }
9570ef20
MD
121 }
122
123 offs = reg_nr << 2;
124
125 if (reg_nr == TCR)
de693461 126 iowrite16(value, ch->base + offs);
9570ef20 127 else
de693461 128 iowrite32(value, ch->base + offs);
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MD
129}
130
de2d12c7 131static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
9570ef20 132{
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MD
133 unsigned long flags, value;
134
135 /* start stop register shared by multiple timer channels */
2b027f1f 136 raw_spin_lock_irqsave(&ch->tmu->lock, flags);
de2d12c7 137 value = sh_tmu_read(ch, TSTR);
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MD
138
139 if (start)
fe68eb80 140 value |= 1 << ch->index;
9570ef20 141 else
fe68eb80 142 value &= ~(1 << ch->index);
9570ef20 143
de2d12c7 144 sh_tmu_write(ch, TSTR, value);
2b027f1f 145 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
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MD
146}
147
de2d12c7 148static int __sh_tmu_enable(struct sh_tmu_channel *ch)
9570ef20 149{
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MD
150 int ret;
151
d4905ce3 152 /* enable clock */
de2d12c7 153 ret = clk_enable(ch->tmu->clk);
9570ef20 154 if (ret) {
fe68eb80
LP
155 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
156 ch->index);
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MD
157 return ret;
158 }
159
160 /* make sure channel is disabled */
de2d12c7 161 sh_tmu_start_stop_ch(ch, 0);
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MD
162
163 /* maximum timeout */
de2d12c7
LP
164 sh_tmu_write(ch, TCOR, 0xffffffff);
165 sh_tmu_write(ch, TCNT, 0xffffffff);
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MD
166
167 /* configure channel to parent clock / 4, irq off */
de2d12c7 168 ch->rate = clk_get_rate(ch->tmu->clk) / 4;
5cfe2d15 169 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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MD
170
171 /* enable channel */
de2d12c7 172 sh_tmu_start_stop_ch(ch, 1);
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MD
173
174 return 0;
175}
176
de2d12c7 177static int sh_tmu_enable(struct sh_tmu_channel *ch)
61a53bfa 178{
de2d12c7 179 if (ch->enable_count++ > 0)
61a53bfa
RW
180 return 0;
181
de2d12c7
LP
182 pm_runtime_get_sync(&ch->tmu->pdev->dev);
183 dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
61a53bfa 184
de2d12c7 185 return __sh_tmu_enable(ch);
61a53bfa
RW
186}
187
de2d12c7 188static void __sh_tmu_disable(struct sh_tmu_channel *ch)
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MD
189{
190 /* disable channel */
de2d12c7 191 sh_tmu_start_stop_ch(ch, 0);
9570ef20 192
be890a1a 193 /* disable interrupts in TMU block */
5cfe2d15 194 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
be890a1a 195
d4905ce3 196 /* stop clock */
de2d12c7 197 clk_disable(ch->tmu->clk);
9570ef20
MD
198}
199
de2d12c7 200static void sh_tmu_disable(struct sh_tmu_channel *ch)
61a53bfa 201{
de2d12c7 202 if (WARN_ON(ch->enable_count == 0))
61a53bfa
RW
203 return;
204
de2d12c7 205 if (--ch->enable_count > 0)
61a53bfa
RW
206 return;
207
de2d12c7 208 __sh_tmu_disable(ch);
61a53bfa 209
de2d12c7
LP
210 dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
211 pm_runtime_put(&ch->tmu->pdev->dev);
61a53bfa
RW
212}
213
de2d12c7 214static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
9570ef20
MD
215 int periodic)
216{
217 /* stop timer */
de2d12c7 218 sh_tmu_start_stop_ch(ch, 0);
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MD
219
220 /* acknowledge interrupt */
de2d12c7 221 sh_tmu_read(ch, TCR);
9570ef20
MD
222
223 /* enable interrupt */
5cfe2d15 224 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
9570ef20
MD
225
226 /* reload delta value in case of periodic timer */
227 if (periodic)
de2d12c7 228 sh_tmu_write(ch, TCOR, delta);
9570ef20 229 else
de2d12c7 230 sh_tmu_write(ch, TCOR, 0xffffffff);
9570ef20 231
de2d12c7 232 sh_tmu_write(ch, TCNT, delta);
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MD
233
234 /* start timer */
de2d12c7 235 sh_tmu_start_stop_ch(ch, 1);
9570ef20
MD
236}
237
238static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
239{
de2d12c7 240 struct sh_tmu_channel *ch = dev_id;
9570ef20
MD
241
242 /* disable or acknowledge interrupt */
de2d12c7 243 if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
5cfe2d15 244 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
9570ef20 245 else
5cfe2d15 246 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
9570ef20
MD
247
248 /* notify clockevent layer */
de2d12c7 249 ch->ced.event_handler(&ch->ced);
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MD
250 return IRQ_HANDLED;
251}
252
de2d12c7 253static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
9570ef20 254{
de2d12c7 255 return container_of(cs, struct sh_tmu_channel, cs);
9570ef20
MD
256}
257
258static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
259{
de2d12c7 260 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
9570ef20 261
de2d12c7 262 return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
9570ef20
MD
263}
264
265static int sh_tmu_clocksource_enable(struct clocksource *cs)
266{
de2d12c7 267 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
0aeac458 268 int ret;
9570ef20 269
de2d12c7 270 if (WARN_ON(ch->cs_enabled))
61a53bfa
RW
271 return 0;
272
de2d12c7 273 ret = sh_tmu_enable(ch);
eaa49a8c 274 if (!ret) {
fba9e072 275 __clocksource_update_freq_hz(cs, ch->rate);
de2d12c7 276 ch->cs_enabled = true;
eaa49a8c 277 }
61a53bfa 278
0aeac458 279 return ret;
9570ef20
MD
280}
281
282static void sh_tmu_clocksource_disable(struct clocksource *cs)
283{
de2d12c7 284 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
eaa49a8c 285
de2d12c7 286 if (WARN_ON(!ch->cs_enabled))
61a53bfa 287 return;
eaa49a8c 288
de2d12c7
LP
289 sh_tmu_disable(ch);
290 ch->cs_enabled = false;
eaa49a8c
RW
291}
292
293static void sh_tmu_clocksource_suspend(struct clocksource *cs)
294{
de2d12c7 295 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
eaa49a8c 296
de2d12c7 297 if (!ch->cs_enabled)
61a53bfa 298 return;
eaa49a8c 299
de2d12c7
LP
300 if (--ch->enable_count == 0) {
301 __sh_tmu_disable(ch);
302 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
61a53bfa 303 }
eaa49a8c
RW
304}
305
306static void sh_tmu_clocksource_resume(struct clocksource *cs)
307{
de2d12c7 308 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
eaa49a8c 309
de2d12c7 310 if (!ch->cs_enabled)
61a53bfa
RW
311 return;
312
de2d12c7
LP
313 if (ch->enable_count++ == 0) {
314 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
315 __sh_tmu_enable(ch);
61a53bfa 316 }
9570ef20
MD
317}
318
de2d12c7 319static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
f1010ed1 320 const char *name)
9570ef20 321{
de2d12c7 322 struct clocksource *cs = &ch->cs;
9570ef20
MD
323
324 cs->name = name;
f1010ed1 325 cs->rating = 200;
9570ef20
MD
326 cs->read = sh_tmu_clocksource_read;
327 cs->enable = sh_tmu_clocksource_enable;
328 cs->disable = sh_tmu_clocksource_disable;
eaa49a8c
RW
329 cs->suspend = sh_tmu_clocksource_suspend;
330 cs->resume = sh_tmu_clocksource_resume;
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MD
331 cs->mask = CLOCKSOURCE_MASK(32);
332 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
66f49121 333
fe68eb80
LP
334 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
335 ch->index);
0aeac458
MD
336
337 /* Register with dummy 1 Hz value, gets updated in ->enable() */
338 clocksource_register_hz(cs, 1);
9570ef20
MD
339 return 0;
340}
341
de2d12c7 342static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
9570ef20 343{
de2d12c7 344 return container_of(ced, struct sh_tmu_channel, ced);
9570ef20
MD
345}
346
de2d12c7 347static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
9570ef20 348{
de2d12c7 349 struct clock_event_device *ced = &ch->ced;
9570ef20 350
de2d12c7 351 sh_tmu_enable(ch);
9570ef20 352
de2d12c7 353 clockevents_config(ced, ch->rate);
9570ef20
MD
354
355 if (periodic) {
de2d12c7
LP
356 ch->periodic = (ch->rate + HZ/2) / HZ;
357 sh_tmu_set_next(ch, ch->periodic, 1);
9570ef20
MD
358 }
359}
360
361static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
362 struct clock_event_device *ced)
363{
de2d12c7 364 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
9570ef20
MD
365 int disabled = 0;
366
367 /* deal with old setting first */
368 switch (ced->mode) {
369 case CLOCK_EVT_MODE_PERIODIC:
370 case CLOCK_EVT_MODE_ONESHOT:
de2d12c7 371 sh_tmu_disable(ch);
9570ef20
MD
372 disabled = 1;
373 break;
374 default:
375 break;
376 }
377
378 switch (mode) {
379 case CLOCK_EVT_MODE_PERIODIC:
de2d12c7 380 dev_info(&ch->tmu->pdev->dev,
fe68eb80 381 "ch%u: used for periodic clock events\n", ch->index);
de2d12c7 382 sh_tmu_clock_event_start(ch, 1);
9570ef20
MD
383 break;
384 case CLOCK_EVT_MODE_ONESHOT:
de2d12c7 385 dev_info(&ch->tmu->pdev->dev,
fe68eb80 386 "ch%u: used for oneshot clock events\n", ch->index);
de2d12c7 387 sh_tmu_clock_event_start(ch, 0);
9570ef20
MD
388 break;
389 case CLOCK_EVT_MODE_UNUSED:
390 if (!disabled)
de2d12c7 391 sh_tmu_disable(ch);
9570ef20
MD
392 break;
393 case CLOCK_EVT_MODE_SHUTDOWN:
394 default:
395 break;
396 }
397}
398
399static int sh_tmu_clock_event_next(unsigned long delta,
400 struct clock_event_device *ced)
401{
de2d12c7 402 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
9570ef20
MD
403
404 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
405
406 /* program new delta value */
de2d12c7 407 sh_tmu_set_next(ch, delta, 0);
9570ef20
MD
408 return 0;
409}
410
eaa49a8c
RW
411static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
412{
de2d12c7 413 pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
eaa49a8c
RW
414}
415
416static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
417{
de2d12c7 418 pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
eaa49a8c
RW
419}
420
de2d12c7 421static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
f1010ed1 422 const char *name)
9570ef20 423{
de2d12c7 424 struct clock_event_device *ced = &ch->ced;
9570ef20
MD
425 int ret;
426
9570ef20
MD
427 ced->name = name;
428 ced->features = CLOCK_EVT_FEAT_PERIODIC;
429 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
f1010ed1 430 ced->rating = 200;
f2a54738 431 ced->cpumask = cpu_possible_mask;
9570ef20
MD
432 ced->set_next_event = sh_tmu_clock_event_next;
433 ced->set_mode = sh_tmu_clock_event_mode;
eaa49a8c
RW
434 ced->suspend = sh_tmu_clock_event_suspend;
435 ced->resume = sh_tmu_clock_event_resume;
9570ef20 436
fe68eb80
LP
437 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
438 ch->index);
3977407e
PM
439
440 clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
da64c2a8 441
de2d12c7 442 ret = request_irq(ch->irq, sh_tmu_interrupt,
1c56cf6b 443 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
de2d12c7 444 dev_name(&ch->tmu->pdev->dev), ch);
9570ef20 445 if (ret) {
fe68eb80
LP
446 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
447 ch->index, ch->irq);
9570ef20
MD
448 return;
449 }
9570ef20
MD
450}
451
84876d05 452static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
f1010ed1 453 bool clockevent, bool clocksource)
9570ef20 454{
8c7f21e6
LP
455 if (clockevent) {
456 ch->tmu->has_clockevent = true;
f1010ed1 457 sh_tmu_register_clockevent(ch, name);
8c7f21e6
LP
458 } else if (clocksource) {
459 ch->tmu->has_clocksource = true;
f1010ed1 460 sh_tmu_register_clocksource(ch, name);
8c7f21e6 461 }
9570ef20
MD
462
463 return 0;
464}
465
8c7f21e6
LP
466static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
467 bool clockevent, bool clocksource,
a94ddaa6
LP
468 struct sh_tmu_device *tmu)
469{
8c7f21e6
LP
470 /* Skip unused channels. */
471 if (!clockevent && !clocksource)
472 return 0;
a94ddaa6 473
a94ddaa6 474 ch->tmu = tmu;
681b9e85 475 ch->index = index;
a94ddaa6 476
681b9e85
LP
477 if (tmu->model == SH_TMU_SH3)
478 ch->base = tmu->mapbase + 4 + ch->index * 12;
479 else
480 ch->base = tmu->mapbase + 8 + ch->index * 12;
fe68eb80 481
c54697ae 482 ch->irq = platform_get_irq(tmu->pdev, index);
a94ddaa6 483 if (ch->irq < 0) {
fe68eb80
LP
484 dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
485 ch->index);
a94ddaa6
LP
486 return ch->irq;
487 }
488
489 ch->cs_enabled = false;
490 ch->enable_count = 0;
491
84876d05 492 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
8c7f21e6 493 clockevent, clocksource);
a94ddaa6
LP
494}
495
8c7f21e6 496static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
9570ef20 497{
9570ef20 498 struct resource *res;
9570ef20 499
0a72aa39 500 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
9570ef20 501 if (!res) {
0a72aa39 502 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
8c7f21e6 503 return -ENXIO;
9570ef20
MD
504 }
505
8c7f21e6
LP
506 tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
507 if (tmu->mapbase == NULL)
508 return -ENXIO;
509
8c7f21e6
LP
510 return 0;
511}
de693461 512
3e29b554
LP
513static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
514{
515 struct device_node *np = tmu->pdev->dev.of_node;
516
517 tmu->model = SH_TMU;
518 tmu->num_channels = 3;
519
520 of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
521
522 if (tmu->num_channels != 2 && tmu->num_channels != 3) {
523 dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
524 tmu->num_channels);
525 return -EINVAL;
526 }
527
528 return 0;
529}
530
8c7f21e6
LP
531static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
532{
8c7f21e6
LP
533 unsigned int i;
534 int ret;
535
8c7f21e6 536 tmu->pdev = pdev;
8c7f21e6 537
2b027f1f
LP
538 raw_spin_lock_init(&tmu->lock);
539
3e29b554
LP
540 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
541 ret = sh_tmu_parse_dt(tmu);
542 if (ret < 0)
543 return ret;
544 } else if (pdev->dev.platform_data) {
545 const struct platform_device_id *id = pdev->id_entry;
546 struct sh_timer_config *cfg = pdev->dev.platform_data;
547
548 tmu->model = id->driver_data;
549 tmu->num_channels = hweight8(cfg->channels_mask);
550 } else {
551 dev_err(&tmu->pdev->dev, "missing platform data\n");
552 return -ENXIO;
553 }
554
8c7f21e6 555 /* Get hold of clock. */
681b9e85 556 tmu->clk = clk_get(&tmu->pdev->dev, "fck");
0a72aa39
LP
557 if (IS_ERR(tmu->clk)) {
558 dev_err(&tmu->pdev->dev, "cannot get clock\n");
8c7f21e6 559 return PTR_ERR(tmu->clk);
9570ef20 560 }
1c09eb3e 561
0a72aa39 562 ret = clk_prepare(tmu->clk);
1c09eb3e 563 if (ret < 0)
8c7f21e6
LP
564 goto err_clk_put;
565
566 /* Map the memory resource. */
567 ret = sh_tmu_map_memory(tmu);
568 if (ret < 0) {
569 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
570 goto err_clk_unprepare;
571 }
1c09eb3e 572
8c7f21e6 573 /* Allocate and setup the channels. */
8c7f21e6
LP
574 tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
575 GFP_KERNEL);
a5de49f4
LP
576 if (tmu->channels == NULL) {
577 ret = -ENOMEM;
8c7f21e6 578 goto err_unmap;
a5de49f4
LP
579 }
580
681b9e85
LP
581 /*
582 * Use the first channel as a clock event device and the second channel
583 * as a clock source.
584 */
585 for (i = 0; i < tmu->num_channels; ++i) {
586 ret = sh_tmu_channel_setup(&tmu->channels[i], i,
587 i == 0, i == 1, tmu);
8c7f21e6
LP
588 if (ret < 0)
589 goto err_unmap;
8c7f21e6 590 }
a5de49f4 591
8c7f21e6 592 platform_set_drvdata(pdev, tmu);
394a4486
LP
593
594 return 0;
595
8c7f21e6 596err_unmap:
a5de49f4 597 kfree(tmu->channels);
681b9e85 598 iounmap(tmu->mapbase);
8c7f21e6 599err_clk_unprepare:
0a72aa39 600 clk_unprepare(tmu->clk);
8c7f21e6 601err_clk_put:
0a72aa39 602 clk_put(tmu->clk);
9570ef20
MD
603 return ret;
604}
605
1850514b 606static int sh_tmu_probe(struct platform_device *pdev)
9570ef20 607{
0a72aa39 608 struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
9570ef20
MD
609 int ret;
610
eaa49a8c 611 if (!is_early_platform_device(pdev)) {
61a53bfa
RW
612 pm_runtime_set_active(&pdev->dev);
613 pm_runtime_enable(&pdev->dev);
eaa49a8c 614 }
2ee619f9 615
0a72aa39 616 if (tmu) {
214a607a 617 dev_info(&pdev->dev, "kept as earlytimer\n");
61a53bfa 618 goto out;
9570ef20
MD
619 }
620
3b77a83e 621 tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
814876b0 622 if (tmu == NULL)
9570ef20 623 return -ENOMEM;
9570ef20 624
0a72aa39 625 ret = sh_tmu_setup(tmu, pdev);
9570ef20 626 if (ret) {
0a72aa39 627 kfree(tmu);
61a53bfa
RW
628 pm_runtime_idle(&pdev->dev);
629 return ret;
9570ef20 630 }
61a53bfa
RW
631 if (is_early_platform_device(pdev))
632 return 0;
633
634 out:
8c7f21e6 635 if (tmu->has_clockevent || tmu->has_clocksource)
61a53bfa
RW
636 pm_runtime_irq_safe(&pdev->dev);
637 else
638 pm_runtime_idle(&pdev->dev);
639
640 return 0;
9570ef20
MD
641}
642
1850514b 643static int sh_tmu_remove(struct platform_device *pdev)
9570ef20
MD
644{
645 return -EBUSY; /* cannot unregister clockevent and clocksource */
646}
647
8c7f21e6 648static const struct platform_device_id sh_tmu_id_table[] = {
8c7f21e6
LP
649 { "sh-tmu", SH_TMU },
650 { "sh-tmu-sh3", SH_TMU_SH3 },
651 { }
652};
653MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
654
3e29b554
LP
655static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
656 { .compatible = "renesas,tmu" },
657 { }
658};
659MODULE_DEVICE_TABLE(of, sh_tmu_of_table);
660
9570ef20
MD
661static struct platform_driver sh_tmu_device_driver = {
662 .probe = sh_tmu_probe,
1850514b 663 .remove = sh_tmu_remove,
9570ef20
MD
664 .driver = {
665 .name = "sh_tmu",
3e29b554 666 .of_match_table = of_match_ptr(sh_tmu_of_table),
8c7f21e6
LP
667 },
668 .id_table = sh_tmu_id_table,
9570ef20
MD
669};
670
671static int __init sh_tmu_init(void)
672{
673 return platform_driver_register(&sh_tmu_device_driver);
674}
675
676static void __exit sh_tmu_exit(void)
677{
678 platform_driver_unregister(&sh_tmu_device_driver);
679}
680
681early_platform_init("earlytimer", &sh_tmu_device_driver);
b9773c3f 682subsys_initcall(sh_tmu_init);
9570ef20
MD
683module_exit(sh_tmu_exit);
684
685MODULE_AUTHOR("Magnus Damm");
686MODULE_DESCRIPTION("SuperH TMU Timer Driver");
687MODULE_LICENSE("GPL v2");