Commit | Line | Data |
---|---|---|
0b9294fe | 1 | // SPDX-License-Identifier: GPL-2.0 |
9570ef20 MD |
2 | /* |
3 | * SuperH Timer Support - TMU | |
4 | * | |
5 | * Copyright (C) 2009 Magnus Damm | |
9570ef20 MD |
6 | */ |
7 | ||
13931f80 LP |
8 | #include <linux/clk.h> |
9 | #include <linux/clockchips.h> | |
10 | #include <linux/clocksource.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/err.h> | |
9570ef20 | 13 | #include <linux/init.h> |
9570ef20 | 14 | #include <linux/interrupt.h> |
9570ef20 | 15 | #include <linux/io.h> |
13931f80 | 16 | #include <linux/ioport.h> |
9570ef20 | 17 | #include <linux/irq.h> |
7deeab5d | 18 | #include <linux/module.h> |
3e29b554 | 19 | #include <linux/of.h> |
13931f80 | 20 | #include <linux/platform_device.h> |
2ee619f9 | 21 | #include <linux/pm_domain.h> |
eaa49a8c | 22 | #include <linux/pm_runtime.h> |
13931f80 LP |
23 | #include <linux/sh_timer.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
9570ef20 | 26 | |
8c7f21e6 | 27 | enum sh_tmu_model { |
8c7f21e6 LP |
28 | SH_TMU, |
29 | SH_TMU_SH3, | |
30 | }; | |
31 | ||
0a72aa39 | 32 | struct sh_tmu_device; |
de2d12c7 LP |
33 | |
34 | struct sh_tmu_channel { | |
0a72aa39 | 35 | struct sh_tmu_device *tmu; |
fe68eb80 | 36 | unsigned int index; |
de2d12c7 | 37 | |
de693461 | 38 | void __iomem *base; |
1c56cf6b | 39 | int irq; |
de2d12c7 | 40 | |
9570ef20 MD |
41 | unsigned long periodic; |
42 | struct clock_event_device ced; | |
43 | struct clocksource cs; | |
eaa49a8c | 44 | bool cs_enabled; |
61a53bfa | 45 | unsigned int enable_count; |
9570ef20 MD |
46 | }; |
47 | ||
0a72aa39 | 48 | struct sh_tmu_device { |
de2d12c7 LP |
49 | struct platform_device *pdev; |
50 | ||
51 | void __iomem *mapbase; | |
52 | struct clk *clk; | |
c3c0a20d | 53 | unsigned long rate; |
de2d12c7 | 54 | |
8c7f21e6 LP |
55 | enum sh_tmu_model model; |
56 | ||
2b027f1f LP |
57 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
58 | ||
a5de49f4 LP |
59 | struct sh_tmu_channel *channels; |
60 | unsigned int num_channels; | |
8c7f21e6 LP |
61 | |
62 | bool has_clockevent; | |
63 | bool has_clocksource; | |
de2d12c7 LP |
64 | }; |
65 | ||
9570ef20 MD |
66 | #define TSTR -1 /* shared register */ |
67 | #define TCOR 0 /* channel register */ | |
68 | #define TCNT 1 /* channel register */ | |
69 | #define TCR 2 /* channel register */ | |
70 | ||
5cfe2d15 LP |
71 | #define TCR_UNF (1 << 8) |
72 | #define TCR_UNIE (1 << 5) | |
73 | #define TCR_TPSC_CLK4 (0 << 0) | |
74 | #define TCR_TPSC_CLK16 (1 << 0) | |
75 | #define TCR_TPSC_CLK64 (2 << 0) | |
76 | #define TCR_TPSC_CLK256 (3 << 0) | |
77 | #define TCR_TPSC_CLK1024 (4 << 0) | |
78 | #define TCR_TPSC_MASK (7 << 0) | |
79 | ||
de2d12c7 | 80 | static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) |
9570ef20 | 81 | { |
9570ef20 MD |
82 | unsigned long offs; |
83 | ||
8c7f21e6 LP |
84 | if (reg_nr == TSTR) { |
85 | switch (ch->tmu->model) { | |
8c7f21e6 LP |
86 | case SH_TMU_SH3: |
87 | return ioread8(ch->tmu->mapbase + 2); | |
88 | case SH_TMU: | |
89 | return ioread8(ch->tmu->mapbase + 4); | |
90 | } | |
91 | } | |
9570ef20 MD |
92 | |
93 | offs = reg_nr << 2; | |
94 | ||
95 | if (reg_nr == TCR) | |
de693461 | 96 | return ioread16(ch->base + offs); |
9570ef20 | 97 | else |
de693461 | 98 | return ioread32(ch->base + offs); |
9570ef20 MD |
99 | } |
100 | ||
de2d12c7 | 101 | static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, |
9570ef20 MD |
102 | unsigned long value) |
103 | { | |
9570ef20 MD |
104 | unsigned long offs; |
105 | ||
106 | if (reg_nr == TSTR) { | |
8c7f21e6 | 107 | switch (ch->tmu->model) { |
8c7f21e6 LP |
108 | case SH_TMU_SH3: |
109 | return iowrite8(value, ch->tmu->mapbase + 2); | |
110 | case SH_TMU: | |
111 | return iowrite8(value, ch->tmu->mapbase + 4); | |
112 | } | |
9570ef20 MD |
113 | } |
114 | ||
115 | offs = reg_nr << 2; | |
116 | ||
117 | if (reg_nr == TCR) | |
de693461 | 118 | iowrite16(value, ch->base + offs); |
9570ef20 | 119 | else |
de693461 | 120 | iowrite32(value, ch->base + offs); |
9570ef20 MD |
121 | } |
122 | ||
de2d12c7 | 123 | static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) |
9570ef20 | 124 | { |
9570ef20 MD |
125 | unsigned long flags, value; |
126 | ||
127 | /* start stop register shared by multiple timer channels */ | |
2b027f1f | 128 | raw_spin_lock_irqsave(&ch->tmu->lock, flags); |
de2d12c7 | 129 | value = sh_tmu_read(ch, TSTR); |
9570ef20 MD |
130 | |
131 | if (start) | |
fe68eb80 | 132 | value |= 1 << ch->index; |
9570ef20 | 133 | else |
fe68eb80 | 134 | value &= ~(1 << ch->index); |
9570ef20 | 135 | |
de2d12c7 | 136 | sh_tmu_write(ch, TSTR, value); |
2b027f1f | 137 | raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); |
9570ef20 MD |
138 | } |
139 | ||
de2d12c7 | 140 | static int __sh_tmu_enable(struct sh_tmu_channel *ch) |
9570ef20 | 141 | { |
9570ef20 MD |
142 | int ret; |
143 | ||
d4905ce3 | 144 | /* enable clock */ |
de2d12c7 | 145 | ret = clk_enable(ch->tmu->clk); |
9570ef20 | 146 | if (ret) { |
fe68eb80 LP |
147 | dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", |
148 | ch->index); | |
9570ef20 MD |
149 | return ret; |
150 | } | |
151 | ||
152 | /* make sure channel is disabled */ | |
de2d12c7 | 153 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 MD |
154 | |
155 | /* maximum timeout */ | |
de2d12c7 LP |
156 | sh_tmu_write(ch, TCOR, 0xffffffff); |
157 | sh_tmu_write(ch, TCNT, 0xffffffff); | |
9570ef20 MD |
158 | |
159 | /* configure channel to parent clock / 4, irq off */ | |
5cfe2d15 | 160 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
9570ef20 MD |
161 | |
162 | /* enable channel */ | |
de2d12c7 | 163 | sh_tmu_start_stop_ch(ch, 1); |
9570ef20 MD |
164 | |
165 | return 0; | |
166 | } | |
167 | ||
de2d12c7 | 168 | static int sh_tmu_enable(struct sh_tmu_channel *ch) |
61a53bfa | 169 | { |
de2d12c7 | 170 | if (ch->enable_count++ > 0) |
61a53bfa RW |
171 | return 0; |
172 | ||
de2d12c7 LP |
173 | pm_runtime_get_sync(&ch->tmu->pdev->dev); |
174 | dev_pm_syscore_device(&ch->tmu->pdev->dev, true); | |
61a53bfa | 175 | |
de2d12c7 | 176 | return __sh_tmu_enable(ch); |
61a53bfa RW |
177 | } |
178 | ||
de2d12c7 | 179 | static void __sh_tmu_disable(struct sh_tmu_channel *ch) |
9570ef20 MD |
180 | { |
181 | /* disable channel */ | |
de2d12c7 | 182 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 | 183 | |
be890a1a | 184 | /* disable interrupts in TMU block */ |
5cfe2d15 | 185 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
be890a1a | 186 | |
d4905ce3 | 187 | /* stop clock */ |
de2d12c7 | 188 | clk_disable(ch->tmu->clk); |
9570ef20 MD |
189 | } |
190 | ||
de2d12c7 | 191 | static void sh_tmu_disable(struct sh_tmu_channel *ch) |
61a53bfa | 192 | { |
de2d12c7 | 193 | if (WARN_ON(ch->enable_count == 0)) |
61a53bfa RW |
194 | return; |
195 | ||
de2d12c7 | 196 | if (--ch->enable_count > 0) |
61a53bfa RW |
197 | return; |
198 | ||
de2d12c7 | 199 | __sh_tmu_disable(ch); |
61a53bfa | 200 | |
de2d12c7 LP |
201 | dev_pm_syscore_device(&ch->tmu->pdev->dev, false); |
202 | pm_runtime_put(&ch->tmu->pdev->dev); | |
61a53bfa RW |
203 | } |
204 | ||
de2d12c7 | 205 | static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, |
9570ef20 MD |
206 | int periodic) |
207 | { | |
208 | /* stop timer */ | |
de2d12c7 | 209 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 MD |
210 | |
211 | /* acknowledge interrupt */ | |
de2d12c7 | 212 | sh_tmu_read(ch, TCR); |
9570ef20 MD |
213 | |
214 | /* enable interrupt */ | |
5cfe2d15 | 215 | sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
9570ef20 MD |
216 | |
217 | /* reload delta value in case of periodic timer */ | |
218 | if (periodic) | |
de2d12c7 | 219 | sh_tmu_write(ch, TCOR, delta); |
9570ef20 | 220 | else |
de2d12c7 | 221 | sh_tmu_write(ch, TCOR, 0xffffffff); |
9570ef20 | 222 | |
de2d12c7 | 223 | sh_tmu_write(ch, TCNT, delta); |
9570ef20 MD |
224 | |
225 | /* start timer */ | |
de2d12c7 | 226 | sh_tmu_start_stop_ch(ch, 1); |
9570ef20 MD |
227 | } |
228 | ||
229 | static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) | |
230 | { | |
de2d12c7 | 231 | struct sh_tmu_channel *ch = dev_id; |
9570ef20 MD |
232 | |
233 | /* disable or acknowledge interrupt */ | |
2bcc4da3 | 234 | if (clockevent_state_oneshot(&ch->ced)) |
5cfe2d15 | 235 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
9570ef20 | 236 | else |
5cfe2d15 | 237 | sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
9570ef20 MD |
238 | |
239 | /* notify clockevent layer */ | |
de2d12c7 | 240 | ch->ced.event_handler(&ch->ced); |
9570ef20 MD |
241 | return IRQ_HANDLED; |
242 | } | |
243 | ||
de2d12c7 | 244 | static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) |
9570ef20 | 245 | { |
de2d12c7 | 246 | return container_of(cs, struct sh_tmu_channel, cs); |
9570ef20 MD |
247 | } |
248 | ||
a5a1d1c2 | 249 | static u64 sh_tmu_clocksource_read(struct clocksource *cs) |
9570ef20 | 250 | { |
de2d12c7 | 251 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
9570ef20 | 252 | |
de2d12c7 | 253 | return sh_tmu_read(ch, TCNT) ^ 0xffffffff; |
9570ef20 MD |
254 | } |
255 | ||
256 | static int sh_tmu_clocksource_enable(struct clocksource *cs) | |
257 | { | |
de2d12c7 | 258 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
0aeac458 | 259 | int ret; |
9570ef20 | 260 | |
de2d12c7 | 261 | if (WARN_ON(ch->cs_enabled)) |
61a53bfa RW |
262 | return 0; |
263 | ||
de2d12c7 | 264 | ret = sh_tmu_enable(ch); |
c3c0a20d | 265 | if (!ret) |
de2d12c7 | 266 | ch->cs_enabled = true; |
61a53bfa | 267 | |
0aeac458 | 268 | return ret; |
9570ef20 MD |
269 | } |
270 | ||
271 | static void sh_tmu_clocksource_disable(struct clocksource *cs) | |
272 | { | |
de2d12c7 | 273 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 274 | |
de2d12c7 | 275 | if (WARN_ON(!ch->cs_enabled)) |
61a53bfa | 276 | return; |
eaa49a8c | 277 | |
de2d12c7 LP |
278 | sh_tmu_disable(ch); |
279 | ch->cs_enabled = false; | |
eaa49a8c RW |
280 | } |
281 | ||
282 | static void sh_tmu_clocksource_suspend(struct clocksource *cs) | |
283 | { | |
de2d12c7 | 284 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 285 | |
de2d12c7 | 286 | if (!ch->cs_enabled) |
61a53bfa | 287 | return; |
eaa49a8c | 288 | |
de2d12c7 LP |
289 | if (--ch->enable_count == 0) { |
290 | __sh_tmu_disable(ch); | |
291 | pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev); | |
61a53bfa | 292 | } |
eaa49a8c RW |
293 | } |
294 | ||
295 | static void sh_tmu_clocksource_resume(struct clocksource *cs) | |
296 | { | |
de2d12c7 | 297 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 298 | |
de2d12c7 | 299 | if (!ch->cs_enabled) |
61a53bfa RW |
300 | return; |
301 | ||
de2d12c7 LP |
302 | if (ch->enable_count++ == 0) { |
303 | pm_genpd_syscore_poweron(&ch->tmu->pdev->dev); | |
304 | __sh_tmu_enable(ch); | |
61a53bfa | 305 | } |
9570ef20 MD |
306 | } |
307 | ||
de2d12c7 | 308 | static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, |
f1010ed1 | 309 | const char *name) |
9570ef20 | 310 | { |
de2d12c7 | 311 | struct clocksource *cs = &ch->cs; |
9570ef20 MD |
312 | |
313 | cs->name = name; | |
f1010ed1 | 314 | cs->rating = 200; |
9570ef20 MD |
315 | cs->read = sh_tmu_clocksource_read; |
316 | cs->enable = sh_tmu_clocksource_enable; | |
317 | cs->disable = sh_tmu_clocksource_disable; | |
eaa49a8c RW |
318 | cs->suspend = sh_tmu_clocksource_suspend; |
319 | cs->resume = sh_tmu_clocksource_resume; | |
9570ef20 MD |
320 | cs->mask = CLOCKSOURCE_MASK(32); |
321 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
66f49121 | 322 | |
fe68eb80 LP |
323 | dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", |
324 | ch->index); | |
0aeac458 | 325 | |
c3c0a20d | 326 | clocksource_register_hz(cs, ch->tmu->rate); |
9570ef20 MD |
327 | return 0; |
328 | } | |
329 | ||
de2d12c7 | 330 | static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) |
9570ef20 | 331 | { |
de2d12c7 | 332 | return container_of(ced, struct sh_tmu_channel, ced); |
9570ef20 MD |
333 | } |
334 | ||
de2d12c7 | 335 | static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) |
9570ef20 | 336 | { |
de2d12c7 | 337 | sh_tmu_enable(ch); |
9570ef20 | 338 | |
9570ef20 | 339 | if (periodic) { |
c3c0a20d | 340 | ch->periodic = (ch->tmu->rate + HZ/2) / HZ; |
de2d12c7 | 341 | sh_tmu_set_next(ch, ch->periodic, 1); |
9570ef20 MD |
342 | } |
343 | } | |
344 | ||
2bcc4da3 VK |
345 | static int sh_tmu_clock_event_shutdown(struct clock_event_device *ced) |
346 | { | |
347 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); | |
348 | ||
452b1324 VK |
349 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
350 | sh_tmu_disable(ch); | |
2bcc4da3 VK |
351 | return 0; |
352 | } | |
353 | ||
354 | static int sh_tmu_clock_event_set_state(struct clock_event_device *ced, | |
355 | int periodic) | |
9570ef20 | 356 | { |
de2d12c7 | 357 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
9570ef20 MD |
358 | |
359 | /* deal with old setting first */ | |
2bcc4da3 | 360 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
de2d12c7 | 361 | sh_tmu_disable(ch); |
9570ef20 | 362 | |
2bcc4da3 VK |
363 | dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", |
364 | ch->index, periodic ? "periodic" : "oneshot"); | |
365 | sh_tmu_clock_event_start(ch, periodic); | |
366 | return 0; | |
367 | } | |
368 | ||
369 | static int sh_tmu_clock_event_set_oneshot(struct clock_event_device *ced) | |
370 | { | |
371 | return sh_tmu_clock_event_set_state(ced, 0); | |
372 | } | |
373 | ||
374 | static int sh_tmu_clock_event_set_periodic(struct clock_event_device *ced) | |
375 | { | |
376 | return sh_tmu_clock_event_set_state(ced, 1); | |
9570ef20 MD |
377 | } |
378 | ||
379 | static int sh_tmu_clock_event_next(unsigned long delta, | |
380 | struct clock_event_device *ced) | |
381 | { | |
de2d12c7 | 382 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
9570ef20 | 383 | |
2bcc4da3 | 384 | BUG_ON(!clockevent_state_oneshot(ced)); |
9570ef20 MD |
385 | |
386 | /* program new delta value */ | |
de2d12c7 | 387 | sh_tmu_set_next(ch, delta, 0); |
9570ef20 MD |
388 | return 0; |
389 | } | |
390 | ||
eaa49a8c RW |
391 | static void sh_tmu_clock_event_suspend(struct clock_event_device *ced) |
392 | { | |
de2d12c7 | 393 | pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
eaa49a8c RW |
394 | } |
395 | ||
396 | static void sh_tmu_clock_event_resume(struct clock_event_device *ced) | |
397 | { | |
de2d12c7 | 398 | pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
eaa49a8c RW |
399 | } |
400 | ||
de2d12c7 | 401 | static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, |
f1010ed1 | 402 | const char *name) |
9570ef20 | 403 | { |
de2d12c7 | 404 | struct clock_event_device *ced = &ch->ced; |
9570ef20 MD |
405 | int ret; |
406 | ||
9570ef20 MD |
407 | ced->name = name; |
408 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
409 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
f1010ed1 | 410 | ced->rating = 200; |
f2a54738 | 411 | ced->cpumask = cpu_possible_mask; |
9570ef20 | 412 | ced->set_next_event = sh_tmu_clock_event_next; |
2bcc4da3 VK |
413 | ced->set_state_shutdown = sh_tmu_clock_event_shutdown; |
414 | ced->set_state_periodic = sh_tmu_clock_event_set_periodic; | |
415 | ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; | |
eaa49a8c RW |
416 | ced->suspend = sh_tmu_clock_event_suspend; |
417 | ced->resume = sh_tmu_clock_event_resume; | |
9570ef20 | 418 | |
fe68eb80 LP |
419 | dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", |
420 | ch->index); | |
3977407e | 421 | |
c3c0a20d | 422 | clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); |
da64c2a8 | 423 | |
de2d12c7 | 424 | ret = request_irq(ch->irq, sh_tmu_interrupt, |
1c56cf6b | 425 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, |
de2d12c7 | 426 | dev_name(&ch->tmu->pdev->dev), ch); |
9570ef20 | 427 | if (ret) { |
fe68eb80 LP |
428 | dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", |
429 | ch->index, ch->irq); | |
9570ef20 MD |
430 | return; |
431 | } | |
9570ef20 MD |
432 | } |
433 | ||
84876d05 | 434 | static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, |
f1010ed1 | 435 | bool clockevent, bool clocksource) |
9570ef20 | 436 | { |
8c7f21e6 LP |
437 | if (clockevent) { |
438 | ch->tmu->has_clockevent = true; | |
f1010ed1 | 439 | sh_tmu_register_clockevent(ch, name); |
8c7f21e6 LP |
440 | } else if (clocksource) { |
441 | ch->tmu->has_clocksource = true; | |
f1010ed1 | 442 | sh_tmu_register_clocksource(ch, name); |
8c7f21e6 | 443 | } |
9570ef20 MD |
444 | |
445 | return 0; | |
446 | } | |
447 | ||
8c7f21e6 LP |
448 | static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, |
449 | bool clockevent, bool clocksource, | |
a94ddaa6 LP |
450 | struct sh_tmu_device *tmu) |
451 | { | |
8c7f21e6 LP |
452 | /* Skip unused channels. */ |
453 | if (!clockevent && !clocksource) | |
454 | return 0; | |
a94ddaa6 | 455 | |
a94ddaa6 | 456 | ch->tmu = tmu; |
681b9e85 | 457 | ch->index = index; |
a94ddaa6 | 458 | |
681b9e85 LP |
459 | if (tmu->model == SH_TMU_SH3) |
460 | ch->base = tmu->mapbase + 4 + ch->index * 12; | |
461 | else | |
462 | ch->base = tmu->mapbase + 8 + ch->index * 12; | |
fe68eb80 | 463 | |
c54697ae | 464 | ch->irq = platform_get_irq(tmu->pdev, index); |
a94ddaa6 | 465 | if (ch->irq < 0) { |
fe68eb80 LP |
466 | dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n", |
467 | ch->index); | |
a94ddaa6 LP |
468 | return ch->irq; |
469 | } | |
470 | ||
471 | ch->cs_enabled = false; | |
472 | ch->enable_count = 0; | |
473 | ||
84876d05 | 474 | return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), |
8c7f21e6 | 475 | clockevent, clocksource); |
a94ddaa6 LP |
476 | } |
477 | ||
8c7f21e6 | 478 | static int sh_tmu_map_memory(struct sh_tmu_device *tmu) |
9570ef20 | 479 | { |
9570ef20 | 480 | struct resource *res; |
9570ef20 | 481 | |
0a72aa39 | 482 | res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); |
9570ef20 | 483 | if (!res) { |
0a72aa39 | 484 | dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); |
8c7f21e6 | 485 | return -ENXIO; |
9570ef20 MD |
486 | } |
487 | ||
8c7f21e6 LP |
488 | tmu->mapbase = ioremap_nocache(res->start, resource_size(res)); |
489 | if (tmu->mapbase == NULL) | |
490 | return -ENXIO; | |
491 | ||
8c7f21e6 LP |
492 | return 0; |
493 | } | |
de693461 | 494 | |
3e29b554 LP |
495 | static int sh_tmu_parse_dt(struct sh_tmu_device *tmu) |
496 | { | |
497 | struct device_node *np = tmu->pdev->dev.of_node; | |
498 | ||
499 | tmu->model = SH_TMU; | |
500 | tmu->num_channels = 3; | |
501 | ||
502 | of_property_read_u32(np, "#renesas,channels", &tmu->num_channels); | |
503 | ||
504 | if (tmu->num_channels != 2 && tmu->num_channels != 3) { | |
505 | dev_err(&tmu->pdev->dev, "invalid number of channels %u\n", | |
506 | tmu->num_channels); | |
507 | return -EINVAL; | |
508 | } | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
8c7f21e6 LP |
513 | static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) |
514 | { | |
8c7f21e6 LP |
515 | unsigned int i; |
516 | int ret; | |
517 | ||
8c7f21e6 | 518 | tmu->pdev = pdev; |
8c7f21e6 | 519 | |
2b027f1f LP |
520 | raw_spin_lock_init(&tmu->lock); |
521 | ||
3e29b554 LP |
522 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
523 | ret = sh_tmu_parse_dt(tmu); | |
524 | if (ret < 0) | |
525 | return ret; | |
526 | } else if (pdev->dev.platform_data) { | |
527 | const struct platform_device_id *id = pdev->id_entry; | |
528 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
529 | ||
530 | tmu->model = id->driver_data; | |
531 | tmu->num_channels = hweight8(cfg->channels_mask); | |
532 | } else { | |
533 | dev_err(&tmu->pdev->dev, "missing platform data\n"); | |
534 | return -ENXIO; | |
535 | } | |
536 | ||
8c7f21e6 | 537 | /* Get hold of clock. */ |
681b9e85 | 538 | tmu->clk = clk_get(&tmu->pdev->dev, "fck"); |
0a72aa39 LP |
539 | if (IS_ERR(tmu->clk)) { |
540 | dev_err(&tmu->pdev->dev, "cannot get clock\n"); | |
8c7f21e6 | 541 | return PTR_ERR(tmu->clk); |
9570ef20 | 542 | } |
1c09eb3e | 543 | |
0a72aa39 | 544 | ret = clk_prepare(tmu->clk); |
1c09eb3e | 545 | if (ret < 0) |
8c7f21e6 LP |
546 | goto err_clk_put; |
547 | ||
c3c0a20d NS |
548 | /* Determine clock rate. */ |
549 | ret = clk_enable(tmu->clk); | |
550 | if (ret < 0) | |
551 | goto err_clk_unprepare; | |
552 | ||
553 | tmu->rate = clk_get_rate(tmu->clk) / 4; | |
554 | clk_disable(tmu->clk); | |
555 | ||
8c7f21e6 LP |
556 | /* Map the memory resource. */ |
557 | ret = sh_tmu_map_memory(tmu); | |
558 | if (ret < 0) { | |
559 | dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); | |
560 | goto err_clk_unprepare; | |
561 | } | |
1c09eb3e | 562 | |
8c7f21e6 | 563 | /* Allocate and setup the channels. */ |
6396bb22 | 564 | tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels), |
8c7f21e6 | 565 | GFP_KERNEL); |
a5de49f4 LP |
566 | if (tmu->channels == NULL) { |
567 | ret = -ENOMEM; | |
8c7f21e6 | 568 | goto err_unmap; |
a5de49f4 LP |
569 | } |
570 | ||
681b9e85 LP |
571 | /* |
572 | * Use the first channel as a clock event device and the second channel | |
573 | * as a clock source. | |
574 | */ | |
575 | for (i = 0; i < tmu->num_channels; ++i) { | |
576 | ret = sh_tmu_channel_setup(&tmu->channels[i], i, | |
577 | i == 0, i == 1, tmu); | |
8c7f21e6 LP |
578 | if (ret < 0) |
579 | goto err_unmap; | |
8c7f21e6 | 580 | } |
a5de49f4 | 581 | |
8c7f21e6 | 582 | platform_set_drvdata(pdev, tmu); |
394a4486 LP |
583 | |
584 | return 0; | |
585 | ||
8c7f21e6 | 586 | err_unmap: |
a5de49f4 | 587 | kfree(tmu->channels); |
681b9e85 | 588 | iounmap(tmu->mapbase); |
8c7f21e6 | 589 | err_clk_unprepare: |
0a72aa39 | 590 | clk_unprepare(tmu->clk); |
8c7f21e6 | 591 | err_clk_put: |
0a72aa39 | 592 | clk_put(tmu->clk); |
9570ef20 MD |
593 | return ret; |
594 | } | |
595 | ||
1850514b | 596 | static int sh_tmu_probe(struct platform_device *pdev) |
9570ef20 | 597 | { |
0a72aa39 | 598 | struct sh_tmu_device *tmu = platform_get_drvdata(pdev); |
9570ef20 MD |
599 | int ret; |
600 | ||
eaa49a8c | 601 | if (!is_early_platform_device(pdev)) { |
61a53bfa RW |
602 | pm_runtime_set_active(&pdev->dev); |
603 | pm_runtime_enable(&pdev->dev); | |
eaa49a8c | 604 | } |
2ee619f9 | 605 | |
0a72aa39 | 606 | if (tmu) { |
214a607a | 607 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
61a53bfa | 608 | goto out; |
9570ef20 MD |
609 | } |
610 | ||
3b77a83e | 611 | tmu = kzalloc(sizeof(*tmu), GFP_KERNEL); |
814876b0 | 612 | if (tmu == NULL) |
9570ef20 | 613 | return -ENOMEM; |
9570ef20 | 614 | |
0a72aa39 | 615 | ret = sh_tmu_setup(tmu, pdev); |
9570ef20 | 616 | if (ret) { |
0a72aa39 | 617 | kfree(tmu); |
61a53bfa RW |
618 | pm_runtime_idle(&pdev->dev); |
619 | return ret; | |
9570ef20 | 620 | } |
61a53bfa RW |
621 | if (is_early_platform_device(pdev)) |
622 | return 0; | |
623 | ||
624 | out: | |
8c7f21e6 | 625 | if (tmu->has_clockevent || tmu->has_clocksource) |
61a53bfa RW |
626 | pm_runtime_irq_safe(&pdev->dev); |
627 | else | |
628 | pm_runtime_idle(&pdev->dev); | |
629 | ||
630 | return 0; | |
9570ef20 MD |
631 | } |
632 | ||
1850514b | 633 | static int sh_tmu_remove(struct platform_device *pdev) |
9570ef20 MD |
634 | { |
635 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
636 | } | |
637 | ||
8c7f21e6 | 638 | static const struct platform_device_id sh_tmu_id_table[] = { |
8c7f21e6 LP |
639 | { "sh-tmu", SH_TMU }, |
640 | { "sh-tmu-sh3", SH_TMU_SH3 }, | |
641 | { } | |
642 | }; | |
643 | MODULE_DEVICE_TABLE(platform, sh_tmu_id_table); | |
644 | ||
3e29b554 LP |
645 | static const struct of_device_id sh_tmu_of_table[] __maybe_unused = { |
646 | { .compatible = "renesas,tmu" }, | |
647 | { } | |
648 | }; | |
649 | MODULE_DEVICE_TABLE(of, sh_tmu_of_table); | |
650 | ||
9570ef20 MD |
651 | static struct platform_driver sh_tmu_device_driver = { |
652 | .probe = sh_tmu_probe, | |
1850514b | 653 | .remove = sh_tmu_remove, |
9570ef20 MD |
654 | .driver = { |
655 | .name = "sh_tmu", | |
3e29b554 | 656 | .of_match_table = of_match_ptr(sh_tmu_of_table), |
8c7f21e6 LP |
657 | }, |
658 | .id_table = sh_tmu_id_table, | |
9570ef20 MD |
659 | }; |
660 | ||
661 | static int __init sh_tmu_init(void) | |
662 | { | |
663 | return platform_driver_register(&sh_tmu_device_driver); | |
664 | } | |
665 | ||
666 | static void __exit sh_tmu_exit(void) | |
667 | { | |
668 | platform_driver_unregister(&sh_tmu_device_driver); | |
669 | } | |
670 | ||
671 | early_platform_init("earlytimer", &sh_tmu_device_driver); | |
b9773c3f | 672 | subsys_initcall(sh_tmu_init); |
9570ef20 MD |
673 | module_exit(sh_tmu_exit); |
674 | ||
675 | MODULE_AUTHOR("Magnus Damm"); | |
676 | MODULE_DESCRIPTION("SuperH TMU Timer Driver"); | |
677 | MODULE_LICENSE("GPL v2"); |