Commit | Line | Data |
---|---|---|
9570ef20 MD |
1 | /* |
2 | * SuperH Timer Support - TMU | |
3 | * | |
4 | * Copyright (C) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
9570ef20 MD |
14 | */ |
15 | ||
13931f80 LP |
16 | #include <linux/clk.h> |
17 | #include <linux/clockchips.h> | |
18 | #include <linux/clocksource.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
9570ef20 | 21 | #include <linux/init.h> |
9570ef20 | 22 | #include <linux/interrupt.h> |
9570ef20 | 23 | #include <linux/io.h> |
13931f80 | 24 | #include <linux/ioport.h> |
9570ef20 | 25 | #include <linux/irq.h> |
7deeab5d | 26 | #include <linux/module.h> |
3e29b554 | 27 | #include <linux/of.h> |
13931f80 | 28 | #include <linux/platform_device.h> |
2ee619f9 | 29 | #include <linux/pm_domain.h> |
eaa49a8c | 30 | #include <linux/pm_runtime.h> |
13931f80 LP |
31 | #include <linux/sh_timer.h> |
32 | #include <linux/slab.h> | |
33 | #include <linux/spinlock.h> | |
9570ef20 | 34 | |
8c7f21e6 | 35 | enum sh_tmu_model { |
8c7f21e6 LP |
36 | SH_TMU, |
37 | SH_TMU_SH3, | |
38 | }; | |
39 | ||
0a72aa39 | 40 | struct sh_tmu_device; |
de2d12c7 LP |
41 | |
42 | struct sh_tmu_channel { | |
0a72aa39 | 43 | struct sh_tmu_device *tmu; |
fe68eb80 | 44 | unsigned int index; |
de2d12c7 | 45 | |
de693461 | 46 | void __iomem *base; |
1c56cf6b | 47 | int irq; |
de2d12c7 | 48 | |
9570ef20 MD |
49 | unsigned long periodic; |
50 | struct clock_event_device ced; | |
51 | struct clocksource cs; | |
eaa49a8c | 52 | bool cs_enabled; |
61a53bfa | 53 | unsigned int enable_count; |
9570ef20 MD |
54 | }; |
55 | ||
0a72aa39 | 56 | struct sh_tmu_device { |
de2d12c7 LP |
57 | struct platform_device *pdev; |
58 | ||
59 | void __iomem *mapbase; | |
60 | struct clk *clk; | |
c3c0a20d | 61 | unsigned long rate; |
de2d12c7 | 62 | |
8c7f21e6 LP |
63 | enum sh_tmu_model model; |
64 | ||
2b027f1f LP |
65 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
66 | ||
a5de49f4 LP |
67 | struct sh_tmu_channel *channels; |
68 | unsigned int num_channels; | |
8c7f21e6 LP |
69 | |
70 | bool has_clockevent; | |
71 | bool has_clocksource; | |
de2d12c7 LP |
72 | }; |
73 | ||
9570ef20 MD |
74 | #define TSTR -1 /* shared register */ |
75 | #define TCOR 0 /* channel register */ | |
76 | #define TCNT 1 /* channel register */ | |
77 | #define TCR 2 /* channel register */ | |
78 | ||
5cfe2d15 LP |
79 | #define TCR_UNF (1 << 8) |
80 | #define TCR_UNIE (1 << 5) | |
81 | #define TCR_TPSC_CLK4 (0 << 0) | |
82 | #define TCR_TPSC_CLK16 (1 << 0) | |
83 | #define TCR_TPSC_CLK64 (2 << 0) | |
84 | #define TCR_TPSC_CLK256 (3 << 0) | |
85 | #define TCR_TPSC_CLK1024 (4 << 0) | |
86 | #define TCR_TPSC_MASK (7 << 0) | |
87 | ||
de2d12c7 | 88 | static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) |
9570ef20 | 89 | { |
9570ef20 MD |
90 | unsigned long offs; |
91 | ||
8c7f21e6 LP |
92 | if (reg_nr == TSTR) { |
93 | switch (ch->tmu->model) { | |
8c7f21e6 LP |
94 | case SH_TMU_SH3: |
95 | return ioread8(ch->tmu->mapbase + 2); | |
96 | case SH_TMU: | |
97 | return ioread8(ch->tmu->mapbase + 4); | |
98 | } | |
99 | } | |
9570ef20 MD |
100 | |
101 | offs = reg_nr << 2; | |
102 | ||
103 | if (reg_nr == TCR) | |
de693461 | 104 | return ioread16(ch->base + offs); |
9570ef20 | 105 | else |
de693461 | 106 | return ioread32(ch->base + offs); |
9570ef20 MD |
107 | } |
108 | ||
de2d12c7 | 109 | static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, |
9570ef20 MD |
110 | unsigned long value) |
111 | { | |
9570ef20 MD |
112 | unsigned long offs; |
113 | ||
114 | if (reg_nr == TSTR) { | |
8c7f21e6 | 115 | switch (ch->tmu->model) { |
8c7f21e6 LP |
116 | case SH_TMU_SH3: |
117 | return iowrite8(value, ch->tmu->mapbase + 2); | |
118 | case SH_TMU: | |
119 | return iowrite8(value, ch->tmu->mapbase + 4); | |
120 | } | |
9570ef20 MD |
121 | } |
122 | ||
123 | offs = reg_nr << 2; | |
124 | ||
125 | if (reg_nr == TCR) | |
de693461 | 126 | iowrite16(value, ch->base + offs); |
9570ef20 | 127 | else |
de693461 | 128 | iowrite32(value, ch->base + offs); |
9570ef20 MD |
129 | } |
130 | ||
de2d12c7 | 131 | static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) |
9570ef20 | 132 | { |
9570ef20 MD |
133 | unsigned long flags, value; |
134 | ||
135 | /* start stop register shared by multiple timer channels */ | |
2b027f1f | 136 | raw_spin_lock_irqsave(&ch->tmu->lock, flags); |
de2d12c7 | 137 | value = sh_tmu_read(ch, TSTR); |
9570ef20 MD |
138 | |
139 | if (start) | |
fe68eb80 | 140 | value |= 1 << ch->index; |
9570ef20 | 141 | else |
fe68eb80 | 142 | value &= ~(1 << ch->index); |
9570ef20 | 143 | |
de2d12c7 | 144 | sh_tmu_write(ch, TSTR, value); |
2b027f1f | 145 | raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); |
9570ef20 MD |
146 | } |
147 | ||
de2d12c7 | 148 | static int __sh_tmu_enable(struct sh_tmu_channel *ch) |
9570ef20 | 149 | { |
9570ef20 MD |
150 | int ret; |
151 | ||
d4905ce3 | 152 | /* enable clock */ |
de2d12c7 | 153 | ret = clk_enable(ch->tmu->clk); |
9570ef20 | 154 | if (ret) { |
fe68eb80 LP |
155 | dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", |
156 | ch->index); | |
9570ef20 MD |
157 | return ret; |
158 | } | |
159 | ||
160 | /* make sure channel is disabled */ | |
de2d12c7 | 161 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 MD |
162 | |
163 | /* maximum timeout */ | |
de2d12c7 LP |
164 | sh_tmu_write(ch, TCOR, 0xffffffff); |
165 | sh_tmu_write(ch, TCNT, 0xffffffff); | |
9570ef20 MD |
166 | |
167 | /* configure channel to parent clock / 4, irq off */ | |
5cfe2d15 | 168 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
9570ef20 MD |
169 | |
170 | /* enable channel */ | |
de2d12c7 | 171 | sh_tmu_start_stop_ch(ch, 1); |
9570ef20 MD |
172 | |
173 | return 0; | |
174 | } | |
175 | ||
de2d12c7 | 176 | static int sh_tmu_enable(struct sh_tmu_channel *ch) |
61a53bfa | 177 | { |
de2d12c7 | 178 | if (ch->enable_count++ > 0) |
61a53bfa RW |
179 | return 0; |
180 | ||
de2d12c7 LP |
181 | pm_runtime_get_sync(&ch->tmu->pdev->dev); |
182 | dev_pm_syscore_device(&ch->tmu->pdev->dev, true); | |
61a53bfa | 183 | |
de2d12c7 | 184 | return __sh_tmu_enable(ch); |
61a53bfa RW |
185 | } |
186 | ||
de2d12c7 | 187 | static void __sh_tmu_disable(struct sh_tmu_channel *ch) |
9570ef20 MD |
188 | { |
189 | /* disable channel */ | |
de2d12c7 | 190 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 | 191 | |
be890a1a | 192 | /* disable interrupts in TMU block */ |
5cfe2d15 | 193 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
be890a1a | 194 | |
d4905ce3 | 195 | /* stop clock */ |
de2d12c7 | 196 | clk_disable(ch->tmu->clk); |
9570ef20 MD |
197 | } |
198 | ||
de2d12c7 | 199 | static void sh_tmu_disable(struct sh_tmu_channel *ch) |
61a53bfa | 200 | { |
de2d12c7 | 201 | if (WARN_ON(ch->enable_count == 0)) |
61a53bfa RW |
202 | return; |
203 | ||
de2d12c7 | 204 | if (--ch->enable_count > 0) |
61a53bfa RW |
205 | return; |
206 | ||
de2d12c7 | 207 | __sh_tmu_disable(ch); |
61a53bfa | 208 | |
de2d12c7 LP |
209 | dev_pm_syscore_device(&ch->tmu->pdev->dev, false); |
210 | pm_runtime_put(&ch->tmu->pdev->dev); | |
61a53bfa RW |
211 | } |
212 | ||
de2d12c7 | 213 | static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, |
9570ef20 MD |
214 | int periodic) |
215 | { | |
216 | /* stop timer */ | |
de2d12c7 | 217 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 MD |
218 | |
219 | /* acknowledge interrupt */ | |
de2d12c7 | 220 | sh_tmu_read(ch, TCR); |
9570ef20 MD |
221 | |
222 | /* enable interrupt */ | |
5cfe2d15 | 223 | sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
9570ef20 MD |
224 | |
225 | /* reload delta value in case of periodic timer */ | |
226 | if (periodic) | |
de2d12c7 | 227 | sh_tmu_write(ch, TCOR, delta); |
9570ef20 | 228 | else |
de2d12c7 | 229 | sh_tmu_write(ch, TCOR, 0xffffffff); |
9570ef20 | 230 | |
de2d12c7 | 231 | sh_tmu_write(ch, TCNT, delta); |
9570ef20 MD |
232 | |
233 | /* start timer */ | |
de2d12c7 | 234 | sh_tmu_start_stop_ch(ch, 1); |
9570ef20 MD |
235 | } |
236 | ||
237 | static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) | |
238 | { | |
de2d12c7 | 239 | struct sh_tmu_channel *ch = dev_id; |
9570ef20 MD |
240 | |
241 | /* disable or acknowledge interrupt */ | |
2bcc4da3 | 242 | if (clockevent_state_oneshot(&ch->ced)) |
5cfe2d15 | 243 | sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
9570ef20 | 244 | else |
5cfe2d15 | 245 | sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
9570ef20 MD |
246 | |
247 | /* notify clockevent layer */ | |
de2d12c7 | 248 | ch->ced.event_handler(&ch->ced); |
9570ef20 MD |
249 | return IRQ_HANDLED; |
250 | } | |
251 | ||
de2d12c7 | 252 | static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) |
9570ef20 | 253 | { |
de2d12c7 | 254 | return container_of(cs, struct sh_tmu_channel, cs); |
9570ef20 MD |
255 | } |
256 | ||
a5a1d1c2 | 257 | static u64 sh_tmu_clocksource_read(struct clocksource *cs) |
9570ef20 | 258 | { |
de2d12c7 | 259 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
9570ef20 | 260 | |
de2d12c7 | 261 | return sh_tmu_read(ch, TCNT) ^ 0xffffffff; |
9570ef20 MD |
262 | } |
263 | ||
264 | static int sh_tmu_clocksource_enable(struct clocksource *cs) | |
265 | { | |
de2d12c7 | 266 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
0aeac458 | 267 | int ret; |
9570ef20 | 268 | |
de2d12c7 | 269 | if (WARN_ON(ch->cs_enabled)) |
61a53bfa RW |
270 | return 0; |
271 | ||
de2d12c7 | 272 | ret = sh_tmu_enable(ch); |
c3c0a20d | 273 | if (!ret) |
de2d12c7 | 274 | ch->cs_enabled = true; |
61a53bfa | 275 | |
0aeac458 | 276 | return ret; |
9570ef20 MD |
277 | } |
278 | ||
279 | static void sh_tmu_clocksource_disable(struct clocksource *cs) | |
280 | { | |
de2d12c7 | 281 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 282 | |
de2d12c7 | 283 | if (WARN_ON(!ch->cs_enabled)) |
61a53bfa | 284 | return; |
eaa49a8c | 285 | |
de2d12c7 LP |
286 | sh_tmu_disable(ch); |
287 | ch->cs_enabled = false; | |
eaa49a8c RW |
288 | } |
289 | ||
290 | static void sh_tmu_clocksource_suspend(struct clocksource *cs) | |
291 | { | |
de2d12c7 | 292 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 293 | |
de2d12c7 | 294 | if (!ch->cs_enabled) |
61a53bfa | 295 | return; |
eaa49a8c | 296 | |
de2d12c7 LP |
297 | if (--ch->enable_count == 0) { |
298 | __sh_tmu_disable(ch); | |
299 | pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev); | |
61a53bfa | 300 | } |
eaa49a8c RW |
301 | } |
302 | ||
303 | static void sh_tmu_clocksource_resume(struct clocksource *cs) | |
304 | { | |
de2d12c7 | 305 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 306 | |
de2d12c7 | 307 | if (!ch->cs_enabled) |
61a53bfa RW |
308 | return; |
309 | ||
de2d12c7 LP |
310 | if (ch->enable_count++ == 0) { |
311 | pm_genpd_syscore_poweron(&ch->tmu->pdev->dev); | |
312 | __sh_tmu_enable(ch); | |
61a53bfa | 313 | } |
9570ef20 MD |
314 | } |
315 | ||
de2d12c7 | 316 | static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, |
f1010ed1 | 317 | const char *name) |
9570ef20 | 318 | { |
de2d12c7 | 319 | struct clocksource *cs = &ch->cs; |
9570ef20 MD |
320 | |
321 | cs->name = name; | |
f1010ed1 | 322 | cs->rating = 200; |
9570ef20 MD |
323 | cs->read = sh_tmu_clocksource_read; |
324 | cs->enable = sh_tmu_clocksource_enable; | |
325 | cs->disable = sh_tmu_clocksource_disable; | |
eaa49a8c RW |
326 | cs->suspend = sh_tmu_clocksource_suspend; |
327 | cs->resume = sh_tmu_clocksource_resume; | |
9570ef20 MD |
328 | cs->mask = CLOCKSOURCE_MASK(32); |
329 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
66f49121 | 330 | |
fe68eb80 LP |
331 | dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", |
332 | ch->index); | |
0aeac458 | 333 | |
c3c0a20d | 334 | clocksource_register_hz(cs, ch->tmu->rate); |
9570ef20 MD |
335 | return 0; |
336 | } | |
337 | ||
de2d12c7 | 338 | static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) |
9570ef20 | 339 | { |
de2d12c7 | 340 | return container_of(ced, struct sh_tmu_channel, ced); |
9570ef20 MD |
341 | } |
342 | ||
de2d12c7 | 343 | static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) |
9570ef20 | 344 | { |
de2d12c7 | 345 | sh_tmu_enable(ch); |
9570ef20 | 346 | |
9570ef20 | 347 | if (periodic) { |
c3c0a20d | 348 | ch->periodic = (ch->tmu->rate + HZ/2) / HZ; |
de2d12c7 | 349 | sh_tmu_set_next(ch, ch->periodic, 1); |
9570ef20 MD |
350 | } |
351 | } | |
352 | ||
2bcc4da3 VK |
353 | static int sh_tmu_clock_event_shutdown(struct clock_event_device *ced) |
354 | { | |
355 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); | |
356 | ||
452b1324 VK |
357 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
358 | sh_tmu_disable(ch); | |
2bcc4da3 VK |
359 | return 0; |
360 | } | |
361 | ||
362 | static int sh_tmu_clock_event_set_state(struct clock_event_device *ced, | |
363 | int periodic) | |
9570ef20 | 364 | { |
de2d12c7 | 365 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
9570ef20 MD |
366 | |
367 | /* deal with old setting first */ | |
2bcc4da3 | 368 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
de2d12c7 | 369 | sh_tmu_disable(ch); |
9570ef20 | 370 | |
2bcc4da3 VK |
371 | dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", |
372 | ch->index, periodic ? "periodic" : "oneshot"); | |
373 | sh_tmu_clock_event_start(ch, periodic); | |
374 | return 0; | |
375 | } | |
376 | ||
377 | static int sh_tmu_clock_event_set_oneshot(struct clock_event_device *ced) | |
378 | { | |
379 | return sh_tmu_clock_event_set_state(ced, 0); | |
380 | } | |
381 | ||
382 | static int sh_tmu_clock_event_set_periodic(struct clock_event_device *ced) | |
383 | { | |
384 | return sh_tmu_clock_event_set_state(ced, 1); | |
9570ef20 MD |
385 | } |
386 | ||
387 | static int sh_tmu_clock_event_next(unsigned long delta, | |
388 | struct clock_event_device *ced) | |
389 | { | |
de2d12c7 | 390 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
9570ef20 | 391 | |
2bcc4da3 | 392 | BUG_ON(!clockevent_state_oneshot(ced)); |
9570ef20 MD |
393 | |
394 | /* program new delta value */ | |
de2d12c7 | 395 | sh_tmu_set_next(ch, delta, 0); |
9570ef20 MD |
396 | return 0; |
397 | } | |
398 | ||
eaa49a8c RW |
399 | static void sh_tmu_clock_event_suspend(struct clock_event_device *ced) |
400 | { | |
de2d12c7 | 401 | pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
eaa49a8c RW |
402 | } |
403 | ||
404 | static void sh_tmu_clock_event_resume(struct clock_event_device *ced) | |
405 | { | |
de2d12c7 | 406 | pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
eaa49a8c RW |
407 | } |
408 | ||
de2d12c7 | 409 | static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, |
f1010ed1 | 410 | const char *name) |
9570ef20 | 411 | { |
de2d12c7 | 412 | struct clock_event_device *ced = &ch->ced; |
9570ef20 MD |
413 | int ret; |
414 | ||
9570ef20 MD |
415 | ced->name = name; |
416 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
417 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
f1010ed1 | 418 | ced->rating = 200; |
f2a54738 | 419 | ced->cpumask = cpu_possible_mask; |
9570ef20 | 420 | ced->set_next_event = sh_tmu_clock_event_next; |
2bcc4da3 VK |
421 | ced->set_state_shutdown = sh_tmu_clock_event_shutdown; |
422 | ced->set_state_periodic = sh_tmu_clock_event_set_periodic; | |
423 | ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; | |
eaa49a8c RW |
424 | ced->suspend = sh_tmu_clock_event_suspend; |
425 | ced->resume = sh_tmu_clock_event_resume; | |
9570ef20 | 426 | |
fe68eb80 LP |
427 | dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", |
428 | ch->index); | |
3977407e | 429 | |
c3c0a20d | 430 | clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); |
da64c2a8 | 431 | |
de2d12c7 | 432 | ret = request_irq(ch->irq, sh_tmu_interrupt, |
1c56cf6b | 433 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, |
de2d12c7 | 434 | dev_name(&ch->tmu->pdev->dev), ch); |
9570ef20 | 435 | if (ret) { |
fe68eb80 LP |
436 | dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", |
437 | ch->index, ch->irq); | |
9570ef20 MD |
438 | return; |
439 | } | |
9570ef20 MD |
440 | } |
441 | ||
84876d05 | 442 | static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, |
f1010ed1 | 443 | bool clockevent, bool clocksource) |
9570ef20 | 444 | { |
8c7f21e6 LP |
445 | if (clockevent) { |
446 | ch->tmu->has_clockevent = true; | |
f1010ed1 | 447 | sh_tmu_register_clockevent(ch, name); |
8c7f21e6 LP |
448 | } else if (clocksource) { |
449 | ch->tmu->has_clocksource = true; | |
f1010ed1 | 450 | sh_tmu_register_clocksource(ch, name); |
8c7f21e6 | 451 | } |
9570ef20 MD |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
8c7f21e6 LP |
456 | static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, |
457 | bool clockevent, bool clocksource, | |
a94ddaa6 LP |
458 | struct sh_tmu_device *tmu) |
459 | { | |
8c7f21e6 LP |
460 | /* Skip unused channels. */ |
461 | if (!clockevent && !clocksource) | |
462 | return 0; | |
a94ddaa6 | 463 | |
a94ddaa6 | 464 | ch->tmu = tmu; |
681b9e85 | 465 | ch->index = index; |
a94ddaa6 | 466 | |
681b9e85 LP |
467 | if (tmu->model == SH_TMU_SH3) |
468 | ch->base = tmu->mapbase + 4 + ch->index * 12; | |
469 | else | |
470 | ch->base = tmu->mapbase + 8 + ch->index * 12; | |
fe68eb80 | 471 | |
c54697ae | 472 | ch->irq = platform_get_irq(tmu->pdev, index); |
a94ddaa6 | 473 | if (ch->irq < 0) { |
fe68eb80 LP |
474 | dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n", |
475 | ch->index); | |
a94ddaa6 LP |
476 | return ch->irq; |
477 | } | |
478 | ||
479 | ch->cs_enabled = false; | |
480 | ch->enable_count = 0; | |
481 | ||
84876d05 | 482 | return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), |
8c7f21e6 | 483 | clockevent, clocksource); |
a94ddaa6 LP |
484 | } |
485 | ||
8c7f21e6 | 486 | static int sh_tmu_map_memory(struct sh_tmu_device *tmu) |
9570ef20 | 487 | { |
9570ef20 | 488 | struct resource *res; |
9570ef20 | 489 | |
0a72aa39 | 490 | res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); |
9570ef20 | 491 | if (!res) { |
0a72aa39 | 492 | dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); |
8c7f21e6 | 493 | return -ENXIO; |
9570ef20 MD |
494 | } |
495 | ||
8c7f21e6 LP |
496 | tmu->mapbase = ioremap_nocache(res->start, resource_size(res)); |
497 | if (tmu->mapbase == NULL) | |
498 | return -ENXIO; | |
499 | ||
8c7f21e6 LP |
500 | return 0; |
501 | } | |
de693461 | 502 | |
3e29b554 LP |
503 | static int sh_tmu_parse_dt(struct sh_tmu_device *tmu) |
504 | { | |
505 | struct device_node *np = tmu->pdev->dev.of_node; | |
506 | ||
507 | tmu->model = SH_TMU; | |
508 | tmu->num_channels = 3; | |
509 | ||
510 | of_property_read_u32(np, "#renesas,channels", &tmu->num_channels); | |
511 | ||
512 | if (tmu->num_channels != 2 && tmu->num_channels != 3) { | |
513 | dev_err(&tmu->pdev->dev, "invalid number of channels %u\n", | |
514 | tmu->num_channels); | |
515 | return -EINVAL; | |
516 | } | |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
8c7f21e6 LP |
521 | static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) |
522 | { | |
8c7f21e6 LP |
523 | unsigned int i; |
524 | int ret; | |
525 | ||
8c7f21e6 | 526 | tmu->pdev = pdev; |
8c7f21e6 | 527 | |
2b027f1f LP |
528 | raw_spin_lock_init(&tmu->lock); |
529 | ||
3e29b554 LP |
530 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
531 | ret = sh_tmu_parse_dt(tmu); | |
532 | if (ret < 0) | |
533 | return ret; | |
534 | } else if (pdev->dev.platform_data) { | |
535 | const struct platform_device_id *id = pdev->id_entry; | |
536 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
537 | ||
538 | tmu->model = id->driver_data; | |
539 | tmu->num_channels = hweight8(cfg->channels_mask); | |
540 | } else { | |
541 | dev_err(&tmu->pdev->dev, "missing platform data\n"); | |
542 | return -ENXIO; | |
543 | } | |
544 | ||
8c7f21e6 | 545 | /* Get hold of clock. */ |
681b9e85 | 546 | tmu->clk = clk_get(&tmu->pdev->dev, "fck"); |
0a72aa39 LP |
547 | if (IS_ERR(tmu->clk)) { |
548 | dev_err(&tmu->pdev->dev, "cannot get clock\n"); | |
8c7f21e6 | 549 | return PTR_ERR(tmu->clk); |
9570ef20 | 550 | } |
1c09eb3e | 551 | |
0a72aa39 | 552 | ret = clk_prepare(tmu->clk); |
1c09eb3e | 553 | if (ret < 0) |
8c7f21e6 LP |
554 | goto err_clk_put; |
555 | ||
c3c0a20d NS |
556 | /* Determine clock rate. */ |
557 | ret = clk_enable(tmu->clk); | |
558 | if (ret < 0) | |
559 | goto err_clk_unprepare; | |
560 | ||
561 | tmu->rate = clk_get_rate(tmu->clk) / 4; | |
562 | clk_disable(tmu->clk); | |
563 | ||
8c7f21e6 LP |
564 | /* Map the memory resource. */ |
565 | ret = sh_tmu_map_memory(tmu); | |
566 | if (ret < 0) { | |
567 | dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); | |
568 | goto err_clk_unprepare; | |
569 | } | |
1c09eb3e | 570 | |
8c7f21e6 | 571 | /* Allocate and setup the channels. */ |
8c7f21e6 LP |
572 | tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels, |
573 | GFP_KERNEL); | |
a5de49f4 LP |
574 | if (tmu->channels == NULL) { |
575 | ret = -ENOMEM; | |
8c7f21e6 | 576 | goto err_unmap; |
a5de49f4 LP |
577 | } |
578 | ||
681b9e85 LP |
579 | /* |
580 | * Use the first channel as a clock event device and the second channel | |
581 | * as a clock source. | |
582 | */ | |
583 | for (i = 0; i < tmu->num_channels; ++i) { | |
584 | ret = sh_tmu_channel_setup(&tmu->channels[i], i, | |
585 | i == 0, i == 1, tmu); | |
8c7f21e6 LP |
586 | if (ret < 0) |
587 | goto err_unmap; | |
8c7f21e6 | 588 | } |
a5de49f4 | 589 | |
8c7f21e6 | 590 | platform_set_drvdata(pdev, tmu); |
394a4486 LP |
591 | |
592 | return 0; | |
593 | ||
8c7f21e6 | 594 | err_unmap: |
a5de49f4 | 595 | kfree(tmu->channels); |
681b9e85 | 596 | iounmap(tmu->mapbase); |
8c7f21e6 | 597 | err_clk_unprepare: |
0a72aa39 | 598 | clk_unprepare(tmu->clk); |
8c7f21e6 | 599 | err_clk_put: |
0a72aa39 | 600 | clk_put(tmu->clk); |
9570ef20 MD |
601 | return ret; |
602 | } | |
603 | ||
1850514b | 604 | static int sh_tmu_probe(struct platform_device *pdev) |
9570ef20 | 605 | { |
0a72aa39 | 606 | struct sh_tmu_device *tmu = platform_get_drvdata(pdev); |
9570ef20 MD |
607 | int ret; |
608 | ||
eaa49a8c | 609 | if (!is_early_platform_device(pdev)) { |
61a53bfa RW |
610 | pm_runtime_set_active(&pdev->dev); |
611 | pm_runtime_enable(&pdev->dev); | |
eaa49a8c | 612 | } |
2ee619f9 | 613 | |
0a72aa39 | 614 | if (tmu) { |
214a607a | 615 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
61a53bfa | 616 | goto out; |
9570ef20 MD |
617 | } |
618 | ||
3b77a83e | 619 | tmu = kzalloc(sizeof(*tmu), GFP_KERNEL); |
814876b0 | 620 | if (tmu == NULL) |
9570ef20 | 621 | return -ENOMEM; |
9570ef20 | 622 | |
0a72aa39 | 623 | ret = sh_tmu_setup(tmu, pdev); |
9570ef20 | 624 | if (ret) { |
0a72aa39 | 625 | kfree(tmu); |
61a53bfa RW |
626 | pm_runtime_idle(&pdev->dev); |
627 | return ret; | |
9570ef20 | 628 | } |
61a53bfa RW |
629 | if (is_early_platform_device(pdev)) |
630 | return 0; | |
631 | ||
632 | out: | |
8c7f21e6 | 633 | if (tmu->has_clockevent || tmu->has_clocksource) |
61a53bfa RW |
634 | pm_runtime_irq_safe(&pdev->dev); |
635 | else | |
636 | pm_runtime_idle(&pdev->dev); | |
637 | ||
638 | return 0; | |
9570ef20 MD |
639 | } |
640 | ||
1850514b | 641 | static int sh_tmu_remove(struct platform_device *pdev) |
9570ef20 MD |
642 | { |
643 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
644 | } | |
645 | ||
8c7f21e6 | 646 | static const struct platform_device_id sh_tmu_id_table[] = { |
8c7f21e6 LP |
647 | { "sh-tmu", SH_TMU }, |
648 | { "sh-tmu-sh3", SH_TMU_SH3 }, | |
649 | { } | |
650 | }; | |
651 | MODULE_DEVICE_TABLE(platform, sh_tmu_id_table); | |
652 | ||
3e29b554 LP |
653 | static const struct of_device_id sh_tmu_of_table[] __maybe_unused = { |
654 | { .compatible = "renesas,tmu" }, | |
655 | { } | |
656 | }; | |
657 | MODULE_DEVICE_TABLE(of, sh_tmu_of_table); | |
658 | ||
9570ef20 MD |
659 | static struct platform_driver sh_tmu_device_driver = { |
660 | .probe = sh_tmu_probe, | |
1850514b | 661 | .remove = sh_tmu_remove, |
9570ef20 MD |
662 | .driver = { |
663 | .name = "sh_tmu", | |
3e29b554 | 664 | .of_match_table = of_match_ptr(sh_tmu_of_table), |
8c7f21e6 LP |
665 | }, |
666 | .id_table = sh_tmu_id_table, | |
9570ef20 MD |
667 | }; |
668 | ||
669 | static int __init sh_tmu_init(void) | |
670 | { | |
671 | return platform_driver_register(&sh_tmu_device_driver); | |
672 | } | |
673 | ||
674 | static void __exit sh_tmu_exit(void) | |
675 | { | |
676 | platform_driver_unregister(&sh_tmu_device_driver); | |
677 | } | |
678 | ||
679 | early_platform_init("earlytimer", &sh_tmu_device_driver); | |
b9773c3f | 680 | subsys_initcall(sh_tmu_init); |
9570ef20 MD |
681 | module_exit(sh_tmu_exit); |
682 | ||
683 | MODULE_AUTHOR("Magnus Damm"); | |
684 | MODULE_DESCRIPTION("SuperH TMU Timer Driver"); | |
685 | MODULE_LICENSE("GPL v2"); |