Commit | Line | Data |
---|---|---|
3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
3fb1b6ad MD |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/err.h> | |
3f7e5e24 | 29 | #include <linux/delay.h> |
3fb1b6ad MD |
30 | #include <linux/clocksource.h> |
31 | #include <linux/clockchips.h> | |
46a12f74 | 32 | #include <linux/sh_timer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
7deeab5d | 34 | #include <linux/module.h> |
615a445f | 35 | #include <linux/pm_domain.h> |
bad81383 | 36 | #include <linux/pm_runtime.h> |
3fb1b6ad | 37 | |
2653caf4 | 38 | struct sh_cmt_device; |
7269f933 | 39 | |
2cda3ac4 LP |
40 | /* |
41 | * The CMT comes in 5 different identified flavours, depending not only on the | |
42 | * SoC but also on the particular instance. The following table lists the main | |
43 | * characteristics of those flavours. | |
44 | * | |
45 | * 16B 32B 32B-F 48B 48B-2 | |
46 | * ----------------------------------------------------------------------------- | |
47 | * Channels 2 1/4 1 6 2/8 | |
48 | * Control Width 16 16 16 16 32 | |
49 | * Counter Width 16 32 32 32/48 32/48 | |
50 | * Shared Start/Stop Y Y Y Y N | |
51 | * | |
52 | * The 48-bit gen2 version has a per-channel start/stop register located in the | |
53 | * channel registers block. All other versions have a shared start/stop register | |
54 | * located in the global space. | |
55 | * | |
56 | * Note that CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
57 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. | |
58 | */ | |
59 | ||
60 | enum sh_cmt_model { | |
61 | SH_CMT_16BIT, | |
62 | SH_CMT_32BIT, | |
63 | SH_CMT_32BIT_FAST, | |
64 | SH_CMT_48BIT, | |
65 | SH_CMT_48BIT_GEN2, | |
66 | }; | |
67 | ||
68 | struct sh_cmt_info { | |
69 | enum sh_cmt_model model; | |
70 | ||
71 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
72 | unsigned long overflow_bit; | |
73 | unsigned long clear_bits; | |
74 | ||
75 | /* callbacks for CMSTR and CMCSR access */ | |
76 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
77 | void (*write_control)(void __iomem *base, unsigned long offs, | |
78 | unsigned long value); | |
79 | ||
80 | /* callbacks for CMCNT and CMCOR access */ | |
81 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
82 | void (*write_count)(void __iomem *base, unsigned long offs, | |
83 | unsigned long value); | |
84 | }; | |
85 | ||
7269f933 | 86 | struct sh_cmt_channel { |
2653caf4 | 87 | struct sh_cmt_device *cmt; |
740a9518 | 88 | unsigned int index; |
3fb1b6ad | 89 | |
c924d2d2 LP |
90 | void __iomem *base; |
91 | ||
3fb1b6ad MD |
92 | unsigned long flags; |
93 | unsigned long match_value; | |
94 | unsigned long next_match_value; | |
95 | unsigned long max_match_value; | |
96 | unsigned long rate; | |
7d0c399f | 97 | raw_spinlock_t lock; |
3fb1b6ad | 98 | struct clock_event_device ced; |
19bdc9d0 | 99 | struct clocksource cs; |
3fb1b6ad | 100 | unsigned long total_cycles; |
bad81383 | 101 | bool cs_enabled; |
7269f933 LP |
102 | }; |
103 | ||
2653caf4 | 104 | struct sh_cmt_device { |
7269f933 LP |
105 | struct platform_device *pdev; |
106 | ||
2cda3ac4 LP |
107 | const struct sh_cmt_info *info; |
108 | ||
36f1ac98 | 109 | void __iomem *mapbase_ch; |
7269f933 | 110 | void __iomem *mapbase; |
7269f933 LP |
111 | struct clk *clk; |
112 | ||
f5ec9b19 LP |
113 | struct sh_cmt_channel *channels; |
114 | unsigned int num_channels; | |
3fb1b6ad MD |
115 | }; |
116 | ||
d14be99b LP |
117 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
118 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
119 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
120 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
121 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
122 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
123 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
124 | ||
125 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
126 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
127 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
128 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
129 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
130 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
131 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
132 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
133 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
134 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
135 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
136 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
137 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
138 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
139 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
140 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
141 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
142 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
143 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
144 | ||
a6a912ca | 145 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
146 | { |
147 | return ioread16(base + (offs << 1)); | |
148 | } | |
149 | ||
a6a912ca MD |
150 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
151 | { | |
152 | return ioread32(base + (offs << 2)); | |
153 | } | |
154 | ||
155 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
156 | unsigned long value) | |
587acb3d MD |
157 | { |
158 | iowrite16(value, base + (offs << 1)); | |
159 | } | |
3fb1b6ad | 160 | |
a6a912ca MD |
161 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
162 | unsigned long value) | |
163 | { | |
164 | iowrite32(value, base + (offs << 2)); | |
165 | } | |
166 | ||
2cda3ac4 LP |
167 | static const struct sh_cmt_info sh_cmt_info[] = { |
168 | [SH_CMT_16BIT] = { | |
169 | .model = SH_CMT_16BIT, | |
170 | .width = 16, | |
d14be99b LP |
171 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
172 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
173 | .read_control = sh_cmt_read16, |
174 | .write_control = sh_cmt_write16, | |
175 | .read_count = sh_cmt_read16, | |
176 | .write_count = sh_cmt_write16, | |
177 | }, | |
178 | [SH_CMT_32BIT] = { | |
179 | .model = SH_CMT_32BIT, | |
180 | .width = 32, | |
d14be99b LP |
181 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
182 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
183 | .read_control = sh_cmt_read16, |
184 | .write_control = sh_cmt_write16, | |
185 | .read_count = sh_cmt_read32, | |
186 | .write_count = sh_cmt_write32, | |
187 | }, | |
188 | [SH_CMT_32BIT_FAST] = { | |
189 | .model = SH_CMT_32BIT_FAST, | |
190 | .width = 32, | |
d14be99b LP |
191 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
192 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
193 | .read_control = sh_cmt_read16, |
194 | .write_control = sh_cmt_write16, | |
195 | .read_count = sh_cmt_read32, | |
196 | .write_count = sh_cmt_write32, | |
197 | }, | |
198 | [SH_CMT_48BIT] = { | |
199 | .model = SH_CMT_48BIT, | |
200 | .width = 32, | |
d14be99b LP |
201 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
202 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
203 | .read_control = sh_cmt_read32, |
204 | .write_control = sh_cmt_write32, | |
205 | .read_count = sh_cmt_read32, | |
206 | .write_count = sh_cmt_write32, | |
207 | }, | |
208 | [SH_CMT_48BIT_GEN2] = { | |
209 | .model = SH_CMT_48BIT_GEN2, | |
210 | .width = 32, | |
d14be99b LP |
211 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
212 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
213 | .read_control = sh_cmt_read32, |
214 | .write_control = sh_cmt_write32, | |
215 | .read_count = sh_cmt_read32, | |
216 | .write_count = sh_cmt_write32, | |
217 | }, | |
218 | }; | |
219 | ||
3fb1b6ad MD |
220 | #define CMCSR 0 /* channel register */ |
221 | #define CMCNT 1 /* channel register */ | |
222 | #define CMCOR 2 /* channel register */ | |
223 | ||
7269f933 | 224 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 225 | { |
2cda3ac4 | 226 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); |
1b56b96b MD |
227 | } |
228 | ||
7269f933 | 229 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 230 | { |
2cda3ac4 | 231 | return ch->cmt->info->read_control(ch->base, CMCSR); |
1b56b96b MD |
232 | } |
233 | ||
7269f933 | 234 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 235 | { |
2cda3ac4 | 236 | return ch->cmt->info->read_count(ch->base, CMCNT); |
3fb1b6ad MD |
237 | } |
238 | ||
7269f933 | 239 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
1b56b96b MD |
240 | unsigned long value) |
241 | { | |
2cda3ac4 | 242 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); |
1b56b96b MD |
243 | } |
244 | ||
7269f933 | 245 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
246 | unsigned long value) |
247 | { | |
2cda3ac4 | 248 | ch->cmt->info->write_control(ch->base, CMCSR, value); |
1b56b96b MD |
249 | } |
250 | ||
7269f933 | 251 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
252 | unsigned long value) |
253 | { | |
2cda3ac4 | 254 | ch->cmt->info->write_count(ch->base, CMCNT, value); |
1b56b96b MD |
255 | } |
256 | ||
7269f933 | 257 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
258 | unsigned long value) |
259 | { | |
2cda3ac4 | 260 | ch->cmt->info->write_count(ch->base, CMCOR, value); |
1b56b96b MD |
261 | } |
262 | ||
7269f933 | 263 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
264 | int *has_wrapped) |
265 | { | |
266 | unsigned long v1, v2, v3; | |
5b644c7a MD |
267 | int o1, o2; |
268 | ||
2cda3ac4 | 269 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
270 | |
271 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
272 | do { | |
5b644c7a | 273 | o2 = o1; |
7269f933 LP |
274 | v1 = sh_cmt_read_cmcnt(ch); |
275 | v2 = sh_cmt_read_cmcnt(ch); | |
276 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 277 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
278 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
279 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 280 | |
5b644c7a | 281 | *has_wrapped = o1; |
3fb1b6ad MD |
282 | return v2; |
283 | } | |
284 | ||
587acb3d | 285 | static DEFINE_RAW_SPINLOCK(sh_cmt_lock); |
3fb1b6ad | 286 | |
7269f933 | 287 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 288 | { |
7269f933 | 289 | struct sh_timer_config *cfg = ch->cmt->pdev->dev.platform_data; |
3fb1b6ad MD |
290 | unsigned long flags, value; |
291 | ||
292 | /* start stop register shared by multiple timer channels */ | |
7d0c399f | 293 | raw_spin_lock_irqsave(&sh_cmt_lock, flags); |
7269f933 | 294 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
295 | |
296 | if (start) | |
297 | value |= 1 << cfg->timer_bit; | |
298 | else | |
299 | value &= ~(1 << cfg->timer_bit); | |
300 | ||
7269f933 | 301 | sh_cmt_write_cmstr(ch, value); |
7d0c399f | 302 | raw_spin_unlock_irqrestore(&sh_cmt_lock, flags); |
3fb1b6ad MD |
303 | } |
304 | ||
7269f933 | 305 | static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) |
3fb1b6ad | 306 | { |
3f7e5e24 | 307 | int k, ret; |
3fb1b6ad | 308 | |
7269f933 LP |
309 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
310 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 311 | |
9436b4ab | 312 | /* enable clock */ |
7269f933 | 313 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 314 | if (ret) { |
740a9518 LP |
315 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
316 | ch->index); | |
3f7e5e24 | 317 | goto err0; |
3fb1b6ad | 318 | } |
3fb1b6ad MD |
319 | |
320 | /* make sure channel is disabled */ | |
7269f933 | 321 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
322 | |
323 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 324 | if (ch->cmt->info->width == 16) { |
7269f933 | 325 | *rate = clk_get_rate(ch->cmt->clk) / 512; |
d14be99b LP |
326 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
327 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 328 | } else { |
7269f933 | 329 | *rate = clk_get_rate(ch->cmt->clk) / 8; |
d14be99b LP |
330 | sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | |
331 | SH_CMT32_CMCSR_CMTOUT_IE | | |
332 | SH_CMT32_CMCSR_CMR_IRQ | | |
333 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 334 | } |
3fb1b6ad | 335 | |
7269f933 LP |
336 | sh_cmt_write_cmcor(ch, 0xffffffff); |
337 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 338 | |
3f7e5e24 MD |
339 | /* |
340 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
341 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
342 | * modifying CMCNT register; two RCLK cycles are necessary before | |
343 | * this register is either read or any modification of the value | |
344 | * it holds is reflected in the LSI's actual operation. | |
345 | * | |
346 | * While at it, we're supposed to clear out the CMCNT as of this | |
347 | * moment, so make sure it's processed properly here. This will | |
348 | * take RCLKx2 at maximum. | |
349 | */ | |
350 | for (k = 0; k < 100; k++) { | |
7269f933 | 351 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
352 | break; |
353 | udelay(1); | |
354 | } | |
355 | ||
7269f933 | 356 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
357 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
358 | ch->index); | |
3f7e5e24 MD |
359 | ret = -ETIMEDOUT; |
360 | goto err1; | |
361 | } | |
362 | ||
3fb1b6ad | 363 | /* enable channel */ |
7269f933 | 364 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 365 | return 0; |
3f7e5e24 MD |
366 | err1: |
367 | /* stop clock */ | |
7269f933 | 368 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
369 | |
370 | err0: | |
371 | return ret; | |
3fb1b6ad MD |
372 | } |
373 | ||
7269f933 | 374 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
375 | { |
376 | /* disable channel */ | |
7269f933 | 377 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 378 | |
be890a1a | 379 | /* disable interrupts in CMT block */ |
7269f933 | 380 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 381 | |
9436b4ab | 382 | /* stop clock */ |
7269f933 | 383 | clk_disable(ch->cmt->clk); |
bad81383 | 384 | |
7269f933 LP |
385 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
386 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
387 | } |
388 | ||
389 | /* private flags */ | |
390 | #define FLAG_CLOCKEVENT (1 << 0) | |
391 | #define FLAG_CLOCKSOURCE (1 << 1) | |
392 | #define FLAG_REPROGRAM (1 << 2) | |
393 | #define FLAG_SKIPEVENT (1 << 3) | |
394 | #define FLAG_IRQCONTEXT (1 << 4) | |
395 | ||
7269f933 | 396 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
397 | int absolute) |
398 | { | |
399 | unsigned long new_match; | |
7269f933 | 400 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
401 | unsigned long delay = 0; |
402 | unsigned long now = 0; | |
403 | int has_wrapped; | |
404 | ||
7269f933 LP |
405 | now = sh_cmt_get_counter(ch, &has_wrapped); |
406 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
407 | |
408 | if (has_wrapped) { | |
409 | /* we're competing with the interrupt handler. | |
410 | * -> let the interrupt handler reprogram the timer. | |
411 | * -> interrupt number two handles the event. | |
412 | */ | |
7269f933 | 413 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
414 | return; |
415 | } | |
416 | ||
417 | if (absolute) | |
418 | now = 0; | |
419 | ||
420 | do { | |
421 | /* reprogram the timer hardware, | |
422 | * but don't save the new match value yet. | |
423 | */ | |
424 | new_match = now + value + delay; | |
7269f933 LP |
425 | if (new_match > ch->max_match_value) |
426 | new_match = ch->max_match_value; | |
3fb1b6ad | 427 | |
7269f933 | 428 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 429 | |
7269f933 LP |
430 | now = sh_cmt_get_counter(ch, &has_wrapped); |
431 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
432 | /* we are changing to a greater match value, |
433 | * so this wrap must be caused by the counter | |
434 | * matching the old value. | |
435 | * -> first interrupt reprograms the timer. | |
436 | * -> interrupt number two handles the event. | |
437 | */ | |
7269f933 | 438 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
439 | break; |
440 | } | |
441 | ||
442 | if (has_wrapped) { | |
443 | /* we are changing to a smaller match value, | |
444 | * so the wrap must be caused by the counter | |
445 | * matching the new value. | |
446 | * -> save programmed match value. | |
447 | * -> let isr handle the event. | |
448 | */ | |
7269f933 | 449 | ch->match_value = new_match; |
3fb1b6ad MD |
450 | break; |
451 | } | |
452 | ||
453 | /* be safe: verify hardware settings */ | |
454 | if (now < new_match) { | |
455 | /* timer value is below match value, all good. | |
456 | * this makes sure we won't miss any match events. | |
457 | * -> save programmed match value. | |
458 | * -> let isr handle the event. | |
459 | */ | |
7269f933 | 460 | ch->match_value = new_match; |
3fb1b6ad MD |
461 | break; |
462 | } | |
463 | ||
464 | /* the counter has reached a value greater | |
465 | * than our new match value. and since the | |
466 | * has_wrapped flag isn't set we must have | |
467 | * programmed a too close event. | |
468 | * -> increase delay and retry. | |
469 | */ | |
470 | if (delay) | |
471 | delay <<= 1; | |
472 | else | |
473 | delay = 1; | |
474 | ||
475 | if (!delay) | |
740a9518 LP |
476 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
477 | ch->index); | |
3fb1b6ad MD |
478 | |
479 | } while (delay); | |
480 | } | |
481 | ||
7269f933 | 482 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 483 | { |
7269f933 | 484 | if (delta > ch->max_match_value) |
740a9518 LP |
485 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
486 | ch->index); | |
3fb1b6ad | 487 | |
7269f933 LP |
488 | ch->next_match_value = delta; |
489 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
490 | } |
491 | ||
7269f933 | 492 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
493 | { |
494 | unsigned long flags; | |
495 | ||
7269f933 LP |
496 | raw_spin_lock_irqsave(&ch->lock, flags); |
497 | __sh_cmt_set_next(ch, delta); | |
498 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
499 | } |
500 | ||
501 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
502 | { | |
7269f933 | 503 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
504 | |
505 | /* clear flags */ | |
2cda3ac4 LP |
506 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
507 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
508 | |
509 | /* update clock source counter to begin with if enabled | |
510 | * the wrap flag should be cleared by the timer specific | |
511 | * isr before we end up here. | |
512 | */ | |
7269f933 LP |
513 | if (ch->flags & FLAG_CLOCKSOURCE) |
514 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 515 | |
7269f933 LP |
516 | if (!(ch->flags & FLAG_REPROGRAM)) |
517 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 518 | |
7269f933 | 519 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 520 | |
7269f933 LP |
521 | if (ch->flags & FLAG_CLOCKEVENT) { |
522 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
523 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
524 | ch->next_match_value = ch->max_match_value; | |
525 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
526 | } |
527 | ||
7269f933 | 528 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
529 | } |
530 | } | |
531 | ||
7269f933 | 532 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 533 | |
7269f933 LP |
534 | if (ch->flags & FLAG_REPROGRAM) { |
535 | ch->flags &= ~FLAG_REPROGRAM; | |
536 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 537 | |
7269f933 LP |
538 | if (ch->flags & FLAG_CLOCKEVENT) |
539 | if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
540 | || (ch->match_value == ch->next_match_value)) | |
541 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
542 | } |
543 | ||
7269f933 | 544 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
545 | |
546 | return IRQ_HANDLED; | |
547 | } | |
548 | ||
7269f933 | 549 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
550 | { |
551 | int ret = 0; | |
552 | unsigned long flags; | |
553 | ||
7269f933 | 554 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 555 | |
7269f933 LP |
556 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
557 | ret = sh_cmt_enable(ch, &ch->rate); | |
3fb1b6ad MD |
558 | |
559 | if (ret) | |
560 | goto out; | |
7269f933 | 561 | ch->flags |= flag; |
3fb1b6ad MD |
562 | |
563 | /* setup timeout if no clockevent */ | |
7269f933 LP |
564 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
565 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 566 | out: |
7269f933 | 567 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
568 | |
569 | return ret; | |
570 | } | |
571 | ||
7269f933 | 572 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
573 | { |
574 | unsigned long flags; | |
575 | unsigned long f; | |
576 | ||
7269f933 | 577 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 578 | |
7269f933 LP |
579 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
580 | ch->flags &= ~flag; | |
3fb1b6ad | 581 | |
7269f933 LP |
582 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
583 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
584 | |
585 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
586 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
587 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 588 | |
7269f933 | 589 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
590 | } |
591 | ||
7269f933 | 592 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 593 | { |
7269f933 | 594 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
595 | } |
596 | ||
597 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
598 | { | |
7269f933 | 599 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
600 | unsigned long flags, raw; |
601 | unsigned long value; | |
602 | int has_wrapped; | |
603 | ||
7269f933 LP |
604 | raw_spin_lock_irqsave(&ch->lock, flags); |
605 | value = ch->total_cycles; | |
606 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
607 | |
608 | if (unlikely(has_wrapped)) | |
7269f933 LP |
609 | raw += ch->match_value + 1; |
610 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
611 | |
612 | return value + raw; | |
613 | } | |
614 | ||
615 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
616 | { | |
3593f5fe | 617 | int ret; |
7269f933 | 618 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 619 | |
7269f933 | 620 | WARN_ON(ch->cs_enabled); |
bad81383 | 621 | |
7269f933 | 622 | ch->total_cycles = 0; |
19bdc9d0 | 623 | |
7269f933 | 624 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
bad81383 | 625 | if (!ret) { |
7269f933 LP |
626 | __clocksource_updatefreq_hz(cs, ch->rate); |
627 | ch->cs_enabled = true; | |
bad81383 | 628 | } |
3593f5fe | 629 | return ret; |
19bdc9d0 MD |
630 | } |
631 | ||
632 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
633 | { | |
7269f933 | 634 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 635 | |
7269f933 | 636 | WARN_ON(!ch->cs_enabled); |
bad81383 | 637 | |
7269f933 LP |
638 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
639 | ch->cs_enabled = false; | |
19bdc9d0 MD |
640 | } |
641 | ||
9bb5ec88 RW |
642 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
643 | { | |
7269f933 | 644 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 645 | |
7269f933 LP |
646 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
647 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
648 | } |
649 | ||
c8162884 MD |
650 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
651 | { | |
7269f933 | 652 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 653 | |
7269f933 LP |
654 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
655 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
656 | } |
657 | ||
7269f933 | 658 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
1d053e1d | 659 | const char *name, unsigned long rating) |
19bdc9d0 | 660 | { |
7269f933 | 661 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
662 | |
663 | cs->name = name; | |
664 | cs->rating = rating; | |
665 | cs->read = sh_cmt_clocksource_read; | |
666 | cs->enable = sh_cmt_clocksource_enable; | |
667 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 668 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 669 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
670 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
671 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 672 | |
740a9518 LP |
673 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
674 | ch->index); | |
f4d7c356 | 675 | |
3593f5fe MD |
676 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ |
677 | clocksource_register_hz(cs, 1); | |
19bdc9d0 MD |
678 | return 0; |
679 | } | |
680 | ||
7269f933 | 681 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 682 | { |
7269f933 | 683 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
684 | } |
685 | ||
7269f933 | 686 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 687 | { |
7269f933 | 688 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad | 689 | |
7269f933 | 690 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
691 | |
692 | /* TODO: calculate good shift from rate and counter bit width */ | |
693 | ||
694 | ced->shift = 32; | |
7269f933 LP |
695 | ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift); |
696 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
3fb1b6ad MD |
697 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
698 | ||
699 | if (periodic) | |
7269f933 | 700 | sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 701 | else |
7269f933 | 702 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
703 | } |
704 | ||
705 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
706 | struct clock_event_device *ced) | |
707 | { | |
7269f933 | 708 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
709 | |
710 | /* deal with old setting first */ | |
711 | switch (ced->mode) { | |
712 | case CLOCK_EVT_MODE_PERIODIC: | |
713 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 714 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
715 | break; |
716 | default: | |
717 | break; | |
718 | } | |
719 | ||
720 | switch (mode) { | |
721 | case CLOCK_EVT_MODE_PERIODIC: | |
7269f933 | 722 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 723 | "ch%u: used for periodic clock events\n", ch->index); |
7269f933 | 724 | sh_cmt_clock_event_start(ch, 1); |
3fb1b6ad MD |
725 | break; |
726 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 727 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 728 | "ch%u: used for oneshot clock events\n", ch->index); |
7269f933 | 729 | sh_cmt_clock_event_start(ch, 0); |
3fb1b6ad MD |
730 | break; |
731 | case CLOCK_EVT_MODE_SHUTDOWN: | |
732 | case CLOCK_EVT_MODE_UNUSED: | |
7269f933 | 733 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
734 | break; |
735 | default: | |
736 | break; | |
737 | } | |
738 | } | |
739 | ||
740 | static int sh_cmt_clock_event_next(unsigned long delta, | |
741 | struct clock_event_device *ced) | |
742 | { | |
7269f933 | 743 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
744 | |
745 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
7269f933 LP |
746 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
747 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 748 | else |
7269f933 | 749 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
750 | |
751 | return 0; | |
752 | } | |
753 | ||
9bb5ec88 RW |
754 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
755 | { | |
7269f933 | 756 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 757 | |
7269f933 LP |
758 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
759 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
760 | } |
761 | ||
762 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
763 | { | |
7269f933 | 764 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 765 | |
7269f933 LP |
766 | clk_prepare(ch->cmt->clk); |
767 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
768 | } |
769 | ||
7269f933 | 770 | static void sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
1d053e1d | 771 | const char *name, unsigned long rating) |
3fb1b6ad | 772 | { |
7269f933 | 773 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad | 774 | |
3fb1b6ad MD |
775 | ced->name = name; |
776 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
777 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
778 | ced->rating = rating; | |
f1ebe1e4 | 779 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad MD |
780 | ced->set_next_event = sh_cmt_clock_event_next; |
781 | ced->set_mode = sh_cmt_clock_event_mode; | |
9bb5ec88 RW |
782 | ced->suspend = sh_cmt_clock_event_suspend; |
783 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 784 | |
740a9518 LP |
785 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
786 | ch->index); | |
3fb1b6ad MD |
787 | clockevents_register_device(ced); |
788 | } | |
789 | ||
1d053e1d | 790 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
d1fcc0a8 PM |
791 | unsigned long clockevent_rating, |
792 | unsigned long clocksource_rating) | |
3fb1b6ad | 793 | { |
3fb1b6ad | 794 | if (clockevent_rating) |
7269f933 | 795 | sh_cmt_register_clockevent(ch, name, clockevent_rating); |
3fb1b6ad | 796 | |
19bdc9d0 | 797 | if (clocksource_rating) |
7269f933 | 798 | sh_cmt_register_clocksource(ch, name, clocksource_rating); |
19bdc9d0 | 799 | |
3fb1b6ad MD |
800 | return 0; |
801 | } | |
802 | ||
740a9518 | 803 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
b882e7b1 LP |
804 | struct sh_cmt_device *cmt) |
805 | { | |
806 | struct sh_timer_config *cfg = cmt->pdev->dev.platform_data; | |
807 | int irq; | |
808 | int ret; | |
809 | ||
b882e7b1 | 810 | ch->cmt = cmt; |
c924d2d2 | 811 | ch->base = cmt->mapbase_ch; |
740a9518 | 812 | ch->index = index; |
b882e7b1 LP |
813 | |
814 | irq = platform_get_irq(cmt->pdev, 0); | |
815 | if (irq < 0) { | |
740a9518 LP |
816 | dev_err(&cmt->pdev->dev, "ch%u: failed to get irq\n", |
817 | ch->index); | |
b882e7b1 LP |
818 | return irq; |
819 | } | |
820 | ||
2cda3ac4 | 821 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
822 | ch->max_match_value = ~0; |
823 | else | |
2cda3ac4 | 824 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
825 | |
826 | ch->match_value = ch->max_match_value; | |
827 | raw_spin_lock_init(&ch->lock); | |
828 | ||
1d053e1d | 829 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
b882e7b1 LP |
830 | cfg->clockevent_rating, |
831 | cfg->clocksource_rating); | |
832 | if (ret) { | |
740a9518 LP |
833 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
834 | ch->index); | |
b882e7b1 LP |
835 | return ret; |
836 | } | |
837 | ch->cs_enabled = false; | |
838 | ||
839 | ret = request_irq(irq, sh_cmt_interrupt, | |
840 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
841 | dev_name(&cmt->pdev->dev), ch); | |
842 | if (ret) { | |
740a9518 LP |
843 | dev_err(&cmt->pdev->dev, "ch%u: failed to request irq %d\n", |
844 | ch->index, irq); | |
b882e7b1 LP |
845 | return ret; |
846 | } | |
847 | ||
848 | return 0; | |
849 | } | |
850 | ||
2653caf4 | 851 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
3fb1b6ad | 852 | { |
46a12f74 | 853 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
8874c5e3 | 854 | struct resource *res, *res2; |
b882e7b1 | 855 | int ret; |
3fb1b6ad MD |
856 | ret = -ENXIO; |
857 | ||
2653caf4 | 858 | cmt->pdev = pdev; |
3fb1b6ad MD |
859 | |
860 | if (!cfg) { | |
2653caf4 | 861 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
3fb1b6ad MD |
862 | goto err0; |
863 | } | |
864 | ||
2653caf4 | 865 | res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
3fb1b6ad | 866 | if (!res) { |
2653caf4 | 867 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); |
3fb1b6ad MD |
868 | goto err0; |
869 | } | |
870 | ||
8874c5e3 | 871 | /* optional resource for the shared timer start/stop register */ |
2653caf4 | 872 | res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1); |
8874c5e3 | 873 | |
36f1ac98 LP |
874 | /* map memory, let mapbase_ch point to our channel */ |
875 | cmt->mapbase_ch = ioremap_nocache(res->start, resource_size(res)); | |
876 | if (cmt->mapbase_ch == NULL) { | |
2653caf4 | 877 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); |
3fb1b6ad MD |
878 | goto err0; |
879 | } | |
880 | ||
8874c5e3 | 881 | /* map second resource for CMSTR */ |
36f1ac98 LP |
882 | cmt->mapbase = ioremap_nocache(res2 ? res2->start : |
883 | res->start - cfg->channel_offset, | |
884 | res2 ? resource_size(res2) : 2); | |
885 | if (cmt->mapbase == NULL) { | |
2653caf4 | 886 | dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n"); |
8874c5e3 MD |
887 | goto err1; |
888 | } | |
889 | ||
3fb1b6ad | 890 | /* get hold of clock */ |
2653caf4 LP |
891 | cmt->clk = clk_get(&cmt->pdev->dev, "cmt_fck"); |
892 | if (IS_ERR(cmt->clk)) { | |
893 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
894 | ret = PTR_ERR(cmt->clk); | |
8874c5e3 | 895 | goto err2; |
3fb1b6ad MD |
896 | } |
897 | ||
2653caf4 | 898 | ret = clk_prepare(cmt->clk); |
57dee992 LP |
899 | if (ret < 0) |
900 | goto err3; | |
901 | ||
2cda3ac4 LP |
902 | /* identify the model based on the resources */ |
903 | if (resource_size(res) == 6) | |
904 | cmt->info = &sh_cmt_info[SH_CMT_16BIT]; | |
905 | else if (res2 && (resource_size(res2) == 4)) | |
906 | cmt->info = &sh_cmt_info[SH_CMT_48BIT_GEN2]; | |
907 | else | |
908 | cmt->info = &sh_cmt_info[SH_CMT_32BIT]; | |
3fb1b6ad | 909 | |
f5ec9b19 LP |
910 | cmt->channels = kzalloc(sizeof(*cmt->channels), GFP_KERNEL); |
911 | if (cmt->channels == NULL) { | |
912 | ret = -ENOMEM; | |
913 | goto err4; | |
914 | } | |
915 | ||
916 | cmt->num_channels = 1; | |
917 | ||
918 | ret = sh_cmt_setup_channel(&cmt->channels[0], cfg->timer_bit, cmt); | |
b882e7b1 | 919 | if (ret < 0) |
57dee992 | 920 | goto err4; |
da64c2a8 | 921 | |
2653caf4 | 922 | platform_set_drvdata(pdev, cmt); |
adccc69e | 923 | |
da64c2a8 | 924 | return 0; |
57dee992 | 925 | err4: |
f5ec9b19 | 926 | kfree(cmt->channels); |
2653caf4 | 927 | clk_unprepare(cmt->clk); |
8874c5e3 | 928 | err3: |
2653caf4 | 929 | clk_put(cmt->clk); |
8874c5e3 | 930 | err2: |
2653caf4 | 931 | iounmap(cmt->mapbase); |
36f1ac98 LP |
932 | err1: |
933 | iounmap(cmt->mapbase_ch); | |
da64c2a8 | 934 | err0: |
3fb1b6ad MD |
935 | return ret; |
936 | } | |
937 | ||
1850514b | 938 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 939 | { |
2653caf4 | 940 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
bad81383 | 941 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
3fb1b6ad MD |
942 | int ret; |
943 | ||
9bb5ec88 | 944 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
945 | pm_runtime_set_active(&pdev->dev); |
946 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 947 | } |
615a445f | 948 | |
2653caf4 | 949 | if (cmt) { |
214a607a | 950 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 951 | goto out; |
e475eedb MD |
952 | } |
953 | ||
b262bc74 | 954 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
2653caf4 | 955 | if (cmt == NULL) { |
3fb1b6ad MD |
956 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
957 | return -ENOMEM; | |
958 | } | |
959 | ||
2653caf4 | 960 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 961 | if (ret) { |
2653caf4 | 962 | kfree(cmt); |
bad81383 RW |
963 | pm_runtime_idle(&pdev->dev); |
964 | return ret; | |
3fb1b6ad | 965 | } |
bad81383 RW |
966 | if (is_early_platform_device(pdev)) |
967 | return 0; | |
968 | ||
969 | out: | |
970 | if (cfg->clockevent_rating || cfg->clocksource_rating) | |
971 | pm_runtime_irq_safe(&pdev->dev); | |
972 | else | |
973 | pm_runtime_idle(&pdev->dev); | |
974 | ||
975 | return 0; | |
3fb1b6ad MD |
976 | } |
977 | ||
1850514b | 978 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
979 | { |
980 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
981 | } | |
982 | ||
983 | static struct platform_driver sh_cmt_device_driver = { | |
984 | .probe = sh_cmt_probe, | |
1850514b | 985 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
986 | .driver = { |
987 | .name = "sh_cmt", | |
988 | } | |
989 | }; | |
990 | ||
991 | static int __init sh_cmt_init(void) | |
992 | { | |
993 | return platform_driver_register(&sh_cmt_device_driver); | |
994 | } | |
995 | ||
996 | static void __exit sh_cmt_exit(void) | |
997 | { | |
998 | platform_driver_unregister(&sh_cmt_device_driver); | |
999 | } | |
1000 | ||
e475eedb | 1001 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 1002 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1003 | module_exit(sh_cmt_exit); |
1004 | ||
1005 | MODULE_AUTHOR("Magnus Damm"); | |
1006 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1007 | MODULE_LICENSE("GPL v2"); |